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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
9fa32b12 | 2 | /* |
1537d386 PC |
3 | * Copyright (C) 2014, STMicroelectronics - All Rights Reserved |
4 | * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. | |
9fa32b12 VM |
5 | */ |
6 | ||
7 | #ifndef _STV0991_CREG_H | |
8 | #define _STV0991_CREG_H | |
9 | ||
10 | struct stv0991_creg { | |
11 | u32 version; /* offset 0x0 */ | |
12 | u32 hdpctl; /* offset 0x4 */ | |
13 | u32 hdpval; /* offset 0x8 */ | |
14 | u32 hdpgposet; /* offset 0xc */ | |
15 | u32 hdpgpoclr; /* offset 0x10 */ | |
16 | u32 hdpgpoval; /* offset 0x14 */ | |
17 | u32 stm_mux; /* offset 0x18 */ | |
18 | u32 sysctrl_1; /* offset 0x1c */ | |
19 | u32 sysctrl_2; /* offset 0x20 */ | |
20 | u32 sysctrl_3; /* offset 0x24 */ | |
21 | u32 sysctrl_4; /* offset 0x28 */ | |
22 | u32 reserved_1[0x35]; /* offset 0x2C-0xFC */ | |
23 | u32 mux1; /* offset 0x100 */ | |
24 | u32 mux2; /* offset 0x104 */ | |
25 | u32 mux3; /* offset 0x108 */ | |
26 | u32 mux4; /* offset 0x10c */ | |
27 | u32 mux5; /* offset 0x110 */ | |
28 | u32 mux6; /* offset 0x114 */ | |
29 | u32 mux7; /* offset 0x118 */ | |
30 | u32 mux8; /* offset 0x11c */ | |
31 | u32 mux9; /* offset 0x120 */ | |
32 | u32 mux10; /* offset 0x124 */ | |
33 | u32 mux11; /* offset 0x128 */ | |
34 | u32 mux12; /* offset 0x12c */ | |
35 | u32 mux13; /* offset 0x130 */ | |
36 | u32 reserved_2[0x33]; /* offset 0x134-0x1FC */ | |
37 | u32 cfg_pad1; /* offset 0x200 */ | |
38 | u32 cfg_pad2; /* offset 0x204 */ | |
39 | u32 cfg_pad3; /* offset 0x208 */ | |
40 | u32 cfg_pad4; /* offset 0x20c */ | |
41 | u32 cfg_pad5; /* offset 0x210 */ | |
42 | u32 cfg_pad6; /* offset 0x214 */ | |
43 | u32 cfg_pad7; /* offset 0x218 */ | |
44 | u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */ | |
45 | u32 vdd_pad1; /* offset 0x300 */ | |
46 | u32 vdd_pad2; /* offset 0x304 */ | |
47 | u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */ | |
48 | u32 vdd_comp1; /* offset 0x400 */ | |
49 | }; | |
50 | ||
54afb500 VM |
51 | /* CREG MUX 13 register */ |
52 | #define FLASH_CS_NC_SHIFT 4 | |
53 | #define FLASH_CS_NC_MASK ~(7 << FLASH_CS_NC_SHIFT) | |
54 | #define CFG_FLASH_CS_NC (0 << FLASH_CS_NC_SHIFT) | |
55 | ||
56 | #define FLASH_CLK_SHIFT 0 | |
57 | #define FLASH_CLK_MASK ~(7 << FLASH_CLK_SHIFT) | |
58 | #define CFG_FLASH_CLK (0 << FLASH_CLK_SHIFT) | |
59 | ||
9fa32b12 VM |
60 | /* CREG MUX 12 register */ |
61 | #define GPIOC_30_MUX_SHIFT 24 | |
62 | #define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT) | |
63 | #define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT) | |
64 | ||
65 | #define GPIOC_31_MUX_SHIFT 28 | |
66 | #define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT) | |
67 | #define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT) | |
68 | ||
69 | /* CREG MUX 7 register */ | |
70 | #define GPIOB_16_MUX_SHIFT 0 | |
71 | #define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT) | |
72 | #define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT) | |
73 | ||
74 | #define GPIOB_17_MUX_SHIFT 4 | |
75 | #define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT) | |
76 | #define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT) | |
77 | ||
78 | /* CREG CFG_PAD6 register */ | |
79 | ||
80 | #define GPIOC_31_MODE_SHIFT 30 | |
81 | #define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT) | |
82 | #define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT) | |
83 | #define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT) | |
84 | ||
85 | #define GPIOC_30_MODE_SHIFT 28 | |
86 | #define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT) | |
87 | #define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT) | |
88 | #define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT) | |
89 | ||
2ce4eaf4 VM |
90 | /* CREG Ethernet pad config */ |
91 | ||
92 | #define VDD_ETH_PS_1V8 0 | |
93 | #define VDD_ETH_PS_2V5 2 | |
94 | #define VDD_ETH_PS_3V3 3 | |
95 | #define VDD_ETH_PS_MASK 0x3 | |
96 | ||
97 | #define VDD_ETH_PS_SHIFT 12 | |
98 | #define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT) | |
99 | ||
100 | #define VDD_ETH_M_PS_SHIFT 28 | |
101 | #define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT) | |
102 | ||
9fa32b12 | 103 | #endif |