[people/ms/u-boot.git] / arch / arm / include / asm / arch-sunxi / clock_sun6i.h

/*
 * sun6i clock register definitions
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _SUNXI_CLOCK_SUN6I_H
#define _SUNXI_CLOCK_SUN6I_H

struct sunxi_ccm_reg {
	u32 pll1_cfg;		/* 0x00 pll1 control */
	u32 reserved0;
	u32 pll2_cfg;		/* 0x08 pll2 control */
	u32 reserved1;
	u32 pll3_cfg;		/* 0x10 pll3 control */
	u32 reserved2;
	u32 pll4_cfg;		/* 0x18 pll4 control */
	u32 reserved3;
	u32 pll5_cfg;		/* 0x20 pll5 control */
	u32 reserved4;
	u32 pll6_cfg;		/* 0x28 pll6 control */
	u32 reserved5;
	u32 pll7_cfg;		/* 0x30 pll7 control */
	u32 reserved6;
	u32 pll8_cfg;		/* 0x38 pll8 control */
	u32 reserved7;
	u32 mipi_pll_cfg;	/* 0x40 MIPI pll control */
	u32 pll9_cfg;		/* 0x44 pll9 control */
	u32 pll10_cfg;		/* 0x48 pll10 control */
	u32 reserved8;
	u32 cpu_axi_cfg;	/* 0x50 CPU/AXI divide ratio */
	u32 ahb1_apb1_div;	/* 0x54 AHB1/APB1 divide ratio */
	u32 apb2_div;		/* 0x58 APB2 divide ratio */
	u32 axi_gate;		/* 0x5c axi module clock gating */
	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
	u32 apb1_gate;		/* 0x68 apb1 module clock gating */
	u32 apb2_gate;		/* 0x6c apb2 module clock gating */
	u32 reserved9[4];
	u32 nand0_clk_cfg;	/* 0x80 nand0 clock control */
	u32 nand1_clk_cfg;	/* 0x84 nand1 clock control */
	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
	u32 ts_clk_cfg;		/* 0x98 transport stream clock control */
	u32 ss_clk_cfg;		/* 0x9c security system clock control */
	u32 spi0_clk_cfg;	/* 0xa0 spi0 clock control */
	u32 spi1_clk_cfg;	/* 0xa4 spi1 clock control */
	u32 spi2_clk_cfg;	/* 0xa8 spi2 clock control */
	u32 spi3_clk_cfg;	/* 0xac spi3 clock control */
	u32 i2s0_clk_cfg;	/* 0xb0 I2S0 clock control*/
	u32 i2s1_clk_cfg;	/* 0xb4 I2S1 clock control */
	u32 reserved10[2];
	u32 spdif_clk_cfg;	/* 0xc0 SPDIF clock control */
	u32 reserved11[2];
	u32 usb_clk_cfg;	/* 0xcc USB clock control */
	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control */
	u32 reserved12[7];
	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
	u32 reserved13[2];
	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
	u32 mp_clk_cfg;		/* 0x114 MP module clock */
	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
	u32 reserved14[3];
	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
	u32 lcd1_ch1_clk_cfg;	/* 0x130 LCD1 CH1 module clock */
	u32 csi0_clk_cfg;	/* 0x134 CSI0 module clock */
	u32 csi1_clk_cfg;	/* 0x138 CSI1 module clock */
	u32 ve_clk_cfg;		/* 0x13c VE module clock */
	u32 adda_clk_cfg;	/* 0x140 ADDA module clock */
	u32 avs_clk_cfg;	/* 0x144 AVS module clock */
	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
	u32 reserved15;
	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
	u32 ps_clk_cfg;		/* 0x154 PS module clock */
	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
	u32 reserved16;
	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
	u32 reserved17[4];
	u32 iep_drc0_clk_cfg;	/* 0x180 IEP DRC0 module clock */
	u32 iep_drc1_clk_cfg;	/* 0x184 IEP DRC1 module clock */
	u32 iep_deu0_clk_cfg;	/* 0x188 IEP DEU0 module clock */
	u32 iep_deu1_clk_cfg;	/* 0x18c IEP DEU1 module clock */
	u32 reserved18[4];
	u32 gpu_core_clk_cfg;	/* 0x1a0 GPU core clock config */
	u32 gpu_mem_clk_cfg;	/* 0x1a4 GPU memory clock config */
	u32 gpu_hyd_clk_cfg;	/* 0x1a0 GPU HYD clock config */
	u32 reserved19[21];
	u32 pll_lock;		/* 0x200 PLL Lock Time */
	u32 pll1_lock;		/* 0x204 PLL1 Lock Time */
	u32 reserved20[6];
	u32 pll1_bias_cfg;	/* 0x220 PLL1 Bias config */
	u32 pll2_bias_cfg;	/* 0x224 PLL2 Bias config */
	u32 pll3_bias_cfg;	/* 0x228 PLL3 Bias config */
	u32 pll4_bias_cfg;	/* 0x22c PLL4 Bias config */
	u32 pll5_bias_cfg;	/* 0x230 PLL5 Bias config */
	u32 pll6_bias_cfg;	/* 0x234 PLL6 Bias config */
	u32 pll7_bias_cfg;	/* 0x238 PLL7 Bias config */
	u32 pll8_bias_cfg;	/* 0x23c PLL8 Bias config */
	u32 mipi_bias_cfg;	/* 0x240 MIPI Bias config */
	u32 pll9_bias_cfg;	/* 0x244 PLL9 Bias config */
	u32 pll10_bias_cfg;	/* 0x248 PLL10 Bias config */
	u32 reserved21[13];
	u32 pll1_pattern_cfg;	/* 0x280 PLL1 Pattern config */
	u32 pll2_pattern_cfg;	/* 0x284 PLL2 Pattern config */
	u32 pll3_pattern_cfg;	/* 0x288 PLL3 Pattern config */
	u32 pll4_pattern_cfg;	/* 0x28c PLL4 Pattern config */
	u32 pll5_pattern_cfg;	/* 0x290 PLL5 Pattern config */
	u32 pll6_pattern_cfg;	/* 0x294 PLL6 Pattern config */
	u32 pll7_pattern_cfg;	/* 0x298 PLL7 Pattern config */
	u32 pll8_pattern_cfg;	/* 0x29c PLL8 Pattern config */
	u32 mipi_pattern_cfg;	/* 0x2a0 MIPI Pattern config */
	u32 pll9_pattern_cfg;	/* 0x2a4 PLL9 Pattern config */
	u32 pll10_pattern_cfg;	/* 0x2a8 PLL10 Pattern config */
	u32 reserved22[5];
	u32 ahb_reset0_cfg;	/* 0x2c0 AHB1 Reset 0 config */
	u32 ahb_reset1_cfg;	/* 0x2c4 AHB1 Reset 1 config */
	u32 ahb_reset2_cfg;	/* 0x2c8 AHB1 Reset 2 config */
	u32 reserved23;
	u32 apb1_reset_cfg;	/* 0x2d0 APB1 Reset config */
	u32 reserved24;
	u32 apb2_reset_cfg;	/* 0x2d8 APB2 Reset config */
};

/* apb2 bit field */
#define APB2_CLK_SRC_LOSC		(0x0 << 24)
#define APB2_CLK_SRC_OSC24M		(0x1 << 24)
#define APB2_CLK_SRC_PLL6		(0x2 << 24)
#define APB2_CLK_SRC_MASK		(0x3 << 24)
#define APB2_CLK_RATE_N_1		(0x0 << 16)
#define APB2_CLK_RATE_N_2		(0x1 << 16)
#define APB2_CLK_RATE_N_4		(0x2 << 16)
#define APB2_CLK_RATE_N_8		(0x3 << 16)
#define APB2_CLK_RATE_N_MASK		(3 << 16)
#define APB2_CLK_RATE_M(m)		(((m)-1) << 0)
#define APB2_CLK_RATE_M_MASK            (0x1f << 0)

/* apb2 gate field */
#define APB2_GATE_UART_SHIFT	(16)
#define APB2_GATE_UART_MASK		(0xff << APB2_GATE_UART_SHIFT)
#define APB2_GATE_TWI_SHIFT	(0)
#define APB2_GATE_TWI_MASK		(0xf << APB2_GATE_TWI_SHIFT)

/* cpu_axi_cfg bits */
#define AXI_DIV_SHIFT			0
#define ATB_DIV_SHIFT			8
#define CPU_CLK_SRC_SHIFT		16

#define AXI_DIV_1			0
#define AXI_DIV_2			1
#define AXI_DIV_3			2
#define AXI_DIV_4			3
#define ATB_DIV_1			0
#define ATB_DIV_2			1
#define ATB_DIV_4			2
#define CPU_CLK_SRC_OSC24M		1
#define CPU_CLK_SRC_PLL1		2

#define CCM_PLL1_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
#define CCM_PLL1_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
#define CCM_PLL1_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
#define CCM_PLL1_CTRL_MAGIC		(0x1 << 16)
#define CCM_PLL1_CTRL_EN		(0x1 << 31)

#define CCM_PLL3_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
#define CCM_PLL3_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
#define CCM_PLL3_CTRL_INTEGER_MODE	(0x1 << 24)
#define CCM_PLL3_CTRL_EN		(0x1 << 31)

#define CCM_PLL5_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
#define CCM_PLL5_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
#define CCM_PLL5_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
#define CCM_PLL5_CTRL_UPD		(0x1 << 20)
#define CCM_PLL5_CTRL_EN		(0x1 << 31)

#define PLL6_CFG_DEFAULT		0x90041811 /* 600 MHz */

#define CCM_PLL6_CTRL_N_SHIFT		8
#define CCM_PLL6_CTRL_N_MASK		(0x1f << CCM_PLL6_CTRL_N_SHIFT)
#define CCM_PLL6_CTRL_K_SHIFT		4
#define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)

#define AHB1_ABP1_DIV_DEFAULT		0x00002020

#define AXI_GATE_OFFSET_DRAM		0

/* ahb_gate0 offsets */
#define AHB_GATE_OFFSET_USB_OHCI1	30
#define AHB_GATE_OFFSET_USB_OHCI0	29
#define AHB_GATE_OFFSET_USB_EHCI1	27
#define AHB_GATE_OFFSET_USB_EHCI0	26
#define AHB_GATE_OFFSET_MCTL		14
#define AHB_GATE_OFFSET_GMAC		17
#define AHB_GATE_OFFSET_MMC3		11
#define AHB_GATE_OFFSET_MMC2		10
#define AHB_GATE_OFFSET_MMC1		9
#define AHB_GATE_OFFSET_MMC0		8
#define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))

/* ahb_gate1 offsets */
#define AHB_GATE_OFFSET_DRC0		25
#define AHB_GATE_OFFSET_DE_BE0		12
#define AHB_GATE_OFFSET_HDMI		11
#define AHB_GATE_OFFSET_LCD1		5
#define AHB_GATE_OFFSET_LCD0		4

#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
#define CCM_MMC_CTRL_PLL6   (0x1 << 24)

#define CCM_MMC_CTRL_ENABLE (0x1 << 31)

#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
/* There is no global phy clk gate on sun6i, define as 0 */
#define CCM_USB_CTRL_PHYGATE 0
#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)

#define CCM_GMAC_CTRL_TX_CLK_SRC_MII	0x0
#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
#define CCM_GMAC_CTRL_GPIT_MII		(0x0 << 2)
#define CCM_GMAC_CTRL_GPIT_RGMII	(0x1 << 2)

#define MDFS_CLK_DEFAULT		0x81000002 /* PLL6 / 3 */

#define CCM_DRAMCLK_CFG_DIV0(x)		((x - 1) << 8)
#define CCM_DRAMCLK_CFG_DIV0_MASK	(0xf << 8)
#define CCM_DRAMCLK_CFG_UPD		(0x1 << 16)
#define CCM_DRAMCLK_CFG_RST		(0x1 << 31)

#define CCM_DRAM_GATE_OFFSET_DE_BE0	26

#define CCM_LCD_CH0_CTRL_PLL3		(0 << 24)
#define CCM_LCD_CH0_CTRL_PLL7		(1 << 24)
#define CCM_LCD_CH0_CTRL_PLL3_2X	(2 << 24)
#define CCM_LCD_CH0_CTRL_PLL7_2X	(3 << 24)
#define CCM_LCD_CH0_CTRL_MIPI_PLL	(4 << 24)
#define CCM_LCD_CH0_CTRL_GATE		(0x1 << 31)

#define CCM_LCD_CH1_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
#define CCM_LCD_CH1_CTRL_PLL3		(0 << 24)
#define CCM_LCD_CH1_CTRL_PLL7		(1 << 24)
#define CCM_LCD_CH1_CTRL_PLL3_2X	(2 << 24)
#define CCM_LCD_CH1_CTRL_PLL7_2X	(3 << 24)
#define CCM_LCD_CH1_CTRL_GATE		(0x1 << 31)

#define CCM_HDMI_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
#define CCM_HDMI_CTRL_PLL_MASK		(3 << 24)
#define CCM_HDMI_CTRL_PLL3		(0 << 24)
#define CCM_HDMI_CTRL_PLL7		(1 << 24)
#define CCM_HDMI_CTRL_PLL3_2X		(2 << 24)
#define CCM_HDMI_CTRL_PLL7_2X		(3 << 24)
#define CCM_HDMI_CTRL_DDC_GATE		(0x1 << 30)
#define CCM_HDMI_CTRL_GATE		(0x1 << 31)

#define MBUS_CLK_DEFAULT		0x81000001 /* PLL6 / 2 */

/* ahb_reset0 offsets */
#define AHB_RESET_OFFSET_GMAC		17
#define AHB_RESET_OFFSET_MCTL		14
#define AHB_RESET_OFFSET_MMC3		11
#define AHB_RESET_OFFSET_MMC2		10
#define AHB_RESET_OFFSET_MMC1		9
#define AHB_RESET_OFFSET_MMC0		8
#define AHB_RESET_OFFSET_MMC(n)		(AHB_RESET_OFFSET_MMC0 + (n))

/* ahb_reset0 offsets */
#define AHB_RESET_OFFSET_DRC0		25
#define AHB_RESET_OFFSET_DE_BE0		12
#define AHB_RESET_OFFSET_HDMI		11
#define AHB_RESET_OFFSET_LCD1		5
#define AHB_RESET_OFFSET_LCD0		4

/* apb2 reset */
#define APB2_RESET_UART_SHIFT		(16)
#define APB2_RESET_UART_MASK		(0xff << APB2_RESET_UART_SHIFT)
#define APB2_RESET_TWI_SHIFT		(0)
#define APB2_RESET_TWI_MASK		(0xf << APB2_RESET_TWI_SHIFT)

/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
#define CCM_DE_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
#define CCM_DE_CTRL_PLL_MASK		(0xf << 24)
#define CCM_DE_CTRL_PLL3		(0 << 24)
#define CCM_DE_CTRL_PLL7		(1 << 24)
#define CCM_DE_CTRL_PLL6_2X		(2 << 24)
#define CCM_DE_CTRL_PLL8		(3 << 24)
#define CCM_DE_CTRL_PLL9		(4 << 24)
#define CCM_DE_CTRL_PLL10		(5 << 24)
#define CCM_DE_CTRL_GATE		(1 << 31)

#endif /* _SUNXI_CLOCK_SUN6I_H */
Commit	Line	Data
14177e47 CYT	1	/*
	2	* sun6i clock register definitions
	3	*
	4	* (C) Copyright 2007-2011
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#ifndef _SUNXI_CLOCK_SUN6I_H
	12	#define _SUNXI_CLOCK_SUN6I_H
	13
	14	struct sunxi_ccm_reg {
	15	u32 pll1_cfg; /* 0x00 pll1 control */
	16	u32 reserved0;
	17	u32 pll2_cfg; /* 0x08 pll2 control */
	18	u32 reserved1;
	19	u32 pll3_cfg; /* 0x10 pll3 control */
	20	u32 reserved2;
	21	u32 pll4_cfg; /* 0x18 pll4 control */
	22	u32 reserved3;
	23	u32 pll5_cfg; /* 0x20 pll5 control */
	24	u32 reserved4;
	25	u32 pll6_cfg; /* 0x28 pll6 control */
	26	u32 reserved5;
	27	u32 pll7_cfg; /* 0x30 pll7 control */
	28	u32 reserved6;
	29	u32 pll8_cfg; /* 0x38 pll8 control */
	30	u32 reserved7;
	31	u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
	32	u32 pll9_cfg; /* 0x44 pll9 control */
	33	u32 pll10_cfg; /* 0x48 pll10 control */
	34	u32 reserved8;
	35	u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
	36	u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
	37	u32 apb2_div; /* 0x58 APB2 divide ratio */
	38	u32 axi_gate; /* 0x5c axi module clock gating */
	39	u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
	40	u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
	41	u32 apb1_gate; /* 0x68 apb1 module clock gating */
	42	u32 apb2_gate; /* 0x6c apb2 module clock gating */
	43	u32 reserved9[4];
	44	u32 nand0_clk_cfg; /* 0x80 nand0 clock control */
	45	u32 nand1_clk_cfg; /* 0x84 nand1 clock control */
	46	u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
	47	u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
	48	u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
	49	u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
	50	u32 ts_clk_cfg; /* 0x98 transport stream clock control */
	51	u32 ss_clk_cfg; /* 0x9c security system clock control */
	52	u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */
	53	u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */
	54	u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */
	55	u32 spi3_clk_cfg; /* 0xac spi3 clock control */
	56	u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/
	57	u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */
	58	u32 reserved10[2];
	59	u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */
	60	u32 reserved11[2];
	61	u32 usb_clk_cfg; /* 0xcc USB clock control */
	62	u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */
	63	u32 reserved12[7];
	64	u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
65	u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
66	u32 reserved13[2];
67	u32 dram_clk_gate; /* 0x100 DRAM module gating */
68	u32 be0_clk_cfg; /* 0x104 BE0 module clock */
69	u32 be1_clk_cfg; /* 0x108 BE1 module clock */
70	u32 fe0_clk_cfg; /* 0x10c FE0 module clock */
71	u32 fe1_clk_cfg; /* 0x110 FE1 module clock */
72	u32 mp_clk_cfg; /* 0x114 MP module clock */
73	u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */
74	u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */
75	u32 reserved14[3];
76	u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */
77	u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */
78	u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */
79	u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */
80	u32 ve_clk_cfg; /* 0x13c VE module clock */
81	u32 adda_clk_cfg; /* 0x140 ADDA module clock */
82	u32 avs_clk_cfg; /* 0x144 AVS module clock */
83	u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
84	u32 reserved15;
85	u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
86	u32 ps_clk_cfg; /* 0x154 PS module clock */
87	u32 mtc_clk_cfg; /* 0x158 MTC module clock */
88	u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
89	u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
90	u32 reserved16;
91	u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
92	u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
93	u32 reserved17[4];
94	u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */
95	u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */
96	u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */
97	u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */
98	u32 reserved18[4];
99	u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */
100	u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */
101	u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */
102	u32 reserved19[21];
103	u32 pll_lock; /* 0x200 PLL Lock Time */
104	u32 pll1_lock; /* 0x204 PLL1 Lock Time */
105	u32 reserved20[6];
106	u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */
107	u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */
108	u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */
109	u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */
110	u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */
111	u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */
112	u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */
113	u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */
114	u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */
115	u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */
116	u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */
117	u32 reserved21[13];
118	u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */
119	u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */
120	u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */
121	u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */
122	u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */
123	u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */
124	u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */
125	u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */
126	u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
127	u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
128	u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
129	u32 reserved22[5];
130	u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
131	u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
132	u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
133	u32 reserved23;
134	u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
135	u32 reserved24;
136	u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
137	};
138
139	/* apb2 bit field */
140	#define APB2_CLK_SRC_LOSC (0x0 << 24)
141	#define APB2_CLK_SRC_OSC24M (0x1 << 24)
142	#define APB2_CLK_SRC_PLL6 (0x2 << 24)
143	#define APB2_CLK_SRC_MASK (0x3 << 24)
144	#define APB2_CLK_RATE_N_1 (0x0 << 16)
145	#define APB2_CLK_RATE_N_2 (0x1 << 16)
146	#define APB2_CLK_RATE_N_4 (0x2 << 16)
147	#define APB2_CLK_RATE_N_8 (0x3 << 16)
148	#define APB2_CLK_RATE_N_MASK (3 << 16)
149	#define APB2_CLK_RATE_M(m) (((m)-1) << 0)
150	#define APB2_CLK_RATE_M_MASK (0x1f << 0)
151
152	/* apb2 gate field */
153	#define APB2_GATE_UART_SHIFT (16)
154	#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT)
155	#define APB2_GATE_TWI_SHIFT (0)
156	#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT)
157
158	/* cpu_axi_cfg bits */
159	#define AXI_DIV_SHIFT 0
160	#define ATB_DIV_SHIFT 8
161	#define CPU_CLK_SRC_SHIFT 16
162
163	#define AXI_DIV_1 0
164	#define AXI_DIV_2 1
165	#define AXI_DIV_3 2
166	#define AXI_DIV_4 3
167	#define ATB_DIV_1 0
168	#define ATB_DIV_2 1
169	#define ATB_DIV_4 2
170	#define CPU_CLK_SRC_OSC24M 1
171	#define CPU_CLK_SRC_PLL1 2
172
62c87ef2 HG	173	#define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
	174	#define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
	175	#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
	176	#define CCM_PLL1_CTRL_MAGIC (0x1 << 16)
	177	#define CCM_PLL1_CTRL_EN (0x1 << 31)
	178
0bd51251 HG	179	#define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
	180	#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
	181	#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24)
	182	#define CCM_PLL3_CTRL_EN (0x1 << 31)
	183
62c87ef2 HG	184	#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
	185	#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
	186	#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
	187	#define CCM_PLL5_CTRL_UPD (0x1 << 20)
	188	#define CCM_PLL5_CTRL_EN (0x1 << 31)
14177e47	189
0bd51251	190	#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */
14177e47 CYT	191
	192	#define CCM_PLL6_CTRL_N_SHIFT 8
	193	#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
	194	#define CCM_PLL6_CTRL_K_SHIFT 4
	195	#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
	196
62c87ef2 HG	197	#define AHB1_ABP1_DIV_DEFAULT 0x00002020
	198
	199	#define AXI_GATE_OFFSET_DRAM 0
	200
0bd51251	201	/* ahb_gate0 offsets */
76946dfe HG	202	#define AHB_GATE_OFFSET_USB_OHCI1 30
	203	#define AHB_GATE_OFFSET_USB_OHCI0 29
	204	#define AHB_GATE_OFFSET_USB_EHCI1 27
	205	#define AHB_GATE_OFFSET_USB_EHCI0 26
62c87ef2	206	#define AHB_GATE_OFFSET_MCTL 14
eafec320	207	#define AHB_GATE_OFFSET_GMAC 17
14177e47 CYT	208	#define AHB_GATE_OFFSET_MMC3 11
	209	#define AHB_GATE_OFFSET_MMC2 10
	210	#define AHB_GATE_OFFSET_MMC1 9
	211	#define AHB_GATE_OFFSET_MMC0 8
	212	#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
	213
0bd51251 HG	214	/* ahb_gate1 offsets */
	215	#define AHB_GATE_OFFSET_DRC0 25
	216	#define AHB_GATE_OFFSET_DE_BE0 12
	217	#define AHB_GATE_OFFSET_HDMI 11
	218	#define AHB_GATE_OFFSET_LCD1 5
	219	#define AHB_GATE_OFFSET_LCD0 4
	220
14177e47 CYT	221	#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
	222	#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
	223
	224	#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
	225
76946dfe HG	226	#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
	227	#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
	228	/* There is no global phy clk gate on sun6i, define as 0 */
	229	#define CCM_USB_CTRL_PHYGATE 0
	230	#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
	231	#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
	232
eafec320 HG	233	#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
	234	#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
	235	#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
	236	#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
	237	#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
	238
62c87ef2 HG	239	#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
	240
	241	#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
	242	#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
	243	#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
	244	#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
	245
0bd51251 HG	246	#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
	247
	248	#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
	249	#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
	250	#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24)
	251	#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24)
	252	#define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24)
	253	#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
	254
	255	#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
	256	#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24)
	257	#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24)
	258	#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24)
	259	#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24)
	260	#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31)
	261
	262	#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
	263	#define CCM_HDMI_CTRL_PLL_MASK (3 << 24)
	264	#define CCM_HDMI_CTRL_PLL3 (0 << 24)
	265	#define CCM_HDMI_CTRL_PLL7 (1 << 24)
	266	#define CCM_HDMI_CTRL_PLL3_2X (2 << 24)
	267	#define CCM_HDMI_CTRL_PLL7_2X (3 << 24)
	268	#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
	269	#define CCM_HDMI_CTRL_GATE (0x1 << 31)
	270
62c87ef2 HG	271	#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
62c87ef2 HG	272
0bd51251	273	/* ahb_reset0 offsets */
eafec320	274	#define AHB_RESET_OFFSET_GMAC 17
62c87ef2	275	#define AHB_RESET_OFFSET_MCTL 14
14177e47 CYT	276	#define AHB_RESET_OFFSET_MMC3 11
	277	#define AHB_RESET_OFFSET_MMC2 10
	278	#define AHB_RESET_OFFSET_MMC1 9
	279	#define AHB_RESET_OFFSET_MMC0 8
	280	#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
	281
0bd51251 HG	282	/* ahb_reset0 offsets */
	283	#define AHB_RESET_OFFSET_DRC0 25
	284	#define AHB_RESET_OFFSET_DE_BE0 12
	285	#define AHB_RESET_OFFSET_HDMI 11
	286	#define AHB_RESET_OFFSET_LCD1 5
	287	#define AHB_RESET_OFFSET_LCD0 4
	288
14177e47 CYT	289	/* apb2 reset */
	290	#define APB2_RESET_UART_SHIFT (16)
	291	#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
	292	#define APB2_RESET_TWI_SHIFT (0)
	293	#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
	294
0bd51251 HG	295	/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
	296	#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
	297	#define CCM_DE_CTRL_PLL_MASK (0xf << 24)
	298	#define CCM_DE_CTRL_PLL3 (0 << 24)
	299	#define CCM_DE_CTRL_PLL7 (1 << 24)
	300	#define CCM_DE_CTRL_PLL6_2X (2 << 24)
	301	#define CCM_DE_CTRL_PLL8 (3 << 24)
	302	#define CCM_DE_CTRL_PLL9 (4 << 24)
	303	#define CCM_DE_CTRL_PLL10 (5 << 24)
	304	#define CCM_DE_CTRL_GATE (1 << 31)
	305
14177e47	306	#endif /* _SUNXI_CLOCK_SUN6I_H */