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3f82b1d3 TW |
1 | /* |
2 | * (C) Copyright 2010,2011 | |
3 | * NVIDIA Corporation <www.nvidia.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
3f82b1d3 TW |
6 | */ |
7 | ||
8 | #ifndef _PMC_H_ | |
9 | #define _PMC_H_ | |
10 | ||
11 | /* Power Management Controller (APBDEV_PMC_) registers */ | |
12 | struct pmc_ctlr { | |
13 | uint pmc_cntrl; /* _CNTRL_0, offset 00 */ | |
14 | uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */ | |
15 | uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */ | |
16 | uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */ | |
17 | uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */ | |
18 | uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */ | |
19 | uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */ | |
20 | uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */ | |
21 | uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */ | |
22 | uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */ | |
23 | uint pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */ | |
24 | uint pmc_pwrgate_timer_on; /* _PWRGATE_TIMER_ON_0, offset 2C */ | |
25 | uint pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */ | |
26 | uint pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */ | |
27 | uint pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */ | |
28 | uint pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */ | |
29 | uint pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */ | |
30 | uint pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */ | |
31 | uint pmc_pwr_det; /* _PWR_DET_0, offset 48 */ | |
32 | uint pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */ | |
33 | ||
34 | uint pmc_scratch0; /* _SCRATCH0_0, offset 50 */ | |
35 | uint pmc_scratch1; /* _SCRATCH1_0, offset 54 */ | |
36 | uint pmc_scratch2; /* _SCRATCH2_0, offset 58 */ | |
37 | uint pmc_scratch3; /* _SCRATCH3_0, offset 5C */ | |
38 | uint pmc_scratch4; /* _SCRATCH4_0, offset 60 */ | |
39 | uint pmc_scratch5; /* _SCRATCH5_0, offset 64 */ | |
40 | uint pmc_scratch6; /* _SCRATCH6_0, offset 68 */ | |
41 | uint pmc_scratch7; /* _SCRATCH7_0, offset 6C */ | |
42 | uint pmc_scratch8; /* _SCRATCH8_0, offset 70 */ | |
43 | uint pmc_scratch9; /* _SCRATCH9_0, offset 74 */ | |
44 | uint pmc_scratch10; /* _SCRATCH10_0, offset 78 */ | |
45 | uint pmc_scratch11; /* _SCRATCH11_0, offset 7C */ | |
46 | uint pmc_scratch12; /* _SCRATCH12_0, offset 80 */ | |
47 | uint pmc_scratch13; /* _SCRATCH13_0, offset 84 */ | |
48 | uint pmc_scratch14; /* _SCRATCH14_0, offset 88 */ | |
49 | uint pmc_scratch15; /* _SCRATCH15_0, offset 8C */ | |
50 | uint pmc_scratch16; /* _SCRATCH16_0, offset 90 */ | |
51 | uint pmc_scratch17; /* _SCRATCH17_0, offset 94 */ | |
52 | uint pmc_scratch18; /* _SCRATCH18_0, offset 98 */ | |
53 | uint pmc_scratch19; /* _SCRATCH19_0, offset 9C */ | |
54 | uint pmc_scratch20; /* _SCRATCH20_0, offset A0 */ | |
55 | uint pmc_scratch21; /* _SCRATCH21_0, offset A4 */ | |
56 | uint pmc_scratch22; /* _SCRATCH22_0, offset A8 */ | |
57 | uint pmc_scratch23; /* _SCRATCH23_0, offset AC */ | |
58 | ||
59 | uint pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */ | |
60 | uint pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */ | |
61 | uint pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */ | |
62 | uint pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */ | |
63 | uint pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */ | |
64 | uint pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */ | |
65 | ||
66 | uint pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */ | |
67 | uint pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */ | |
68 | uint pmc_pg_mask; /* _PG_MASK_0, offset D0 */ | |
69 | uint pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */ | |
70 | uint pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */ | |
71 | uint pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */ | |
72 | uint pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */ | |
73 | uint pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */ | |
74 | uint pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */ | |
75 | uint pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */ | |
76 | uint pmc_usb_ao; /* _USB_AO_0, offset F0 */ | |
77 | uint pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */ | |
78 | uint pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */ | |
79 | ||
80 | uint pmc_scratch24; /* _SCRATCH24_0, offset FC */ | |
81 | uint pmc_scratch25; /* _SCRATCH24_0, offset 100 */ | |
82 | uint pmc_scratch26; /* _SCRATCH24_0, offset 104 */ | |
83 | uint pmc_scratch27; /* _SCRATCH24_0, offset 108 */ | |
84 | uint pmc_scratch28; /* _SCRATCH24_0, offset 10C */ | |
85 | uint pmc_scratch29; /* _SCRATCH24_0, offset 110 */ | |
86 | uint pmc_scratch30; /* _SCRATCH24_0, offset 114 */ | |
87 | uint pmc_scratch31; /* _SCRATCH24_0, offset 118 */ | |
88 | uint pmc_scratch32; /* _SCRATCH24_0, offset 11C */ | |
89 | uint pmc_scratch33; /* _SCRATCH24_0, offset 120 */ | |
90 | uint pmc_scratch34; /* _SCRATCH24_0, offset 124 */ | |
91 | uint pmc_scratch35; /* _SCRATCH24_0, offset 128 */ | |
92 | uint pmc_scratch36; /* _SCRATCH24_0, offset 12C */ | |
93 | uint pmc_scratch37; /* _SCRATCH24_0, offset 130 */ | |
94 | uint pmc_scratch38; /* _SCRATCH24_0, offset 134 */ | |
95 | uint pmc_scratch39; /* _SCRATCH24_0, offset 138 */ | |
96 | uint pmc_scratch40; /* _SCRATCH24_0, offset 13C */ | |
97 | uint pmc_scratch41; /* _SCRATCH24_0, offset 140 */ | |
98 | uint pmc_scratch42; /* _SCRATCH24_0, offset 144 */ | |
99 | ||
100 | uint pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */ | |
101 | uint pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */ | |
102 | uint pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */ | |
103 | uint pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */ | |
104 | uint pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */ | |
105 | uint pmc_gate; /* _GATE_0, offset 15C */ | |
106 | }; | |
107 | ||
74652cf6 TW |
108 | #define CPU_PWRED 1 |
109 | #define CPU_CLMP 1 | |
110 | ||
111 | #define PARTID_CP 0xFFFFFFF8 | |
112 | #define START_CP (1 << 8) | |
113 | ||
114 | #define CPUPWRREQ_OE (1 << 16) | |
2fc65e28 TW |
115 | #define CPUPWRREQ_POL (1 << 15) |
116 | ||
117 | #define CRAILID (0) | |
118 | #define CE0ID (14) | |
119 | #define C0NCID (15) | |
120 | #define CRAIL (1 << CRAILID) | |
121 | #define CE0 (1 << CE0ID) | |
122 | #define C0NC (1 << C0NCID) | |
74652cf6 | 123 | |
3f82b1d3 | 124 | #endif /* PMC_H */ |