[people/ms/u-boot.git] / arch / arm / include / asm / arch-tegra / usb.h

/*
 * Copyright (c) 2011 The Chromium OS Authors.
 * Copyright (c) 2013 NVIDIA Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _TEGRA_USB_H_
#define _TEGRA_USB_H_

/* USB Controller (USBx_CONTROLLER_) regs */
struct usb_ctlr {
	/* 0x000 */
	uint id;
	uint reserved0;
	uint host;
	uint device;

	/* 0x010 */
	uint txbuf;
	uint rxbuf;
	uint reserved1[2];

	/* 0x020 */
	uint reserved2[56];

	/* 0x100 */
	u16 cap_length;
	u16 hci_version;
	uint hcs_params;
	uint hcc_params;
	uint reserved3[5];

	/* 0x120 */
	uint dci_version;
	uint dcc_params;
	uint reserved4[2];

#ifdef CONFIG_TEGRA20
	/* 0x130 */
	uint reserved4_2[4];

	/* 0x140 */
	uint usb_cmd;
	uint usb_sts;
	uint usb_intr;
	uint frindex;

	/* 0x150 */
	uint reserved5;
	uint periodic_list_base;
	uint async_list_addr;
	uint async_tt_sts;

	/* 0x160 */
	uint burst_size;
	uint tx_fill_tuning;
	uint reserved6;   /* is this port_sc1 on some controllers? */
	uint icusb_ctrl;

	/* 0x170 */
	uint ulpi_viewport;
	uint reserved7;
	uint endpt_nak;
	uint endpt_nak_enable;

	/* 0x180 */
	uint reserved;
	uint port_sc1;
	uint reserved8[6];

	/* 0x1a0 */
	uint reserved9;
	uint otgsc;
	uint usb_mode;
	uint endpt_setup_stat;

	/* 0x1b0 */
	uint reserved10[20];

	/* 0x200 */
	uint reserved11[0x80];
#else
	/* 0x130 */
	uint usb_cmd;
	uint usb_sts;
	uint usb_intr;
	uint frindex;

	/* 0x140 */
	uint reserved5;
	uint periodic_list_base;
	uint async_list_addr;
	uint reserved5_1;

	/* 0x150 */
	uint burst_size;
	uint tx_fill_tuning;
	uint reserved6;
	uint icusb_ctrl;

	/* 0x160 */
	uint ulpi_viewport;
	uint reserved7[3];

	/* 0x170 */
	uint reserved;
	uint port_sc1;
	uint reserved8[6];

	/* 0x190 */
	uint reserved9[8];

	/* 0x1b0 */
	uint reserved10;
	uint hostpc1_devlc;
	uint reserved10_1[2];

	/* 0x1c0 */
	uint reserved10_2[4];

	/* 0x1d0 */
	uint reserved10_3[4];

	/* 0x1e0 */
	uint reserved10_4[4];

	/* 0x1f0 */
	uint reserved10_5;
	uint otgsc;
	uint usb_mode;
	uint reserved10_6;

	/* 0x200 */
	uint endpt_nak;
	uint endpt_nak_enable;
	uint endpt_setup_stat;
	uint reserved11_1[0x7D];
#endif

	/* 0x400 */
	uint susp_ctrl;
	uint phy_vbus_sensors;
	uint phy_vbus_wakeup_id;
	uint phy_alt_vbus_sys;

#ifdef CONFIG_TEGRA20
	/* 0x410 */
	uint usb1_legacy_ctrl;
	uint reserved12[4];

	/* 0x424 */
	uint ulpi_timing_ctrl_0;
	uint ulpi_timing_ctrl_1;
	uint reserved13[53];
#else

	/* 0x410 */
	uint usb1_legacy_ctrl;
	uint reserved12[3];

	/* 0x420 */
	uint reserved13[56];
#endif

	/* 0x500 */
	uint reserved14[64 * 3];

	/* 0x800 */
	uint utmip_pll_cfg0;
	uint utmip_pll_cfg1;
	uint utmip_xcvr_cfg0;
	uint utmip_bias_cfg0;

	/* 0x810 */
	uint utmip_hsrx_cfg0;
	uint utmip_hsrx_cfg1;
	uint utmip_fslsrx_cfg0;
	uint utmip_fslsrx_cfg1;

	/* 0x820 */
	uint utmip_tx_cfg0;
	uint utmip_misc_cfg0;
	uint utmip_misc_cfg1;
	uint utmip_debounce_cfg0;

	/* 0x830 */
	uint utmip_bat_chrg_cfg0;
	uint utmip_spare_cfg0;
	uint utmip_xcvr_cfg1;
	uint utmip_bias_cfg1;
};

/* USB1_LEGACY_CTRL */
#define USB1_NO_LEGACY_MODE		1

#define VBUS_SENSE_CTL_SHIFT			1
#define VBUS_SENSE_CTL_MASK			(3 << VBUS_SENSE_CTL_SHIFT)
#define VBUS_SENSE_CTL_VBUS_WAKEUP		0
#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP	1
#define VBUS_SENSE_CTL_AB_SESS_VLD		2
#define VBUS_SENSE_CTL_A_SESS_VLD		3

/* USBx_IF_USB_SUSP_CTRL_0 */
#define UTMIP_PHY_ENB			        (1 << 12)
#define UTMIP_RESET			        (1 << 11)
#define USB_PHY_CLK_VALID			(1 << 7)
#define USB_SUSP_CLR				(1 << 5)

#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
/* USB2_IF_USB_SUSP_CTRL_0 */
#define ULPI_PHY_ENB				(1 << 13)

/* USB2_IF_ULPI_TIMING_CTRL_0 */
#define ULPI_OUTPUT_PINMUX_BYP			(1 << 10)
#define ULPI_CLKOUT_PINMUX_BYP			(1 << 11)

/* USB2_IF_ULPI_TIMING_CTRL_1 */
#define ULPI_DATA_TRIMMER_LOAD			(1 << 0)
#define ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
#define ULPI_STPDIRNXT_TRIMMER_LOAD		(1 << 16)
#define ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
#define ULPI_DIR_TRIMMER_LOAD			(1 << 24)
#define ULPI_DIR_TRIMMER_SEL(x)			(((x) & 0x7) << 25)
#endif

/* USBx_UTMIP_MISC_CFG0 */
#define UTMIP_SUSPEND_EXIT_ON_EDGE		(1 << 22)

/* USBx_UTMIP_MISC_CFG1 */
#define UTMIP_PHY_XTAL_CLOCKEN			(1 << 30)

/*
 * Tegra 3 and later: Moved to Clock and Reset register space, see
 * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
 */
#define UTMIP_PLLU_STABLE_COUNT_SHIFT		6
#define UTMIP_PLLU_STABLE_COUNT_MASK		\
				(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
/*
 * Tegra 3 and later: Moved to Clock and Reset register space, see
 * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
 */
#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT	18
#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK		\
				(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)

/* USBx_UTMIP_PLL_CFG1_0 */
/* Tegra 3 and later: Moved to Clock and Reset register space */
#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT	27
#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK	\
				(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
#define UTMIP_XTAL_FREQ_COUNT_SHIFT		0
#define UTMIP_XTAL_FREQ_COUNT_MASK		0xfff

/* USBx_UTMIP_BIAS_CFG0_0 */
#define UTMIP_HSDISCON_LEVEL_MSB		(1 << 24)
#define UTMIP_OTGPD				(1 << 11)
#define UTMIP_BIASPD				(1 << 10)
#define UTMIP_HSDISCON_LEVEL_SHIFT		2
#define UTMIP_HSDISCON_LEVEL_MASK		\
				(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
#define UTMIP_HSSQUELCH_LEVEL_SHIFT		0
#define UTMIP_HSSQUELCH_LEVEL_MASK		\
				(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)

/* USBx_UTMIP_BIAS_CFG1_0 */
#define UTMIP_FORCE_PDTRK_POWERDOWN		1
#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT	8
#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK	\
				(0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
#define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
#define UTMIP_BIAS_PDTRK_COUNT_MASK		\
				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)

/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
#define UTMIP_DEBOUNCE_CFG0_SHIFT		0
#define UTMIP_DEBOUNCE_CFG0_MASK		0xffff

/* USBx_UTMIP_TX_CFG0_0 */
#define UTMIP_FS_PREAMBLE_J			(1 << 19)

/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
#define UTMIP_PD_CHRG				1

/* USBx_UTMIP_SPARE_CFG0_0 */
#define FUSE_SETUP_SEL				(1 << 3)

/* USBx_UTMIP_HSRX_CFG0_0 */
#define UTMIP_IDLE_WAIT_SHIFT			15
#define UTMIP_IDLE_WAIT_MASK			(0x1f << UTMIP_IDLE_WAIT_SHIFT)
#define UTMIP_ELASTIC_LIMIT_SHIFT		10
#define UTMIP_ELASTIC_LIMIT_MASK		\
				(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)

/* USBx_UTMIP_HSRX_CFG1_0 */
#define UTMIP_HS_SYNC_START_DLY_SHIFT		1
#define UTMIP_HS_SYNC_START_DLY_MASK		\
				(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)

/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
#define IC_ENB1					(1 << 3)

#ifdef CONFIG_TEGRA20
/* PORTSC1, USB1 */
#define PTS1_SHIFT				31
#define PTS1_MASK				(1 << PTS1_SHIFT)
#define STS1					(1 << 30)

/* PORTSC, USB2, USB3 */
#define PTS_SHIFT		30
#define PTS_MASK		(3U << PTS_SHIFT)
#define STS			(1 << 29)
#else
/* USB2D_HOSTPC1_DEVLC_0 */
#define PTS_SHIFT				29
#define PTS_MASK				(0x7U << PTS_SHIFT)
#define STS						(1 << 28)
#endif

#define PTS_UTMI	0
#define PTS_RESERVED	1
#define PTS_ULPI	2
#define PTS_ICUSB_SER	3
#define PTS_HSIC	4

/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
#define WKOC				(1 << 22)
#define WKDS				(1 << 21)
#define WKCN				(1 << 20)

/* USBx_UTMIP_XCVR_CFG0_0 */
#define UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
#define UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
#define UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
#define UTMIP_XCVR_LSBIAS_SE			(1 << 21)
#define UTMIP_XCVR_HSSLEW_MSB_SHIFT		25
#define UTMIP_XCVR_HSSLEW_MSB_MASK		\
			(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
#define UTMIP_XCVR_SETUP_MSB_SHIFT	22
#define UTMIP_XCVR_SETUP_MSB_MASK	(0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
#define UTMIP_XCVR_SETUP_SHIFT		0
#define UTMIP_XCVR_SETUP_MASK		(0xf << UTMIP_XCVR_SETUP_SHIFT)

/* USBx_UTMIP_XCVR_CFG1_0 */
#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT		18
#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK		\
			(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
#define UTMIP_FORCE_PDDISC_POWERDOWN		(1 << 0)
#define UTMIP_FORCE_PDCHRP_POWERDOWN		(1 << 2)
#define UTMIP_FORCE_PDDR_POWERDOWN		(1 << 4)

/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
#define VBUS_VLD_STS			(1 << 26)
#define VBUS_B_SESS_VLD_SW_VALUE	(1 << 12)
#define VBUS_B_SESS_VLD_SW_EN		(1 << 11)

/* Setup USB on the board */
int usb_process_devicetree(const void *blob);

#endif	/* _TEGRA_USB_H_ */
Commit	Line	Data
87f938c9 SG	1	/*
87f938c9 SG	2	* Copyright (c) 2011 The Chromium OS Authors.
7e44d932	3	* Copyright (c) 2013 NVIDIA Corporation
87f938c9	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
87f938c9 SG	6	*/
	7
	8	#ifndef _TEGRA_USB_H_
	9	#define _TEGRA_USB_H_
	10
8f9fd6ca SA	11	/* USB Controller (USBx_CONTROLLER_) regs */
	12	struct usb_ctlr {
	13	/* 0x000 */
	14	uint id;
	15	uint reserved0;
	16	uint host;
	17	uint device;
	18
	19	/* 0x010 */
	20	uint txbuf;
	21	uint rxbuf;
	22	uint reserved1[2];
	23
	24	/* 0x020 */
	25	uint reserved2[56];
	26
	27	/* 0x100 */
	28	u16 cap_length;
	29	u16 hci_version;
	30	uint hcs_params;
	31	uint hcc_params;
	32	uint reserved3[5];
	33
	34	/* 0x120 */
	35	uint dci_version;
	36	uint dcc_params;
	37	uint reserved4[2];
	38
	39	#ifdef CONFIG_TEGRA20
	40	/* 0x130 */
	41	uint reserved4_2[4];
	42
	43	/* 0x140 */
	44	uint usb_cmd;
	45	uint usb_sts;
	46	uint usb_intr;
	47	uint frindex;
	48
	49	/* 0x150 */
	50	uint reserved5;
	51	uint periodic_list_base;
	52	uint async_list_addr;
	53	uint async_tt_sts;
	54
	55	/* 0x160 */
	56	uint burst_size;
	57	uint tx_fill_tuning;
	58	uint reserved6; /* is this port_sc1 on some controllers? */
	59	uint icusb_ctrl;
	60
	61	/* 0x170 */
	62	uint ulpi_viewport;
	63	uint reserved7;
	64	uint endpt_nak;
	65	uint endpt_nak_enable;
	66
	67	/* 0x180 */
	68	uint reserved;
	69	uint port_sc1;
	70	uint reserved8[6];
	71
	72	/* 0x1a0 */
	73	uint reserved9;
	74	uint otgsc;
75	uint usb_mode;
76	uint endpt_setup_stat;
77
78	/* 0x1b0 */
79	uint reserved10[20];
80
81	/* 0x200 */
82	uint reserved11[0x80];
83	#else
84	/* 0x130 */
85	uint usb_cmd;
86	uint usb_sts;
87	uint usb_intr;
88	uint frindex;
89
90	/* 0x140 */
91	uint reserved5;
92	uint periodic_list_base;
93	uint async_list_addr;
94	uint reserved5_1;
95
96	/* 0x150 */
97	uint burst_size;
98	uint tx_fill_tuning;
99	uint reserved6;
100	uint icusb_ctrl;
101
102	/* 0x160 */
103	uint ulpi_viewport;
104	uint reserved7[3];
105
106	/* 0x170 */
107	uint reserved;
108	uint port_sc1;
109	uint reserved8[6];
110
111	/* 0x190 */
112	uint reserved9[8];
113
114	/* 0x1b0 */
115	uint reserved10;
116	uint hostpc1_devlc;
117	uint reserved10_1[2];
118
119	/* 0x1c0 */
120	uint reserved10_2[4];
121
122	/* 0x1d0 */
123	uint reserved10_3[4];
124
125	/* 0x1e0 */
126	uint reserved10_4[4];
127
128	/* 0x1f0 */
129	uint reserved10_5;
130	uint otgsc;
131	uint usb_mode;
132	uint reserved10_6;
133
134	/* 0x200 */
135	uint endpt_nak;
136	uint endpt_nak_enable;
137	uint endpt_setup_stat;
138	uint reserved11_1[0x7D];
139	#endif
140
141	/* 0x400 */
142	uint susp_ctrl;
143	uint phy_vbus_sensors;
144	uint phy_vbus_wakeup_id;
145	uint phy_alt_vbus_sys;
146
147	#ifdef CONFIG_TEGRA20
148	/* 0x410 */
149	uint usb1_legacy_ctrl;
150	uint reserved12[4];
151
152	/* 0x424 */
153	uint ulpi_timing_ctrl_0;
154	uint ulpi_timing_ctrl_1;
155	uint reserved13[53];
156	#else
157
158	/* 0x410 */
159	uint usb1_legacy_ctrl;
160	uint reserved12[3];
161
162	/* 0x420 */
163	uint reserved13[56];
164	#endif
165
166	/* 0x500 */
167	uint reserved14[64 * 3];
168
169	/* 0x800 */
170	uint utmip_pll_cfg0;
171	uint utmip_pll_cfg1;
172	uint utmip_xcvr_cfg0;
173	uint utmip_bias_cfg0;
174
175	/* 0x810 */
176	uint utmip_hsrx_cfg0;
177	uint utmip_hsrx_cfg1;
178	uint utmip_fslsrx_cfg0;
179	uint utmip_fslsrx_cfg1;
180
181	/* 0x820 */
182	uint utmip_tx_cfg0;
183	uint utmip_misc_cfg0;
184	uint utmip_misc_cfg1;
185	uint utmip_debounce_cfg0;
186
187	/* 0x830 */
188	uint utmip_bat_chrg_cfg0;
189	uint utmip_spare_cfg0;
190	uint utmip_xcvr_cfg1;
191	uint utmip_bias_cfg1;
192	};
193
87f938c9 SG	194	/* USB1_LEGACY_CTRL */
	195	#define USB1_NO_LEGACY_MODE 1
	196
	197	#define VBUS_SENSE_CTL_SHIFT 1
	198	#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
	199	#define VBUS_SENSE_CTL_VBUS_WAKEUP 0
	200	#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
	201	#define VBUS_SENSE_CTL_AB_SESS_VLD 2
	202	#define VBUS_SENSE_CTL_A_SESS_VLD 3
	203
	204	/* USBx_IF_USB_SUSP_CTRL_0 */
	205	#define UTMIP_PHY_ENB (1 << 12)
	206	#define UTMIP_RESET (1 << 11)
	207	#define USB_PHY_CLK_VALID (1 << 7)
6d365ea0	208	#define USB_SUSP_CLR (1 << 5)
87f938c9	209
8f9fd6ca	210	#if defined(CONFIG_TEGRA20) \|\| defined(CONFIG_TEGRA30)
7e44d932 JL	211	/* USB2_IF_USB_SUSP_CTRL_0 */
	212	#define ULPI_PHY_ENB (1 << 13)
	213
8f9fd6ca SA	214	/* USB2_IF_ULPI_TIMING_CTRL_0 */
	215	#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
	216	#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
	217
	218	/* USB2_IF_ULPI_TIMING_CTRL_1 */
	219	#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
	220	#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
	221	#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
	222	#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
	223	#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
	224	#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
	225	#endif
	226
7e44d932 JL	227	/* USBx_UTMIP_MISC_CFG0 */
	228	#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
	229
87f938c9	230	/* USBx_UTMIP_MISC_CFG1 */
8f9fd6ca SA	231	#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
	232
	233	/*
	234	* Tegra 3 and later: Moved to Clock and Reset register space, see
	235	* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
	236	*/
87f938c9 SG	237	#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
	238	#define UTMIP_PLLU_STABLE_COUNT_MASK \
	239	(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
8f9fd6ca SA	240	/*
	241	* Tegra 3 and later: Moved to Clock and Reset register space, see
	242	* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
	243	*/
87f938c9 SG	244	#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
	245	#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
	246	(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
87f938c9 SG	247
87f938c9 SG	248	/* USBx_UTMIP_PLL_CFG1_0 */
8f9fd6ca	249	/* Tegra 3 and later: Moved to Clock and Reset register space */
87f938c9 SG	250	#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
87f938c9 SG	251	#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
7e44d932	252	(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
87f938c9 SG	253	#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
	254	#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
	255
7e44d932 JL	256	/* USBx_UTMIP_BIAS_CFG0_0 */
	257	#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
	258	#define UTMIP_OTGPD (1 << 11)
	259	#define UTMIP_BIASPD (1 << 10)
	260	#define UTMIP_HSDISCON_LEVEL_SHIFT 2
	261	#define UTMIP_HSDISCON_LEVEL_MASK \
	262	(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
	263	#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
	264	#define UTMIP_HSSQUELCH_LEVEL_MASK \
	265	(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
	266
87f938c9	267	/* USBx_UTMIP_BIAS_CFG1_0 */
7e44d932	268	#define UTMIP_FORCE_PDTRK_POWERDOWN 1
7aaa5a60 TW	269	#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT 8
	270	#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK \
	271	(0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
87f938c9 SG	272	#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
	273	#define UTMIP_BIAS_PDTRK_COUNT_MASK \
	274	(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
	275
7e44d932	276	/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
87f938c9 SG	277	#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
	278	#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
	279
	280	/* USBx_UTMIP_TX_CFG0_0 */
	281	#define UTMIP_FS_PREAMBLE_J (1 << 19)
	282
	283	/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
	284	#define UTMIP_PD_CHRG 1
	285
87f938c9 SG	286	/* USBx_UTMIP_SPARE_CFG0_0 */
	287	#define FUSE_SETUP_SEL (1 << 3)
	288
	289	/* USBx_UTMIP_HSRX_CFG0_0 */
	290	#define UTMIP_IDLE_WAIT_SHIFT 15
	291	#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
	292	#define UTMIP_ELASTIC_LIMIT_SHIFT 10
	293	#define UTMIP_ELASTIC_LIMIT_MASK \
	294	(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
	295
7e44d932	296	/* USBx_UTMIP_HSRX_CFG1_0 */
87f938c9 SG	297	#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
87f938c9 SG	298	#define UTMIP_HS_SYNC_START_DLY_MASK \
7e44d932	299	(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
87f938c9 SG	300
	301	/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
	302	#define IC_ENB1 (1 << 3)
	303
8f9fd6ca SA	304	#ifdef CONFIG_TEGRA20
	305	/* PORTSC1, USB1 */
	306	#define PTS1_SHIFT 31
	307	#define PTS1_MASK (1 << PTS1_SHIFT)
	308	#define STS1 (1 << 30)
	309
	310	/* PORTSC, USB2, USB3 */
	311	#define PTS_SHIFT 30
	312	#define PTS_MASK (3U << PTS_SHIFT)
	313	#define STS (1 << 29)
	314	#else
	315	/* USB2D_HOSTPC1_DEVLC_0 */
	316	#define PTS_SHIFT 29
	317	#define PTS_MASK (0x7U << PTS_SHIFT)
	318	#define STS (1 << 28)
	319	#endif
	320
7e44d932	321	#define PTS_UTMI 0
87f938c9	322	#define PTS_RESERVED 1
7e44d932	323	#define PTS_ULPI 2
87f938c9	324	#define PTS_ICUSB_SER 3
7e44d932	325	#define PTS_HSIC 4
87f938c9	326
7e44d932	327	/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
6d365ea0 LS	328	#define WKOC (1 << 22)
	329	#define WKDS (1 << 21)
	330	#define WKCN (1 << 20)
87f938c9 SG	331
	332	/* USBx_UTMIP_XCVR_CFG0_0 */
	333	#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
	334	#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
	335	#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
7e44d932 JL	336	#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
	337	#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
	338	#define UTMIP_XCVR_HSSLEW_MSB_MASK \
	339	(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
	340	#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
	341	#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
	342	#define UTMIP_XCVR_SETUP_SHIFT 0
	343	#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
87f938c9 SG	344
87f938c9 SG	345	/* USBx_UTMIP_XCVR_CFG1_0 */
7e44d932 JL	346	#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
	347	#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
	348	(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
87f938c9 SG	349	#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
	350	#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
	351	#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
	352
	353	/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
	354	#define VBUS_VLD_STS (1 << 26)
a4539a2a SW	355	#define VBUS_B_SESS_VLD_SW_VALUE (1 << 12)
a4539a2a SW	356	#define VBUS_B_SESS_VLD_SW_EN (1 << 11)
87f938c9	357
87f938c9	358	/* Setup USB on the board */
16297cfb	359	int usb_process_devicetree(const void *blob);
87f938c9	360
87f938c9	361	#endif /* _TEGRA_USB_H_ */