[people/ms/u-boot.git] / arch / arm / include / asm / arch-tegra114 / pinmux.h

/*
 * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef _TEGRA114_PINMUX_H_
#define _TEGRA114_PINMUX_H_

/*
 * Pin groups which we adjust. There are three basic attributes of each pin
 * group which use this enum:
 *
 *	- function
 *	- pullup / pulldown
 *	- tristate or normal
 */
enum pmux_pingrp {
	PINGRP_ULPI_DATA0 = 0,  /* offset 0x3000 */
	PINGRP_ULPI_DATA1,
	PINGRP_ULPI_DATA2,
	PINGRP_ULPI_DATA3,
	PINGRP_ULPI_DATA4,
	PINGRP_ULPI_DATA5,
	PINGRP_ULPI_DATA6,
	PINGRP_ULPI_DATA7,
	PINGRP_ULPI_CLK,
	PINGRP_ULPI_DIR,
	PINGRP_ULPI_NXT,
	PINGRP_ULPI_STP,
	PINGRP_DAP3_FS,
	PINGRP_DAP3_DIN,
	PINGRP_DAP3_DOUT,
	PINGRP_DAP3_SCLK,
	PINGRP_GPIO_PV0,
	PINGRP_GPIO_PV1,
	PINGRP_SDMMC1_CLK,
	PINGRP_SDMMC1_CMD,
	PINGRP_SDMMC1_DAT3,
	PINGRP_SDMMC1_DAT2,
	PINGRP_SDMMC1_DAT1,
	PINGRP_SDMMC1_DAT0,
	PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
	PINGRP_CLK2_REQ,
	PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
	PINGRP_DDC_SCL,
	PINGRP_DDC_SDA,
	PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
	PINGRP_UART2_TXD,
	PINGRP_UART2_RTS_N,
	PINGRP_UART2_CTS_N,
	PINGRP_UART3_TXD,
	PINGRP_UART3_RXD,
	PINGRP_UART3_CTS_N,
	PINGRP_UART3_RTS_N,
	PINGRP_GPIO_PU0,
	PINGRP_GPIO_PU1,
	PINGRP_GPIO_PU2,
	PINGRP_GPIO_PU3,
	PINGRP_GPIO_PU4,
	PINGRP_GPIO_PU5,
	PINGRP_GPIO_PU6,
	PINGRP_GEN1_I2C_SDA,
	PINGRP_GEN1_I2C_SCL,
	PINGRP_DAP4_FS,
	PINGRP_DAP4_DIN,
	PINGRP_DAP4_DOUT,
	PINGRP_DAP4_SCLK,
	PINGRP_CLK3_OUT,
	PINGRP_CLK3_REQ,
	PINGRP_GMI_WP_N,
	PINGRP_GMI_IORDY,
	PINGRP_GMI_WAIT,
	PINGRP_GMI_ADV_N,
	PINGRP_GMI_CLK,
	PINGRP_GMI_CS0_N,
	PINGRP_GMI_CS1_N,
	PINGRP_GMI_CS2_N,
	PINGRP_GMI_CS3_N,
	PINGRP_GMI_CS4_N,
	PINGRP_GMI_CS6_N,
	PINGRP_GMI_CS7_N,
	PINGRP_GMI_AD0,
	PINGRP_GMI_AD1,
	PINGRP_GMI_AD2,
	PINGRP_GMI_AD3,
	PINGRP_GMI_AD4,
	PINGRP_GMI_AD5,
	PINGRP_GMI_AD6,
	PINGRP_GMI_AD7,
	PINGRP_GMI_AD8,
	PINGRP_GMI_AD9,
	PINGRP_GMI_AD10,
	PINGRP_GMI_AD11,
	PINGRP_GMI_AD12,
	PINGRP_GMI_AD13,
	PINGRP_GMI_AD14,
	PINGRP_GMI_AD15,
	PINGRP_GMI_A16,
	PINGRP_GMI_A17,
	PINGRP_GMI_A18,
	PINGRP_GMI_A19,
	PINGRP_GMI_WR_N,
	PINGRP_GMI_OE_N,
	PINGRP_GMI_DQS,
	PINGRP_GMI_RST_N,
	PINGRP_GEN2_I2C_SCL,
	PINGRP_GEN2_I2C_SDA,
	PINGRP_SDMMC4_CLK,
	PINGRP_SDMMC4_CMD,
	PINGRP_SDMMC4_DAT0,
	PINGRP_SDMMC4_DAT1,
	PINGRP_SDMMC4_DAT2,
	PINGRP_SDMMC4_DAT3,
	PINGRP_SDMMC4_DAT4,
	PINGRP_SDMMC4_DAT5,
	PINGRP_SDMMC4_DAT6,
	PINGRP_SDMMC4_DAT7,
	PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
	PINGRP_GPIO_PCC1,
	PINGRP_GPIO_PBB0,
	PINGRP_CAM_I2C_SCL,
	PINGRP_CAM_I2C_SDA,
	PINGRP_GPIO_PBB3,
	PINGRP_GPIO_PBB4,
	PINGRP_GPIO_PBB5,
	PINGRP_GPIO_PBB6,
	PINGRP_GPIO_PBB7,
	PINGRP_GPIO_PCC2,
	PINGRP_JTAG_RTCK,
	PINGRP_PWR_I2C_SCL,
	PINGRP_PWR_I2C_SDA,
	PINGRP_KB_ROW0,
	PINGRP_KB_ROW1,
	PINGRP_KB_ROW2,
	PINGRP_KB_ROW3,
	PINGRP_KB_ROW4,
	PINGRP_KB_ROW5,
	PINGRP_KB_ROW6,
	PINGRP_KB_ROW7,
	PINGRP_KB_ROW8,
	PINGRP_KB_ROW9,
	PINGRP_KB_ROW10,
	PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
	PINGRP_KB_COL1,
	PINGRP_KB_COL2,
	PINGRP_KB_COL3,
	PINGRP_KB_COL4,
	PINGRP_KB_COL5,
	PINGRP_KB_COL6,
	PINGRP_KB_COL7,
	PINGRP_CLK_32K_OUT,
	PINGRP_SYS_CLK_REQ,
	PINGRP_CORE_PWR_REQ,
	PINGRP_CPU_PWR_REQ,
	PINGRP_PWR_INT_N,
	PINGRP_CLK_32K_IN,
	PINGRP_OWR,
	PINGRP_DAP1_FS,
	PINGRP_DAP1_DIN,
	PINGRP_DAP1_DOUT,
	PINGRP_DAP1_SCLK,
	PINGRP_CLK1_REQ,
	PINGRP_CLK1_OUT,
	PINGRP_SPDIF_IN,
	PINGRP_SPDIF_OUT,
	PINGRP_DAP2_FS,
	PINGRP_DAP2_DIN,
	PINGRP_DAP2_DOUT,
	PINGRP_DAP2_SCLK,
	PINGRP_DVFS_PWM,
	PINGRP_GPIO_X1_AUD,
	PINGRP_GPIO_X3_AUD,
	PINGRP_DVFS_CLK,
	PINGRP_GPIO_X4_AUD,
	PINGRP_GPIO_X5_AUD,
	PINGRP_GPIO_X6_AUD,
	PINGRP_GPIO_X7_AUD,
	PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
	PINGRP_SDMMC3_CMD,
	PINGRP_SDMMC3_DAT0,
	PINGRP_SDMMC3_DAT1,
	PINGRP_SDMMC3_DAT2,
	PINGRP_SDMMC3_DAT3,
	PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
	PINGRP_SDMMC1_WP_N,
	PINGRP_SDMMC3_CD_N,
	PINGRP_GPIO_W2_AUD,
	PINGRP_GPIO_W3_AUD,
	PINGRP_USB_VBUS_EN0,	/* offset 0x33f4 */
	PINGRP_USB_VBUS_EN1,
	PINGRP_SDMMC3_CLK_LB_IN,
	PINGRP_SDMMC3_CLK_LB_OUT,
	PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
	PMUX_PINGRP_COUNT,
};

enum pmux_drvgrp {
	PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
	PDRIVE_PINGROUP_AO2,
	PDRIVE_PINGROUP_AT1,
	PDRIVE_PINGROUP_AT2,
	PDRIVE_PINGROUP_AT3,
	PDRIVE_PINGROUP_AT4,
	PDRIVE_PINGROUP_AT5,
	PDRIVE_PINGROUP_CDEV1,
	PDRIVE_PINGROUP_CDEV2,
	PDRIVE_PINGROUP_DAP1 = 10,	/* offset 0x890 */
	PDRIVE_PINGROUP_DAP2,
	PDRIVE_PINGROUP_DAP3,
	PDRIVE_PINGROUP_DAP4,
	PDRIVE_PINGROUP_DBG,
	PDRIVE_PINGROUP_SDIO3 = 18,	/* offset 0x8B0 */
	PDRIVE_PINGROUP_SPI,
	PDRIVE_PINGROUP_UAA,
	PDRIVE_PINGROUP_UAB,
	PDRIVE_PINGROUP_UART2,
	PDRIVE_PINGROUP_UART3,
	PDRIVE_PINGROUP_SDIO1 = 33,     /* offset 0x8EC */
	PDRIVE_PINGROUP_DDC = 37,       /* offset 0x8FC */
	PDRIVE_PINGROUP_GMA,
	PDRIVE_PINGROUP_GME = 42,	/* offset 0x910 */
	PDRIVE_PINGROUP_GMF,
	PDRIVE_PINGROUP_GMG,
	PDRIVE_PINGROUP_GMH,
	PDRIVE_PINGROUP_OWR,
	PDRIVE_PINGROUP_UAD,
	PDRIVE_PINGROUP_DEV3 = 49,      /* offset 0x92c */
	PDRIVE_PINGROUP_CEC = 52,       /* offset 0x938 */
	PDRIVE_PINGROUP_AT6 = 75,	/* offset 0x994 */
	PDRIVE_PINGROUP_DAP5,
	PDRIVE_PINGROUP_VBUS,
	PDRIVE_PINGROUP_AO3,
	PDRIVE_PINGROUP_HVC,
	PDRIVE_PINGROUP_SDIO4,
	PDRIVE_PINGROUP_AO0,
	PMUX_DRVGRP_COUNT,
};

/*
 * Functions which can be assigned to each of the pin groups. The values here
 * bear no relation to the values programmed into pinmux registers and are
 * purely a convenience. The translation is done through a table search.
 */
enum pmux_func {
	PMUX_FUNC_AHB_CLK,
	PMUX_FUNC_APB_CLK,
	PMUX_FUNC_AUDIO_SYNC,
	PMUX_FUNC_CRT,
	PMUX_FUNC_DAP1,
	PMUX_FUNC_DAP2,
	PMUX_FUNC_DAP3,
	PMUX_FUNC_DAP4,
	PMUX_FUNC_DAP5,
	PMUX_FUNC_DISPA,
	PMUX_FUNC_DISPB,
	PMUX_FUNC_EMC_TEST0_DLL,
	PMUX_FUNC_EMC_TEST1_DLL,
	PMUX_FUNC_GMI,
	PMUX_FUNC_GMI_INT,
	PMUX_FUNC_HDMI,
	PMUX_FUNC_I2C1,
	PMUX_FUNC_I2C2,
	PMUX_FUNC_I2C3,
	PMUX_FUNC_IDE,
	PMUX_FUNC_KBC,
	PMUX_FUNC_MIO,
	PMUX_FUNC_MIPI_HS,
	PMUX_FUNC_NAND,
	PMUX_FUNC_OSC,
	PMUX_FUNC_OWR,
	PMUX_FUNC_PCIE,
	PMUX_FUNC_PLLA_OUT,
	PMUX_FUNC_PLLC_OUT1,
	PMUX_FUNC_PLLM_OUT1,
	PMUX_FUNC_PLLP_OUT2,
	PMUX_FUNC_PLLP_OUT3,
	PMUX_FUNC_PLLP_OUT4,
	PMUX_FUNC_PWM,
	PMUX_FUNC_PWR_INTR,
	PMUX_FUNC_PWR_ON,
	PMUX_FUNC_RTCK,
	PMUX_FUNC_SDMMC1,
	PMUX_FUNC_SDMMC2,
	PMUX_FUNC_SDMMC3,
	PMUX_FUNC_SDMMC4,
	PMUX_FUNC_SFLASH,
	PMUX_FUNC_SPDIF,
	PMUX_FUNC_SPI1,
	PMUX_FUNC_SPI2,
	PMUX_FUNC_SPI2_ALT,
	PMUX_FUNC_SPI3,
	PMUX_FUNC_SPI4,
	PMUX_FUNC_TRACE,
	PMUX_FUNC_TWC,
	PMUX_FUNC_UARTA,
	PMUX_FUNC_UARTB,
	PMUX_FUNC_UARTC,
	PMUX_FUNC_UARTD,
	PMUX_FUNC_UARTE,
	PMUX_FUNC_ULPI,
	PMUX_FUNC_VI,
	PMUX_FUNC_VI_SENSOR_CLK,
	PMUX_FUNC_XIO,
	/* End of Tegra2 MUX selectors */
	PMUX_FUNC_BLINK,
	PMUX_FUNC_CEC,
	PMUX_FUNC_CLK12,
	PMUX_FUNC_DAP,
	PMUX_FUNC_DAPSDMMC2,
	PMUX_FUNC_DDR,
	PMUX_FUNC_DEV3,
	PMUX_FUNC_DTV,
	PMUX_FUNC_VI_ALT1,
	PMUX_FUNC_VI_ALT2,
	PMUX_FUNC_VI_ALT3,
	PMUX_FUNC_EMC_DLL,
	PMUX_FUNC_EXTPERIPH1,
	PMUX_FUNC_EXTPERIPH2,
	PMUX_FUNC_EXTPERIPH3,
	PMUX_FUNC_GMI_ALT,
	PMUX_FUNC_HDA,
	PMUX_FUNC_HSI,
	PMUX_FUNC_I2C4,
	PMUX_FUNC_I2C5,
	PMUX_FUNC_I2CPWR,
	PMUX_FUNC_I2S0,
	PMUX_FUNC_I2S1,
	PMUX_FUNC_I2S2,
	PMUX_FUNC_I2S3,
	PMUX_FUNC_I2S4,
	PMUX_FUNC_NAND_ALT,
	PMUX_FUNC_POPSDIO4,
	PMUX_FUNC_POPSDMMC4,
	PMUX_FUNC_PWM0,
	PMUX_FUNC_PWM1,
	PMUX_FUNC_PWM2,
	PMUX_FUNC_PWM3,
	PMUX_FUNC_SATA,
	PMUX_FUNC_SPI5,
	PMUX_FUNC_SPI6,
	PMUX_FUNC_SYSCLK,
	PMUX_FUNC_VGP1,
	PMUX_FUNC_VGP2,
	PMUX_FUNC_VGP3,
	PMUX_FUNC_VGP4,
	PMUX_FUNC_VGP5,
	PMUX_FUNC_VGP6,
	/* End of Tegra3 MUX selectors */
	PMUX_FUNC_USB,
	PMUX_FUNC_SOC,
	PMUX_FUNC_CPU,
	PMUX_FUNC_CLK,
	PMUX_FUNC_PWRON,
	PMUX_FUNC_PMI,
	PMUX_FUNC_CLDVFS,
	PMUX_FUNC_RESET_OUT_N,
	/* End of Tegra114 MUX selectors */

	PMUX_FUNC_COUNT,

	PMUX_FUNC_INVALID = 0x4000,
	PMUX_FUNC_RSVD1 = 0x8000,
	PMUX_FUNC_RSVD2 = 0x8001,
	PMUX_FUNC_RSVD3 = 0x8002,
	PMUX_FUNC_RSVD4 = 0x8003,
};

#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#define TEGRA_PMX_HAS_RCV_SEL
#define TEGRA_PMX_HAS_DRVGRPS
#include <asm/arch-tegra/pinmux.h>

#endif /* _TEGRA114_PINMUX_H_ */
Commit	Line	Data
2fc65e28 TW	1	/*
	2	* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#ifndef _TEGRA114_PINMUX_H_
	18	#define _TEGRA114_PINMUX_H_
	19
	20	/*
	21	* Pin groups which we adjust. There are three basic attributes of each pin
	22	* group which use this enum:
	23	*
	24	* - function
	25	* - pullup / pulldown
	26	* - tristate or normal
	27	*/
	28	enum pmux_pingrp {
	29	PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
	30	PINGRP_ULPI_DATA1,
	31	PINGRP_ULPI_DATA2,
	32	PINGRP_ULPI_DATA3,
	33	PINGRP_ULPI_DATA4,
	34	PINGRP_ULPI_DATA5,
	35	PINGRP_ULPI_DATA6,
	36	PINGRP_ULPI_DATA7,
	37	PINGRP_ULPI_CLK,
	38	PINGRP_ULPI_DIR,
	39	PINGRP_ULPI_NXT,
	40	PINGRP_ULPI_STP,
	41	PINGRP_DAP3_FS,
	42	PINGRP_DAP3_DIN,
	43	PINGRP_DAP3_DOUT,
	44	PINGRP_DAP3_SCLK,
	45	PINGRP_GPIO_PV0,
	46	PINGRP_GPIO_PV1,
	47	PINGRP_SDMMC1_CLK,
	48	PINGRP_SDMMC1_CMD,
	49	PINGRP_SDMMC1_DAT3,
	50	PINGRP_SDMMC1_DAT2,
	51	PINGRP_SDMMC1_DAT1,
	52	PINGRP_SDMMC1_DAT0,
8b7776b9	53	PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
2fc65e28	54	PINGRP_CLK2_REQ,
8b7776b9	55	PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
2fc65e28 TW	56	PINGRP_DDC_SCL,
2fc65e28 TW	57	PINGRP_DDC_SDA,
8b7776b9	58	PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
2fc65e28 TW	59	PINGRP_UART2_TXD,
	60	PINGRP_UART2_RTS_N,
	61	PINGRP_UART2_CTS_N,
	62	PINGRP_UART3_TXD,
	63	PINGRP_UART3_RXD,
	64	PINGRP_UART3_CTS_N,
	65	PINGRP_UART3_RTS_N,
	66	PINGRP_GPIO_PU0,
	67	PINGRP_GPIO_PU1,
	68	PINGRP_GPIO_PU2,
	69	PINGRP_GPIO_PU3,
	70	PINGRP_GPIO_PU4,
	71	PINGRP_GPIO_PU5,
	72	PINGRP_GPIO_PU6,
	73	PINGRP_GEN1_I2C_SDA,
	74	PINGRP_GEN1_I2C_SCL,
	75	PINGRP_DAP4_FS,
	76	PINGRP_DAP4_DIN,
	77	PINGRP_DAP4_DOUT,
	78	PINGRP_DAP4_SCLK,
	79	PINGRP_CLK3_OUT,
	80	PINGRP_CLK3_REQ,
	81	PINGRP_GMI_WP_N,
	82	PINGRP_GMI_IORDY,
	83	PINGRP_GMI_WAIT,
	84	PINGRP_GMI_ADV_N,
	85	PINGRP_GMI_CLK,
	86	PINGRP_GMI_CS0_N,
	87	PINGRP_GMI_CS1_N,
	88	PINGRP_GMI_CS2_N,
	89	PINGRP_GMI_CS3_N,
	90	PINGRP_GMI_CS4_N,
	91	PINGRP_GMI_CS6_N,
	92	PINGRP_GMI_CS7_N,
	93	PINGRP_GMI_AD0,
	94	PINGRP_GMI_AD1,
	95	PINGRP_GMI_AD2,
	96	PINGRP_GMI_AD3,
	97	PINGRP_GMI_AD4,
	98	PINGRP_GMI_AD5,
	99	PINGRP_GMI_AD6,
	100	PINGRP_GMI_AD7,
	101	PINGRP_GMI_AD8,
	102	PINGRP_GMI_AD9,
	103	PINGRP_GMI_AD10,
	104	PINGRP_GMI_AD11,
	105	PINGRP_GMI_AD12,
	106	PINGRP_GMI_AD13,
	107	PINGRP_GMI_AD14,
	108	PINGRP_GMI_AD15,
	109	PINGRP_GMI_A16,
	110	PINGRP_GMI_A17,
	111	PINGRP_GMI_A18,
	112	PINGRP_GMI_A19,
	113	PINGRP_GMI_WR_N,
	114	PINGRP_GMI_OE_N,
	115	PINGRP_GMI_DQS,
	116	PINGRP_GMI_RST_N,
	117	PINGRP_GEN2_I2C_SCL,
	118	PINGRP_GEN2_I2C_SDA,
	119	PINGRP_SDMMC4_CLK,
	120	PINGRP_SDMMC4_CMD,
	121	PINGRP_SDMMC4_DAT0,
	122	PINGRP_SDMMC4_DAT1,
123	PINGRP_SDMMC4_DAT2,
124	PINGRP_SDMMC4_DAT3,
125	PINGRP_SDMMC4_DAT4,
126	PINGRP_SDMMC4_DAT5,
127	PINGRP_SDMMC4_DAT6,
128	PINGRP_SDMMC4_DAT7,
8b7776b9	129	PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
2fc65e28 TW	130	PINGRP_GPIO_PCC1,
	131	PINGRP_GPIO_PBB0,
	132	PINGRP_CAM_I2C_SCL,
	133	PINGRP_CAM_I2C_SDA,
	134	PINGRP_GPIO_PBB3,
	135	PINGRP_GPIO_PBB4,
	136	PINGRP_GPIO_PBB5,
	137	PINGRP_GPIO_PBB6,
	138	PINGRP_GPIO_PBB7,
	139	PINGRP_GPIO_PCC2,
	140	PINGRP_JTAG_RTCK,
	141	PINGRP_PWR_I2C_SCL,
	142	PINGRP_PWR_I2C_SDA,
	143	PINGRP_KB_ROW0,
	144	PINGRP_KB_ROW1,
	145	PINGRP_KB_ROW2,
	146	PINGRP_KB_ROW3,
	147	PINGRP_KB_ROW4,
	148	PINGRP_KB_ROW5,
	149	PINGRP_KB_ROW6,
	150	PINGRP_KB_ROW7,
	151	PINGRP_KB_ROW8,
	152	PINGRP_KB_ROW9,
	153	PINGRP_KB_ROW10,
8b7776b9	154	PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
2fc65e28 TW	155	PINGRP_KB_COL1,
	156	PINGRP_KB_COL2,
	157	PINGRP_KB_COL3,
	158	PINGRP_KB_COL4,
	159	PINGRP_KB_COL5,
	160	PINGRP_KB_COL6,
	161	PINGRP_KB_COL7,
	162	PINGRP_CLK_32K_OUT,
	163	PINGRP_SYS_CLK_REQ,
	164	PINGRP_CORE_PWR_REQ,
	165	PINGRP_CPU_PWR_REQ,
	166	PINGRP_PWR_INT_N,
	167	PINGRP_CLK_32K_IN,
	168	PINGRP_OWR,
	169	PINGRP_DAP1_FS,
	170	PINGRP_DAP1_DIN,
	171	PINGRP_DAP1_DOUT,
	172	PINGRP_DAP1_SCLK,
	173	PINGRP_CLK1_REQ,
	174	PINGRP_CLK1_OUT,
	175	PINGRP_SPDIF_IN,
	176	PINGRP_SPDIF_OUT,
	177	PINGRP_DAP2_FS,
	178	PINGRP_DAP2_DIN,
	179	PINGRP_DAP2_DOUT,
	180	PINGRP_DAP2_SCLK,
8b7776b9 TW	181	PINGRP_DVFS_PWM,
	182	PINGRP_GPIO_X1_AUD,
	183	PINGRP_GPIO_X3_AUD,
	184	PINGRP_DVFS_CLK,
	185	PINGRP_GPIO_X4_AUD,
	186	PINGRP_GPIO_X5_AUD,
	187	PINGRP_GPIO_X6_AUD,
	188	PINGRP_GPIO_X7_AUD,
	189	PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
2fc65e28 TW	190	PINGRP_SDMMC3_CMD,
	191	PINGRP_SDMMC3_DAT0,
	192	PINGRP_SDMMC3_DAT1,
	193	PINGRP_SDMMC3_DAT2,
	194	PINGRP_SDMMC3_DAT3,
8b7776b9	195	PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
2fc65e28 TW	196	PINGRP_SDMMC1_WP_N,
2fc65e28 TW	197	PINGRP_SDMMC3_CD_N,
8b7776b9 TW	198	PINGRP_GPIO_W2_AUD,
	199	PINGRP_GPIO_W3_AUD,
	200	PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
2fc65e28 TW	201	PINGRP_USB_VBUS_EN1,
	202	PINGRP_SDMMC3_CLK_LB_IN,
	203	PINGRP_SDMMC3_CLK_LB_OUT,
8b7776b9	204	PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
dfb42fc9	205	PMUX_PINGRP_COUNT,
2fc65e28 TW	206	};
2fc65e28 TW	207
dfb42fc9	208	enum pmux_drvgrp {
2fc65e28 TW	209	PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
	210	PDRIVE_PINGROUP_AO2,
	211	PDRIVE_PINGROUP_AT1,
	212	PDRIVE_PINGROUP_AT2,
	213	PDRIVE_PINGROUP_AT3,
	214	PDRIVE_PINGROUP_AT4,
	215	PDRIVE_PINGROUP_AT5,
	216	PDRIVE_PINGROUP_CDEV1,
	217	PDRIVE_PINGROUP_CDEV2,
477393e7	218	PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
2fc65e28 TW	219	PDRIVE_PINGROUP_DAP2,
	220	PDRIVE_PINGROUP_DAP3,
	221	PDRIVE_PINGROUP_DAP4,
	222	PDRIVE_PINGROUP_DBG,
477393e7	223	PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
2fc65e28 TW	224	PDRIVE_PINGROUP_SPI,
	225	PDRIVE_PINGROUP_UAA,
	226	PDRIVE_PINGROUP_UAB,
	227	PDRIVE_PINGROUP_UART2,
	228	PDRIVE_PINGROUP_UART3,
477393e7 TW	229	PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
477393e7 TW	230	PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
2fc65e28	231	PDRIVE_PINGROUP_GMA,
477393e7	232	PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
2fc65e28 TW	233	PDRIVE_PINGROUP_GMF,
	234	PDRIVE_PINGROUP_GMG,
	235	PDRIVE_PINGROUP_GMH,
	236	PDRIVE_PINGROUP_OWR,
	237	PDRIVE_PINGROUP_UAD,
2fc65e28 TW	238	PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
2fc65e28 TW	239	PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
477393e7	240	PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
2fc65e28 TW	241	PDRIVE_PINGROUP_DAP5,
2fc65e28 TW	242	PDRIVE_PINGROUP_VBUS,
477393e7 TW	243	PDRIVE_PINGROUP_AO3,
	244	PDRIVE_PINGROUP_HVC,
	245	PDRIVE_PINGROUP_SDIO4,
	246	PDRIVE_PINGROUP_AO0,
dfb42fc9	247	PMUX_DRVGRP_COUNT,
2fc65e28 TW	248	};
	249
	250	/*
	251	* Functions which can be assigned to each of the pin groups. The values here
	252	* bear no relation to the values programmed into pinmux registers and are
	253	* purely a convenience. The translation is done through a table search.
	254	*/
	255	enum pmux_func {
	256	PMUX_FUNC_AHB_CLK,
	257	PMUX_FUNC_APB_CLK,
	258	PMUX_FUNC_AUDIO_SYNC,
	259	PMUX_FUNC_CRT,
	260	PMUX_FUNC_DAP1,
	261	PMUX_FUNC_DAP2,
	262	PMUX_FUNC_DAP3,
	263	PMUX_FUNC_DAP4,
	264	PMUX_FUNC_DAP5,
	265	PMUX_FUNC_DISPA,
	266	PMUX_FUNC_DISPB,
	267	PMUX_FUNC_EMC_TEST0_DLL,
	268	PMUX_FUNC_EMC_TEST1_DLL,
	269	PMUX_FUNC_GMI,
	270	PMUX_FUNC_GMI_INT,
	271	PMUX_FUNC_HDMI,
	272	PMUX_FUNC_I2C1,
	273	PMUX_FUNC_I2C2,
	274	PMUX_FUNC_I2C3,
	275	PMUX_FUNC_IDE,
	276	PMUX_FUNC_KBC,
	277	PMUX_FUNC_MIO,
	278	PMUX_FUNC_MIPI_HS,
	279	PMUX_FUNC_NAND,
	280	PMUX_FUNC_OSC,
	281	PMUX_FUNC_OWR,
	282	PMUX_FUNC_PCIE,
	283	PMUX_FUNC_PLLA_OUT,
	284	PMUX_FUNC_PLLC_OUT1,
	285	PMUX_FUNC_PLLM_OUT1,
	286	PMUX_FUNC_PLLP_OUT2,
	287	PMUX_FUNC_PLLP_OUT3,
	288	PMUX_FUNC_PLLP_OUT4,
	289	PMUX_FUNC_PWM,
	290	PMUX_FUNC_PWR_INTR,
	291	PMUX_FUNC_PWR_ON,
	292	PMUX_FUNC_RTCK,
	293	PMUX_FUNC_SDMMC1,
	294	PMUX_FUNC_SDMMC2,
	295	PMUX_FUNC_SDMMC3,
	296	PMUX_FUNC_SDMMC4,
	297	PMUX_FUNC_SFLASH,
	298	PMUX_FUNC_SPDIF,
	299	PMUX_FUNC_SPI1,
	300	PMUX_FUNC_SPI2,
	301	PMUX_FUNC_SPI2_ALT,
	302	PMUX_FUNC_SPI3,
	303	PMUX_FUNC_SPI4,
	304	PMUX_FUNC_TRACE,
	305	PMUX_FUNC_TWC,
	306	PMUX_FUNC_UARTA,
	307	PMUX_FUNC_UARTB,
	308	PMUX_FUNC_UARTC,
	309	PMUX_FUNC_UARTD,
	310	PMUX_FUNC_UARTE,
	311	PMUX_FUNC_ULPI,
312	PMUX_FUNC_VI,
313	PMUX_FUNC_VI_SENSOR_CLK,
314	PMUX_FUNC_XIO,
8b7776b9	315	/* End of Tegra2 MUX selectors */
2fc65e28 TW	316	PMUX_FUNC_BLINK,
	317	PMUX_FUNC_CEC,
	318	PMUX_FUNC_CLK12,
	319	PMUX_FUNC_DAP,
	320	PMUX_FUNC_DAPSDMMC2,
	321	PMUX_FUNC_DDR,
	322	PMUX_FUNC_DEV3,
	323	PMUX_FUNC_DTV,
	324	PMUX_FUNC_VI_ALT1,
	325	PMUX_FUNC_VI_ALT2,
	326	PMUX_FUNC_VI_ALT3,
	327	PMUX_FUNC_EMC_DLL,
	328	PMUX_FUNC_EXTPERIPH1,
	329	PMUX_FUNC_EXTPERIPH2,
	330	PMUX_FUNC_EXTPERIPH3,
	331	PMUX_FUNC_GMI_ALT,
	332	PMUX_FUNC_HDA,
	333	PMUX_FUNC_HSI,
	334	PMUX_FUNC_I2C4,
	335	PMUX_FUNC_I2C5,
	336	PMUX_FUNC_I2CPWR,
	337	PMUX_FUNC_I2S0,
	338	PMUX_FUNC_I2S1,
	339	PMUX_FUNC_I2S2,
	340	PMUX_FUNC_I2S3,
	341	PMUX_FUNC_I2S4,
	342	PMUX_FUNC_NAND_ALT,
	343	PMUX_FUNC_POPSDIO4,
	344	PMUX_FUNC_POPSDMMC4,
	345	PMUX_FUNC_PWM0,
	346	PMUX_FUNC_PWM1,
	347	PMUX_FUNC_PWM2,
	348	PMUX_FUNC_PWM3,
	349	PMUX_FUNC_SATA,
	350	PMUX_FUNC_SPI5,
	351	PMUX_FUNC_SPI6,
	352	PMUX_FUNC_SYSCLK,
	353	PMUX_FUNC_VGP1,
	354	PMUX_FUNC_VGP2,
	355	PMUX_FUNC_VGP3,
	356	PMUX_FUNC_VGP4,
	357	PMUX_FUNC_VGP5,
	358	PMUX_FUNC_VGP6,
8b7776b9	359	/* End of Tegra3 MUX selectors */
2fc65e28 TW	360	PMUX_FUNC_USB,
	361	PMUX_FUNC_SOC,
	362	PMUX_FUNC_CPU,
	363	PMUX_FUNC_CLK,
	364	PMUX_FUNC_PWRON,
	365	PMUX_FUNC_PMI,
	366	PMUX_FUNC_CLDVFS,
	367	PMUX_FUNC_RESET_OUT_N,
8b7776b9	368	/* End of Tegra114 MUX selectors */
2fc65e28	369
e2969957	370	PMUX_FUNC_COUNT,
2fc65e28	371
8b7776b9	372	PMUX_FUNC_INVALID = 0x4000,
2fc65e28 TW	373	PMUX_FUNC_RSVD1 = 0x8000,
	374	PMUX_FUNC_RSVD2 = 0x8001,
	375	PMUX_FUNC_RSVD3 = 0x8002,
	376	PMUX_FUNC_RSVD4 = 0x8003,
	377	};
	378
e2969957 SW	379	#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
e2969957 SW	380	#define TEGRA_PMX_HAS_RCV_SEL
dfb42fc9	381	#define TEGRA_PMX_HAS_DRVGRPS
e2969957	382	#include <asm/arch-tegra/pinmux.h>
2fc65e28	383
e2969957	384	#endif /* _TEGRA114_PINMUX_H_ */