[thirdparty/u-boot.git] / arch / arm / include / asm / arch-tegra124 / clock.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2010-2013
 * NVIDIA Corporation <www.nvidia.com>
 */

/* Tegra124 clock control definitions */

#ifndef _TEGRA124_CLOCK_H_
#define _TEGRA124_CLOCK_H_

#include <asm/arch-tegra/clock.h>

/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_FREQ_SHIFT          28
#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)

/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
#define PLLC_IDDQ			(1 << 26)

/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */
#define SOR0_CLK_SEL0			(1 << 14)
#define SOR0_CLK_SEL1			(1 << 15)

int tegra_plle_enable(void);

void clock_sor_enable_edp_clock(void);

/**
 * clock_set_display_rate() - Set the display clock rate
 *
 * @frequency: the requested PLLD frequency
 *
 * Return the PLLD frequenc (which may not quite what was requested), or 0
 * on failure
 */
u32 clock_set_display_rate(u32 frequency);

/**
 * clock_set_up_plldp() - Set up the EDP clock ready for use
 */
void clock_set_up_plldp(void);

#endif	/* _TEGRA124_CLOCK_H_ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
999c6baf TW	2	/*
	3	* (C) Copyright 2010-2013
	4	* NVIDIA Corporation <www.nvidia.com>
999c6baf TW	5	*/
	6
	7	/* Tegra124 clock control definitions */
	8
	9	#ifndef _TEGRA124_CLOCK_H_
	10	#define _TEGRA124_CLOCK_H_
	11
	12	#include <asm/arch-tegra/clock.h>
	13
	14	/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
	15	#define OSC_FREQ_SHIFT 28
	16	#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
	17
aba11d44 TR	18	/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
	19	#define PLLC_IDDQ (1 << 26)
	20
96e82a25 SG	21	/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */
	22	#define SOR0_CLK_SEL0 (1 << 14)
	23	#define SOR0_CLK_SEL1 (1 << 15)
	24
a7230745 TR	25	int tegra_plle_enable(void);
a7230745 TR	26
96e82a25 SG	27	void clock_sor_enable_edp_clock(void);
	28
	29	/**
	30	* clock_set_display_rate() - Set the display clock rate
	31	*
	32	* @frequency: the requested PLLD frequency
	33	*
	34	* Return the PLLD frequenc (which may not quite what was requested), or 0
	35	* on failure
	36	*/
	37	u32 clock_set_display_rate(u32 frequency);
	38
	39	/**
	40	* clock_set_up_plldp() - Set up the EDP clock ready for use
	41	*/
	42	void clock_set_up_plldp(void);
	43
999c6baf	44	#endif /* _TEGRA124_CLOCK_H_ */