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be72e0c8 JR |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2009 | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
be72e0c8 JR |
5 | */ |
6 | ||
7 | #ifndef __ASM_ARCH_HARDWARE_H | |
8 | #define __ASM_ARCH_HARDWARE_H | |
9 | ||
10 | /* Peripheral clusters */ | |
11 | ||
12 | #define U8500_PER3_BASE 0x80000000 | |
13 | #define U8500_PER2_BASE 0x80110000 | |
14 | #define U8500_PER1_BASE 0x80120000 | |
15 | #define U8500_PER4_BASE 0x80150000 | |
16 | ||
17 | #define U8500_PER6_BASE 0xa03c0000 | |
18 | #define U8500_PER7_BASE 0xa03d0000 | |
19 | #define U8500_PER5_BASE 0xa03e0000 | |
20 | ||
21 | /* GPIO */ | |
22 | ||
23 | #define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) | |
24 | #define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80) | |
25 | ||
26 | #define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000) | |
27 | #define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80) | |
28 | #define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100) | |
29 | #define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180) | |
30 | ||
31 | #define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000) | |
32 | #define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80) | |
33 | ||
34 | #define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000) | |
35 | ||
36 | /* Per7 */ | |
37 | #define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000) | |
38 | ||
39 | /* Per6 */ | |
40 | #define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000) | |
41 | #define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000) | |
42 | #define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) | |
43 | ||
44 | /* Per5 */ | |
45 | #define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) | |
46 | ||
47 | /* Per4 */ | |
48 | #define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) | |
b95f9ec7 | 49 | #define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) |
be72e0c8 JR |
50 | |
51 | /* Per3 */ | |
52 | #define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) | |
53 | #define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) | |
54 | ||
55 | /* Per2 */ | |
56 | #define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) | |
57 | ||
58 | /* Per1 */ | |
59 | #define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) | |
60 | #define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) | |
61 | #define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) | |
62 | ||
63 | /* Last page of Boot ROM */ | |
75dfe964 MP |
64 | #define U8500_BOOTROM_BASE 0x90000000 |
65 | #define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4) | |
66 | #define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4) | |
be72e0c8 | 67 | |
b95f9ec7 | 68 | /* AB8500 specifics */ |
75dfe964 MP |
69 | |
70 | /* address bank */ | |
71 | #define AB8500_REGU_CTRL2 0x0004 | |
b95f9ec7 | 72 | #define AB8500_MISC 0x0010 |
75dfe964 MP |
73 | |
74 | /* registers */ | |
75 | #define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A | |
76 | #define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 | |
77 | #define AB8500_REV_REG 0x1080 | |
78 | ||
b95f9ec7 MP |
79 | #define AB8500_GPIO_SEL2_REG 0x1001 |
80 | #define AB8500_GPIO_DIR2_REG 0x1011 | |
81 | #define AB8500_GPIO_DIR4_REG 0x1013 | |
82 | #define AB8500_GPIO_SEL4_REG 0x1003 | |
83 | #define AB8500_GPIO_OUT2_REG 0x1021 | |
84 | #define AB8500_GPIO_OUT4_REG 0x1023 | |
85 | ||
75dfe964 MP |
86 | #define LDO_VAUX3_ENABLE_MASK 0x3 |
87 | #define LDO_VAUX3_ENABLE_VAL 0x1 | |
88 | #define LDO_VAUX3_SEL_MASK 0xf | |
89 | #define LDO_VAUX3_SEL_2V9 0xd | |
90 | #define LDO_VAUX3_V2_SEL_MASK 0x7 | |
91 | #define LDO_VAUX3_V2_SEL_2V91 0x7 | |
92 | ||
93 | ||
be72e0c8 | 94 | #endif /* __ASM_ARCH_HARDWARE_H */ |