[thirdparty/u-boot.git] / arch / arm / include / asm / arch-vf610 / crm_regs.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2013-2014 Freescale Semiconductor, Inc.
 */

#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__

#ifndef __ASSEMBLY__

#include <linux/types.h>

/* Clock Controller Module (CCM) */
struct ccm_reg {
	u32 ccr;
	u32 csr;
	u32 ccsr;
	u32 cacrr;
	u32 cscmr1;
	u32 cscdr1;
	u32 cscdr2;
	u32 cscdr3;
	u32 cscmr2;
	u32 cscdr4;
	u32 ctor;
	u32 clpcr;
	u32 cisr;
	u32 cimr;
	u32 ccosr;
	u32 cgpr;
	u32 ccgr0;
	u32 ccgr1;
	u32 ccgr2;
	u32 ccgr3;
	u32 ccgr4;
	u32 ccgr5;
	u32 ccgr6;
	u32 ccgr7;
	u32 ccgr8;
	u32 ccgr9;
	u32 ccgr10;
	u32 ccgr11;
	u32 cmeor0;
	u32 cmeor1;
	u32 cmeor2;
	u32 cmeor3;
	u32 cmeor4;
	u32 cmeor5;
	u32 cppdsr;
	u32 ccowr;
	u32 ccpgr0;
	u32 ccpgr1;
	u32 ccpgr2;
	u32 ccpgr3;
};

/* Analog components control digital interface (ANADIG) */
struct anadig_reg {
	u32 reserved_0x000[4];
	u32 pll3_ctrl;
	u32 reserved_0x014[3];
	u32 pll7_ctrl;
	u32 reserved_0x024[3];
	u32 pll2_ctrl;
	u32 reserved_0x034[3];
	u32 pll2_ss;
	u32 reserved_0x044[3];
	u32 pll2_num;
	u32 reserved_0x054[3];
	u32 pll2_denom;
	u32 reserved_0x064[3];
	u32 pll4_ctrl;
	u32 reserved_0x074[3];
	u32 pll4_num;
	u32 reserved_0x084[3];
	u32 pll4_denom;
	u32 reserved_0x094[3];
	u32 pll6_ctrl;
	u32 reserved_0x0A4[3];
	u32 pll6_num;
	u32 reserved_0x0B4[3];
	u32 pll6_denom;
	u32 reserved_0x0C4[7];
	u32 pll5_ctrl;
	u32 reserved_0x0E4[3];
	u32 pll3_pfd;
	u32 reserved_0x0F4[3];
	u32 pll2_pfd;
	u32 reserved_0x104[3];
	u32 reg_1p1;
	u32 reserved_0x114[3];
	u32 reg_3p0;
	u32 reserved_0x124[3];
	u32 reg_2p5;
	u32 reserved_0x134[7];
	u32 ana_misc0;
	u32 reserved_0x154[3];
	u32 ana_misc1;
	u32 reserved_0x164[63];
	u32 anadig_digprog;
	u32 reserved_0x264[3];
	u32 pll1_ctrl;
	u32 reserved_0x274[3];
	u32 pll1_ss;
	u32 reserved_0x284[3];
	u32 pll1_num;
	u32 reserved_0x294[3];
	u32 pll1_denom;
	u32 reserved_0x2A4[3];
	u32 pll1_pdf;
	u32 reserved_0x2B4[3];
	u32 pll_lock;
};
#endif

#define CCM_CCR_FIRC_EN				(1 << 16)
#define CCM_CCR_OSCNT_MASK			0xff
#define CCM_CCR_OSCNT(v)			((v) & 0xff)

#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET	19
#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK		(0x7 << 19)
#define CCM_CCSR_PLL2_PFD_CLK_SEL(v)		(((v) & 0x7) << 19)

#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET	16
#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK		(0x7 << 16)
#define CCM_CCSR_PLL1_PFD_CLK_SEL(v)		(((v) & 0x7) << 16)

#define CCM_CCSR_PLL2_PFD4_EN			(1 << 15)
#define CCM_CCSR_PLL2_PFD3_EN			(1 << 14)
#define CCM_CCSR_PLL2_PFD2_EN			(1 << 13)
#define CCM_CCSR_PLL2_PFD1_EN			(1 << 12)
#define CCM_CCSR_PLL1_PFD4_EN			(1 << 11)
#define CCM_CCSR_PLL1_PFD3_EN			(1 << 10)
#define CCM_CCSR_PLL1_PFD2_EN			(1 << 9)
#define CCM_CCSR_PLL1_PFD1_EN			(1 << 8)

#define CCM_CCSR_DDRC_CLK_SEL(v)		((v) << 6)
#define CCM_CCSR_FAST_CLK_SEL(v)		((v) << 5)

#define CCM_CCSR_SYS_CLK_SEL_OFFSET		0
#define CCM_CCSR_SYS_CLK_SEL_MASK		0x7
#define CCM_CCSR_SYS_CLK_SEL(v)			((v) & 0x7)

#define CCM_CACRR_IPG_CLK_DIV_OFFSET		11
#define CCM_CACRR_IPG_CLK_DIV_MASK		(0x3 << 11)
#define CCM_CACRR_IPG_CLK_DIV(v)		(((v) & 0x3) << 11)
#define CCM_CACRR_BUS_CLK_DIV_OFFSET		3
#define CCM_CACRR_BUS_CLK_DIV_MASK		(0x7 << 3)
#define CCM_CACRR_BUS_CLK_DIV(v)		(((v) & 0x7) << 3)
#define CCM_CACRR_ARM_CLK_DIV_OFFSET		0
#define CCM_CACRR_ARM_CLK_DIV_MASK		0x7
#define CCM_CACRR_ARM_CLK_DIV(v)		((v) & 0x7)

#define CCM_CSCMR1_DCU1_CLK_SEL			(1 << 29)
#define CCM_CSCMR1_DCU0_CLK_SEL			(1 << 28)

#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET		22
#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK		(0x3 << 22)
#define CCM_CSCMR1_QSPI0_CLK_SEL(v)		(((v) & 0x3) << 22)
#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET	18
#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK		(0x3 << 18)
#define CCM_CSCMR1_ESDHC1_CLK_SEL(v)		(((v) & 0x3) << 18)
#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET		12
#define CCM_CSCMR1_NFC_CLK_SEL_MASK		(0x3 << 12)
#define CCM_CSCMR1_NFC_CLK_SEL(v)		(((v) & 0x3) << 12)

#define CCM_CSCDR1_RMII_CLK_EN			(1 << 24)

#define CCM_CSCDR2_NFC_EN			(1 << 9)
#define CCM_CSCDR2_NFC_FRAC_DIV_EN		(1 << 13)
#define CCM_CSCDR2_NFC_CLK_INV			(1 << 14)
#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET		4
#define CCM_CSCDR2_NFC_FRAC_DIV_MASK		(0xf << 4)
#define CCM_CSCDR2_NFC_FRAC_DIV(v)		(((v) & 0xf) << 4)

#define CCM_CSCDR2_ESDHC1_EN			(1 << 29)
#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET	20
#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK		(0xf << 20)
#define CCM_CSCDR2_ESDHC1_CLK_DIV(v)		(((v) & 0xf) << 20)

#define CCM_CSCDR3_DCU1_EN			(1 << 23)
#define CCM_CSCDR3_DCU1_DIV_MASK		(0x7 << 20)
#define CCM_CSCDR3_DCU1_DIV(v)			(((v) & 0x7) << 20)
#define CCM_CSCDR3_DCU0_EN			(1 << 19)
#define CCM_CSCDR3_DCU0_DIV_MASK		(0x7 << 16)
#define CCM_CSCDR3_DCU0_DIV(v)			(((v) & 0x7) << 16)

#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET		13
#define CCM_CSCDR3_NFC_PRE_DIV_MASK		(0x7 << 13)
#define CCM_CSCDR3_NFC_PRE_DIV(v)		(((v) & 0x7) << 13)
#define CCM_CSCDR3_QSPI0_EN			(1 << 4)
#define CCM_CSCDR3_QSPI0_DIV(v)			((v) << 3)
#define CCM_CSCDR3_QSPI0_X2_DIV(v)		((v) << 2)
#define CCM_CSCDR3_QSPI0_X4_DIV(v)		((v) & 0x3)

#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET		4
#define CCM_CSCMR2_RMII_CLK_SEL_MASK		(0x3 << 4)
#define CCM_CSCMR2_RMII_CLK_SEL(v)		(((v) & 0x3) << 4)

#define CCM_REG_CTRL_MASK			0xffffffff
#define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
#define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
#define CCM_CCGR0_DSPI0_CTRL_MASK		(0x3 << 24)
#define CCM_CCGR0_DSPI1_CTRL_MASK		(0x3 << 26)
#define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
#define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
#define CCM_CCGR1_TCON0_CTRL_MASK		(0x3 << 26)
#define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
#define CCM_CCGR2_QSPI0_CTRL_MASK		(0x3 << 8)
#define CCM_CCGR2_IOMUXC_CTRL_MASK		(0x3 << 16)
#define CCM_CCGR2_PORTA_CTRL_MASK		(0x3 << 18)
#define CCM_CCGR2_PORTB_CTRL_MASK		(0x3 << 20)
#define CCM_CCGR2_PORTC_CTRL_MASK		(0x3 << 22)
#define CCM_CCGR2_PORTD_CTRL_MASK		(0x3 << 24)
#define CCM_CCGR2_PORTE_CTRL_MASK		(0x3 << 26)
#define CCM_CCGR3_ANADIG_CTRL_MASK		0x3
#define CCM_CCGR3_SCSC_CTRL_MASK        (0x3 << 4)
#define CCM_CCGR3_DCU0_CTRL_MASK		(0x3 << 16)
#define CCM_CCGR4_WKUP_CTRL_MASK		(0x3 << 20)
#define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
#define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
#define CCM_CCGR4_I2C0_CTRL_MASK		(0x3 << 12)
#define CCM_CCGR4_I2C1_CTRL_MASK		(0x3 << 14)
#define CCM_CCGR6_OCOTP_CTRL_MASK		(0x3 << 10)
#define CCM_CCGR6_DSPI2_CTRL_MASK		(0x3 << 24)
#define CCM_CCGR6_DSPI3_CTRL_MASK		(0x3 << 26)
#define CCM_CCGR6_DDRMC_CTRL_MASK		(0x3 << 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK		(0x3 << 4)
#define CCM_CCGR7_USBC1_CTRL_MASK       (0x3 << 8)
#define CCM_CCGR9_FEC0_CTRL_MASK		0x3
#define CCM_CCGR9_FEC1_CTRL_MASK		(0x3 << 2)
#define CCM_CCGR10_NFC_CTRL_MASK		0x3
#define CCM_CCGR10_I2C2_CTRL_MASK		(0x3 << 12)
#define CCM_CCGR10_I2C3_CTRL_MASK		(0x3 << 14)

#define ANADIG_PLL7_CTRL_BYPASS         (1 << 16)
#define ANADIG_PLL7_CTRL_ENABLE         (1 << 13)
#define ANADIG_PLL7_CTRL_POWERDOWN      (1 << 12)
#define ANADIG_PLL7_CTRL_DIV_SELECT     (1 << 1)
#define ANADIG_PLL5_CTRL_BYPASS                 (1 << 16)
#define ANADIG_PLL5_CTRL_ENABLE                 (1 << 13)
#define ANADIG_PLL5_CTRL_POWERDOWN              (1 << 12)
#define ANADIG_PLL5_CTRL_DIV_SELECT		1
#define ANADIG_PLL3_CTRL_BYPASS         (1 << 16)
#define ANADIG_PLL3_CTRL_ENABLE         (1 << 13)
#define ANADIG_PLL3_CTRL_POWERDOWN      (1 << 12)
#define ANADIG_PLL3_CTRL_DIV_SELECT     (1 << 1)
#define ANADIG_PLL2_CTRL_ENABLE			(1 << 13)
#define ANADIG_PLL2_CTRL_POWERDOWN		(1 << 12)
#define ANADIG_PLL2_CTRL_DIV_SELECT		1
#define ANADIG_PLL1_CTRL_ENABLE			(1 << 13)
#define ANADIG_PLL1_CTRL_POWERDOWN		(1 << 12)
#define ANADIG_PLL1_CTRL_DIV_SELECT		1

#define FASE_CLK_FREQ		24000000
#define SLOW_CLK_FREQ		32000
#define PLL1_PFD1_FREQ		500000000
#define PLL1_PFD2_FREQ		452000000
#define PLL1_PFD3_FREQ		396000000
#define PLL1_PFD4_FREQ		528000000
#define PLL1_MAIN_FREQ		528000000
#define PLL2_PFD1_FREQ		500000000
#define PLL2_PFD2_FREQ		396000000
#define PLL2_PFD3_FREQ		339000000
#define PLL2_PFD4_FREQ		413000000
#define PLL2_MAIN_FREQ		528000000
#define PLL3_MAIN_FREQ		480000000
#define PLL3_PFD3_FREQ		298000000
#define PLL5_MAIN_FREQ		500000000

#define ENET_EXTERNAL_CLK	50000000
#define AUDIO_EXTERNAL_CLK	24576000

#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
24e8bee5	2	/*
cb6d04d6	3	* Copyright 2013-2014 Freescale Semiconductor, Inc.
24e8bee5 AW	4	*/
	5
	6	#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
	7	#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
	8
	9	#ifndef __ASSEMBLY__
	10
80b9c3bb SA	11	#include <linux/types.h>
80b9c3bb SA	12
24e8bee5 AW	13	/* Clock Controller Module (CCM) */
	14	struct ccm_reg {
	15	u32 ccr;
	16	u32 csr;
	17	u32 ccsr;
	18	u32 cacrr;
	19	u32 cscmr1;
	20	u32 cscdr1;
	21	u32 cscdr2;
	22	u32 cscdr3;
	23	u32 cscmr2;
	24	u32 cscdr4;
	25	u32 ctor;
	26	u32 clpcr;
	27	u32 cisr;
	28	u32 cimr;
	29	u32 ccosr;
	30	u32 cgpr;
	31	u32 ccgr0;
	32	u32 ccgr1;
	33	u32 ccgr2;
	34	u32 ccgr3;
	35	u32 ccgr4;
	36	u32 ccgr5;
	37	u32 ccgr6;
	38	u32 ccgr7;
	39	u32 ccgr8;
	40	u32 ccgr9;
	41	u32 ccgr10;
	42	u32 ccgr11;
	43	u32 cmeor0;
	44	u32 cmeor1;
	45	u32 cmeor2;
	46	u32 cmeor3;
	47	u32 cmeor4;
	48	u32 cmeor5;
	49	u32 cppdsr;
	50	u32 ccowr;
	51	u32 ccpgr0;
	52	u32 ccpgr1;
	53	u32 ccpgr2;
	54	u32 ccpgr3;
	55	};
	56
	57	/* Analog components control digital interface (ANADIG) */
	58	struct anadig_reg {
25839c01	59	u32 reserved_0x000[4];
24e8bee5	60	u32 pll3_ctrl;
25839c01	61	u32 reserved_0x014[3];
24e8bee5	62	u32 pll7_ctrl;
25839c01	63	u32 reserved_0x024[3];
24e8bee5	64	u32 pll2_ctrl;
25839c01	65	u32 reserved_0x034[3];
24e8bee5	66	u32 pll2_ss;
25839c01	67	u32 reserved_0x044[3];
24e8bee5	68	u32 pll2_num;
25839c01	69	u32 reserved_0x054[3];
24e8bee5	70	u32 pll2_denom;
25839c01	71	u32 reserved_0x064[3];
24e8bee5	72	u32 pll4_ctrl;
25839c01	73	u32 reserved_0x074[3];
24e8bee5	74	u32 pll4_num;
25839c01	75	u32 reserved_0x084[3];
24e8bee5	76	u32 pll4_denom;
25839c01	77	u32 reserved_0x094[3];
24e8bee5	78	u32 pll6_ctrl;
25839c01	79	u32 reserved_0x0A4[3];
24e8bee5	80	u32 pll6_num;
25839c01	81	u32 reserved_0x0B4[3];
24e8bee5	82	u32 pll6_denom;
25839c01	83	u32 reserved_0x0C4[7];
24e8bee5	84	u32 pll5_ctrl;
25839c01	85	u32 reserved_0x0E4[3];
24e8bee5	86	u32 pll3_pfd;
25839c01	87	u32 reserved_0x0F4[3];
24e8bee5	88	u32 pll2_pfd;
25839c01	89	u32 reserved_0x104[3];
24e8bee5	90	u32 reg_1p1;
25839c01	91	u32 reserved_0x114[3];
24e8bee5	92	u32 reg_3p0;
25839c01	93	u32 reserved_0x124[3];
24e8bee5	94	u32 reg_2p5;
25839c01	95	u32 reserved_0x134[7];
24e8bee5	96	u32 ana_misc0;
25839c01	97	u32 reserved_0x154[3];
24e8bee5	98	u32 ana_misc1;
25839c01	99	u32 reserved_0x164[63];
24e8bee5	100	u32 anadig_digprog;
25839c01	101	u32 reserved_0x264[3];
24e8bee5	102	u32 pll1_ctrl;
25839c01	103	u32 reserved_0x274[3];
24e8bee5	104	u32 pll1_ss;
25839c01	105	u32 reserved_0x284[3];
24e8bee5	106	u32 pll1_num;
25839c01	107	u32 reserved_0x294[3];
24e8bee5	108	u32 pll1_denom;
25839c01	109	u32 reserved_0x2A4[3];
24e8bee5	110	u32 pll1_pdf;
25839c01	111	u32 reserved_0x2B4[3];
24e8bee5 AW	112	u32 pll_lock;
	113	};
	114	#endif
	115
	116	#define CCM_CCR_FIRC_EN (1 << 16)
	117	#define CCM_CCR_OSCNT_MASK 0xff
	118	#define CCM_CCR_OSCNT(v) ((v) & 0xff)
	119
	120	#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
	121	#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
	122	#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
	123
	124	#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
	125	#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
	126	#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
	127
	128	#define CCM_CCSR_PLL2_PFD4_EN (1 << 15)
	129	#define CCM_CCSR_PLL2_PFD3_EN (1 << 14)
	130	#define CCM_CCSR_PLL2_PFD2_EN (1 << 13)
	131	#define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
	132	#define CCM_CCSR_PLL1_PFD4_EN (1 << 11)
	133	#define CCM_CCSR_PLL1_PFD3_EN (1 << 10)
	134	#define CCM_CCSR_PLL1_PFD2_EN (1 << 9)
	135	#define CCM_CCSR_PLL1_PFD1_EN (1 << 8)
	136
	137	#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6)
	138	#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5)
	139
	140	#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
	141	#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
	142	#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
	143
	144	#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
	145	#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
	146	#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
	147	#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
	148	#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
	149	#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3)
	150	#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
	151	#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
	152	#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
	153
80b9c3bb SA	154	#define CCM_CSCMR1_DCU1_CLK_SEL (1 << 29)
	155	#define CCM_CSCMR1_DCU0_CLK_SEL (1 << 28)
	156
cb6d04d6 CF	157	#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22
	158	#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22)
	159	#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22)
24e8bee5 AW	160	#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
	161	#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
	162	#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
b0e31c7b SA	163	#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET 12
	164	#define CCM_CSCMR1_NFC_CLK_SEL_MASK (0x3 << 12)
	165	#define CCM_CSCMR1_NFC_CLK_SEL(v) (((v) & 0x3) << 12)
24e8bee5 AW	166
	167	#define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
	168
b0e31c7b SA	169	#define CCM_CSCDR2_NFC_EN (1 << 9)
	170	#define CCM_CSCDR2_NFC_FRAC_DIV_EN (1 << 13)
	171	#define CCM_CSCDR2_NFC_CLK_INV (1 << 14)
	172	#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET 4
	173	#define CCM_CSCDR2_NFC_FRAC_DIV_MASK (0xf << 4)
	174	#define CCM_CSCDR2_NFC_FRAC_DIV(v) (((v) & 0xf) << 4)
	175
24e8bee5 AW	176	#define CCM_CSCDR2_ESDHC1_EN (1 << 29)
	177	#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
	178	#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
	179	#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
	180
80b9c3bb SA	181	#define CCM_CSCDR3_DCU1_EN (1 << 23)
	182	#define CCM_CSCDR3_DCU1_DIV_MASK (0x7 << 20)
	183	#define CCM_CSCDR3_DCU1_DIV(v) (((v) & 0x7) << 20)
	184	#define CCM_CSCDR3_DCU0_EN (1 << 19)
	185	#define CCM_CSCDR3_DCU0_DIV_MASK (0x7 << 16)
	186	#define CCM_CSCDR3_DCU0_DIV(v) (((v) & 0x7) << 16)
	187
b0e31c7b SA	188	#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET 13
	189	#define CCM_CSCDR3_NFC_PRE_DIV_MASK (0x7 << 13)
	190	#define CCM_CSCDR3_NFC_PRE_DIV(v) (((v) & 0x7) << 13)
cb6d04d6 CF	191	#define CCM_CSCDR3_QSPI0_EN (1 << 4)
	192	#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3)
	193	#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2)
	194	#define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3)
	195
24e8bee5 AW	196	#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
	197	#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
	198	#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
	199
	200	#define CCM_REG_CTRL_MASK 0xffffffff
c7098965	201	#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
24e8bee5	202	#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
098d8584 BD	203	#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24)
098d8584 BD	204	#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
a94bb7a4	205	#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
24e8bee5	206	#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
80b9c3bb	207	#define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26)
24e8bee5	208	#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
cb6d04d6	209	#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8)
24e8bee5 AW	210	#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
	211	#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
	212	#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
	213	#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22)
	214	#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
	215	#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
	216	#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
8b4f9afa	217	#define CCM_CCGR3_SCSC_CTRL_MASK (0x3 << 4)
80b9c3bb	218	#define CCM_CCGR3_DCU0_CTRL_MASK (0x3 << 16)
24e8bee5 AW	219	#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
	220	#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
	221	#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
1221b3d7	222	#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
b44e60ac	223	#define CCM_CCGR4_I2C1_CTRL_MASK (0x3 << 14)
24e8bee5	224	#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
098d8584 BD	225	#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24)
098d8584 BD	226	#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26)
24e8bee5 AW	227	#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
24e8bee5 AW	228	#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
a94bb7a4	229	#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)
24e8bee5 AW	230	#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
24e8bee5 AW	231	#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
b0e31c7b	232	#define CCM_CCGR10_NFC_CTRL_MASK 0x3
b44e60ac AA	233	#define CCM_CCGR10_I2C2_CTRL_MASK (0x3 << 12)
b44e60ac AA	234	#define CCM_CCGR10_I2C3_CTRL_MASK (0x3 << 14)
24e8bee5	235
a94bb7a4 SM	236	#define ANADIG_PLL7_CTRL_BYPASS (1 << 16)
	237	#define ANADIG_PLL7_CTRL_ENABLE (1 << 13)
	238	#define ANADIG_PLL7_CTRL_POWERDOWN (1 << 12)
	239	#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1)
6c81a93d MZ	240	#define ANADIG_PLL5_CTRL_BYPASS (1 << 16)
	241	#define ANADIG_PLL5_CTRL_ENABLE (1 << 13)
	242	#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12)
	243	#define ANADIG_PLL5_CTRL_DIV_SELECT 1
a94bb7a4 SM	244	#define ANADIG_PLL3_CTRL_BYPASS (1 << 16)
	245	#define ANADIG_PLL3_CTRL_ENABLE (1 << 13)
	246	#define ANADIG_PLL3_CTRL_POWERDOWN (1 << 12)
	247	#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1)
24e8bee5 AW	248	#define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
	249	#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
	250	#define ANADIG_PLL2_CTRL_DIV_SELECT 1
	251	#define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
	252	#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
	253	#define ANADIG_PLL1_CTRL_DIV_SELECT 1
	254
	255	#define FASE_CLK_FREQ 24000000
	256	#define SLOW_CLK_FREQ 32000
	257	#define PLL1_PFD1_FREQ 500000000
	258	#define PLL1_PFD2_FREQ 452000000
	259	#define PLL1_PFD3_FREQ 396000000
	260	#define PLL1_PFD4_FREQ 528000000
	261	#define PLL1_MAIN_FREQ 528000000
	262	#define PLL2_PFD1_FREQ 500000000
	263	#define PLL2_PFD2_FREQ 396000000
	264	#define PLL2_PFD3_FREQ 339000000
	265	#define PLL2_PFD4_FREQ 413000000
	266	#define PLL2_MAIN_FREQ 528000000
	267	#define PLL3_MAIN_FREQ 480000000
	268	#define PLL3_PFD3_FREQ 298000000
	269	#define PLL5_MAIN_FREQ 500000000
	270
	271	#define ENET_EXTERNAL_CLK 50000000
	272	#define AUDIO_EXTERNAL_CLK 24576000
	273
	274	#endif /__ARCH_ARM_MACH_VF610_CCM_REGS_H__ /