[people/ms/u-boot.git] / arch / arm / include / asm / arch-zynqmp / hardware.h

/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H

#define ZYNQ_SERIAL_BASEADDR0	0xFF000000
#define ZYNQ_SERIAL_BASEADDR1	0xFF001000

#define ZYNQ_GEM_BASEADDR0	0xFF0B0000
#define ZYNQ_GEM_BASEADDR1	0xFF0C0000
#define ZYNQ_GEM_BASEADDR2	0xFF0D0000
#define ZYNQ_GEM_BASEADDR3	0xFF0E0000

#define ZYNQ_SPI_BASEADDR0	0xFF040000
#define ZYNQ_SPI_BASEADDR1	0xFF050000

#define ZYNQ_I2C_BASEADDR0	0xFF020000
#define ZYNQ_I2C_BASEADDR1	0xFF030000

#define ZYNQ_SDHCI_BASEADDR0	0xFF160000
#define ZYNQ_SDHCI_BASEADDR1	0xFF170000

#define ZYNQMP_SATA_BASEADDR	0xFD0C0000

#define ZYNQMP_CRL_APB_BASEADDR	0xFF5E0000
#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT	0x1000000

struct crlapb_regs {
	u32 reserved0[36];
	u32 cpu_r5_ctrl; /* 0x90 */
	u32 reserved1[37];
	u32 timestamp_ref_ctrl; /* 0x128 */
	u32 reserved2[53];
	u32 boot_mode; /* 0x200 */
	u32 reserved3[14];
	u32 rst_lpd_top; /* 0x23C */
	u32 reserved4[26];
};

#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)

#if defined(CONFIG_SECURE_IOU)
#define ZYNQMP_IOU_SCNTR	0xFF260000
#else
#define ZYNQMP_IOU_SCNTR	0xFF250000
#endif
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN	0x1
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG	0x2

struct iou_scntr {
	u32 counter_control_register;
	u32 reserved0[7];
	u32 base_frequency_id_register;
};

#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)

/* Bootmode setting values */
#define BOOT_MODES_MASK	0x0000000F
#define SD_MODE		0x00000003
#define EMMC_MODE	0x00000006
#define JTAG_MODE	0x00000000

#define ZYNQMP_IOU_SLCR_BASEADDR	0xFF180000

struct iou_slcr_regs {
	u32 mio_pin[78];
	u32 reserved[442];
};

#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)

#define ZYNQMP_RPU_BASEADDR	0xFF9A0000

struct rpu_regs {
	u32 rpu_glbl_ctrl;
	u32 reserved0[63];
	u32 rpu0_cfg; /* 0x100 */
	u32 reserved1[63];
	u32 rpu1_cfg; /* 0x200 */
};

#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)

#define ZYNQMP_CRF_APB_BASEADDR	0xFD1A0000

struct crfapb_regs {
	u32 reserved0[65];
	u32 rst_fpd_apu; /* 0x104 */
	u32 reserved1;
};

#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)

#define ZYNQMP_APU_BASEADDR	0xFD5C0000

struct apu_regs {
	u32 reserved0[16];
	u32 rvbar_addr0_l; /* 0x40 */
	u32 rvbar_addr0_h; /* 0x44 */
	u32 reserved1[20];
};

#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)

/* Board version value */
#define ZYNQMP_CSU_VERSION_SILICON	0x0
#define ZYNQMP_CSU_VERSION_EP108	0x1
#define ZYNQMP_CSU_VERSION_VELOCE	0x2
#define ZYNQMP_CSU_VERSION_QEMU		0x3

#endif /* _ASM_ARCH_HARDWARE_H */
Commit	Line	Data
84c7204b MS	1	/*
	2	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	3	* Michal Simek <michal.simek@xilinx.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef _ASM_ARCH_HARDWARE_H
	9	#define _ASM_ARCH_HARDWARE_H
	10
	11	#define ZYNQ_SERIAL_BASEADDR0 0xFF000000
	12	#define ZYNQ_SERIAL_BASEADDR1 0xFF001000
	13
cb7ea820 MS	14	#define ZYNQ_GEM_BASEADDR0 0xFF0B0000
	15	#define ZYNQ_GEM_BASEADDR1 0xFF0C0000
	16	#define ZYNQ_GEM_BASEADDR2 0xFF0D0000
	17	#define ZYNQ_GEM_BASEADDR3 0xFF0E0000
	18
48d7260d SDPP	19	#define ZYNQ_SPI_BASEADDR0 0xFF040000
	20	#define ZYNQ_SPI_BASEADDR1 0xFF050000
	21
2594e03c SDPP	22	#define ZYNQ_I2C_BASEADDR0 0xFF020000
	23	#define ZYNQ_I2C_BASEADDR1 0xFF030000
	24
84c7204b MS	25	#define ZYNQ_SDHCI_BASEADDR0 0xFF160000
	26	#define ZYNQ_SDHCI_BASEADDR1 0xFF170000
	27
6fe6f135 MS	28	#define ZYNQMP_SATA_BASEADDR 0xFD0C0000
6fe6f135 MS	29
84c7204b MS	30	#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
	31	#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
	32
	33	struct crlapb_regs {
5cb24200 MS	34	u32 reserved0[36];
	35	u32 cpu_r5_ctrl; /* 0x90 */
	36	u32 reserved1[37];
84c7204b	37	u32 timestamp_ref_ctrl; /* 0x128 */
5cb24200	38	u32 reserved2[53];
84c7204b	39	u32 boot_mode; /* 0x200 */
5cb24200 MS	40	u32 reserved3[14];
	41	u32 rst_lpd_top; /* 0x23C */
	42	u32 reserved4[26];
84c7204b MS	43	};
	44
	45	#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
	46
cb526c1c MS	47	#if defined(CONFIG_SECURE_IOU)
	48	#define ZYNQMP_IOU_SCNTR 0xFF260000
	49	#else
84c7204b	50	#define ZYNQMP_IOU_SCNTR 0xFF250000
cb526c1c	51	#endif
84c7204b MS	52	#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
	53	#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
	54
	55	struct iou_scntr {
	56	u32 counter_control_register;
	57	u32 reserved0[7];
	58	u32 base_frequency_id_register;
	59	};
	60
	61	#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
	62
	63	/* Bootmode setting values */
	64	#define BOOT_MODES_MASK 0x0000000F
39c56f55 MS	65	#define SD_MODE 0x00000003
39c56f55 MS	66	#define EMMC_MODE 0x00000006
84c7204b MS	67	#define JTAG_MODE 0x00000000
84c7204b MS	68
225bf9aa MS	69	#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
	70
	71	struct iou_slcr_regs {
	72	u32 mio_pin[78];
	73	u32 reserved[442];
	74	};
	75
	76	#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
	77
5cb24200 MS	78	#define ZYNQMP_RPU_BASEADDR 0xFF9A0000
	79
	80	struct rpu_regs {
	81	u32 rpu_glbl_ctrl;
	82	u32 reserved0[63];
	83	u32 rpu0_cfg; /* 0x100 */
	84	u32 reserved1[63];
	85	u32 rpu1_cfg; /* 0x200 */
	86	};
	87
	88	#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
	89
	90	#define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
	91
	92	struct crfapb_regs {
	93	u32 reserved0[65];
	94	u32 rst_fpd_apu; /* 0x104 */
	95	u32 reserved1;
	96	};
	97
	98	#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
	99
	100	#define ZYNQMP_APU_BASEADDR 0xFD5C0000
	101
	102	struct apu_regs {
	103	u32 reserved0[16];
	104	u32 rvbar_addr0_l; /* 0x40 */
	105	u32 rvbar_addr0_h; /* 0x44 */
	106	u32 reserved1[20];
	107	};
	108
	109	#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
	110
84c7204b MS	111	/* Board version value */
	112	#define ZYNQMP_CSU_VERSION_SILICON 0x0
	113	#define ZYNQMP_CSU_VERSION_EP108 0x1
16247d28	114	#define ZYNQMP_CSU_VERSION_VELOCE 0x2
84c7204b MS	115	#define ZYNQMP_CSU_VERSION_QEMU 0x3
	116
	117	#endif /* _ASM_ARCH_HARDWARE_H */