[people/ms/linux.git] / arch / arm / include / asm / atomic.h

/*
 *  arch/arm/include/asm/atomic.h
 *
 *  Copyright (C) 1996 Russell King.
 *  Copyright (C) 2002 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __ASM_ARM_ATOMIC_H
#define __ASM_ARM_ATOMIC_H

#include <linux/compiler.h>
#include <linux/types.h>
#include <asm/system.h>

#define ATOMIC_INIT(i)	{ (i) }

#ifdef __KERNEL__

/*
 * On ARM, ordinary assignment (str instruction) doesn't clear the local
 * strex/ldrex monitor on some implementations. The reason we can use it for
 * atomic_set() is the clrex or dummy strex done on every exception return.
 */
#define atomic_read(v)	(*(volatile int *)&(v)->counter)
#define atomic_set(v,i)	(((v)->counter) = (i))

#if __LINUX_ARM_ARCH__ >= 6

/*
 * ARMv6 UP and SMP safe atomic ops.  We use load exclusive and
 * store exclusive to ensure that these are atomic.  We may loop
 * to ensure that the update happens.
 */
static inline void atomic_add(int i, atomic_t *v)
{
	unsigned long tmp;
	int result;

	__asm__ __volatile__("@ atomic_add\n"
"1:	ldrex	%0, [%3]\n"
"	add	%0, %0, %4\n"
"	strex	%1, %0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "Ir" (i)
	: "cc");
}

static inline int atomic_add_return(int i, atomic_t *v)
{
	unsigned long tmp;
	int result;

	smp_mb();

	__asm__ __volatile__("@ atomic_add_return\n"
"1:	ldrex	%0, [%3]\n"
"	add	%0, %0, %4\n"
"	strex	%1, %0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "Ir" (i)
	: "cc");

	smp_mb();

	return result;
}

static inline void atomic_sub(int i, atomic_t *v)
{
	unsigned long tmp;
	int result;

	__asm__ __volatile__("@ atomic_sub\n"
"1:	ldrex	%0, [%3]\n"
"	sub	%0, %0, %4\n"
"	strex	%1, %0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "Ir" (i)
	: "cc");
}

static inline int atomic_sub_return(int i, atomic_t *v)
{
	unsigned long tmp;
	int result;

	smp_mb();

	__asm__ __volatile__("@ atomic_sub_return\n"
"1:	ldrex	%0, [%3]\n"
"	sub	%0, %0, %4\n"
"	strex	%1, %0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "Ir" (i)
	: "cc");

	smp_mb();

	return result;
}

static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
{
	unsigned long oldval, res;

	smp_mb();

	do {
		__asm__ __volatile__("@ atomic_cmpxchg\n"
		"ldrex	%1, [%3]\n"
		"mov	%0, #0\n"
		"teq	%1, %4\n"
		"strexeq %0, %5, [%3]\n"
		    : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
		    : "r" (&ptr->counter), "Ir" (old), "r" (new)
		    : "cc");
	} while (res);

	smp_mb();

	return oldval;
}

static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
{
	unsigned long tmp, tmp2;

	__asm__ __volatile__("@ atomic_clear_mask\n"
"1:	ldrex	%0, [%3]\n"
"	bic	%0, %0, %4\n"
"	strex	%1, %0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (tmp), "=&r" (tmp2), "+Qo" (*addr)
	: "r" (addr), "Ir" (mask)
	: "cc");
}

#else /* ARM_ARCH_6 */

#ifdef CONFIG_SMP
#error SMP not supported on pre-ARMv6 CPUs
#endif

static inline int atomic_add_return(int i, atomic_t *v)
{
	unsigned long flags;
	int val;

	raw_local_irq_save(flags);
	val = v->counter;
	v->counter = val += i;
	raw_local_irq_restore(flags);

	return val;
}
#define atomic_add(i, v)	(void) atomic_add_return(i, v)

static inline int atomic_sub_return(int i, atomic_t *v)
{
	unsigned long flags;
	int val;

	raw_local_irq_save(flags);
	val = v->counter;
	v->counter = val -= i;
	raw_local_irq_restore(flags);

	return val;
}
#define atomic_sub(i, v)	(void) atomic_sub_return(i, v)

static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
{
	int ret;
	unsigned long flags;

	raw_local_irq_save(flags);
	ret = v->counter;
	if (likely(ret == old))
		v->counter = new;
	raw_local_irq_restore(flags);

	return ret;
}

static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
{
	unsigned long flags;

	raw_local_irq_save(flags);
	*addr &= ~mask;
	raw_local_irq_restore(flags);
}

#endif /* __LINUX_ARM_ARCH__ */

#define atomic_xchg(v, new) (xchg(&((v)->counter), new))

static inline int atomic_add_unless(atomic_t *v, int a, int u)
{
	int c, old;

	c = atomic_read(v);
	while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
		c = old;
	return c != u;
}

#define atomic_inc(v)		atomic_add(1, v)
#define atomic_dec(v)		atomic_sub(1, v)

#define atomic_inc_and_test(v)	(atomic_add_return(1, v) == 0)
#define atomic_dec_and_test(v)	(atomic_sub_return(1, v) == 0)
#define atomic_inc_return(v)    (atomic_add_return(1, v))
#define atomic_dec_return(v)    (atomic_sub_return(1, v))
#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)

#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)

#define smp_mb__before_atomic_dec()	smp_mb()
#define smp_mb__after_atomic_dec()	smp_mb()
#define smp_mb__before_atomic_inc()	smp_mb()
#define smp_mb__after_atomic_inc()	smp_mb()

#ifndef CONFIG_GENERIC_ATOMIC64
typedef struct {
	u64 __aligned(8) counter;
} atomic64_t;

#define ATOMIC64_INIT(i) { (i) }

static inline u64 atomic64_read(atomic64_t *v)
{
	u64 result;

	__asm__ __volatile__("@ atomic64_read\n"
"	ldrexd	%0, %H0, [%1]"
	: "=&r" (result)
	: "r" (&v->counter), "Qo" (v->counter)
	);

	return result;
}

static inline void atomic64_set(atomic64_t *v, u64 i)
{
	u64 tmp;

	__asm__ __volatile__("@ atomic64_set\n"
"1:	ldrexd	%0, %H0, [%2]\n"
"	strexd	%0, %3, %H3, [%2]\n"
"	teq	%0, #0\n"
"	bne	1b"
	: "=&r" (tmp), "=Qo" (v->counter)
	: "r" (&v->counter), "r" (i)
	: "cc");
}

static inline void atomic64_add(u64 i, atomic64_t *v)
{
	u64 result;
	unsigned long tmp;

	__asm__ __volatile__("@ atomic64_add\n"
"1:	ldrexd	%0, %H0, [%3]\n"
"	adds	%0, %0, %4\n"
"	adc	%H0, %H0, %H4\n"
"	strexd	%1, %0, %H0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "r" (i)
	: "cc");
}

static inline u64 atomic64_add_return(u64 i, atomic64_t *v)
{
	u64 result;
	unsigned long tmp;

	smp_mb();

	__asm__ __volatile__("@ atomic64_add_return\n"
"1:	ldrexd	%0, %H0, [%3]\n"
"	adds	%0, %0, %4\n"
"	adc	%H0, %H0, %H4\n"
"	strexd	%1, %0, %H0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "r" (i)
	: "cc");

	smp_mb();

	return result;
}

static inline void atomic64_sub(u64 i, atomic64_t *v)
{
	u64 result;
	unsigned long tmp;

	__asm__ __volatile__("@ atomic64_sub\n"
"1:	ldrexd	%0, %H0, [%3]\n"
"	subs	%0, %0, %4\n"
"	sbc	%H0, %H0, %H4\n"
"	strexd	%1, %0, %H0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "r" (i)
	: "cc");
}

static inline u64 atomic64_sub_return(u64 i, atomic64_t *v)
{
	u64 result;
	unsigned long tmp;

	smp_mb();

	__asm__ __volatile__("@ atomic64_sub_return\n"
"1:	ldrexd	%0, %H0, [%3]\n"
"	subs	%0, %0, %4\n"
"	sbc	%H0, %H0, %H4\n"
"	strexd	%1, %0, %H0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "r" (i)
	: "cc");

	smp_mb();

	return result;
}

static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new)
{
	u64 oldval;
	unsigned long res;

	smp_mb();

	do {
		__asm__ __volatile__("@ atomic64_cmpxchg\n"
		"ldrexd		%1, %H1, [%3]\n"
		"mov		%0, #0\n"
		"teq		%1, %4\n"
		"teqeq		%H1, %H4\n"
		"strexdeq	%0, %5, %H5, [%3]"
		: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
		: "r" (&ptr->counter), "r" (old), "r" (new)
		: "cc");
	} while (res);

	smp_mb();

	return oldval;
}

static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new)
{
	u64 result;
	unsigned long tmp;

	smp_mb();

	__asm__ __volatile__("@ atomic64_xchg\n"
"1:	ldrexd	%0, %H0, [%3]\n"
"	strexd	%1, %4, %H4, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
	: "r" (&ptr->counter), "r" (new)
	: "cc");

	smp_mb();

	return result;
}

static inline u64 atomic64_dec_if_positive(atomic64_t *v)
{
	u64 result;
	unsigned long tmp;

	smp_mb();

	__asm__ __volatile__("@ atomic64_dec_if_positive\n"
"1:	ldrexd	%0, %H0, [%3]\n"
"	subs	%0, %0, #1\n"
"	sbc	%H0, %H0, #0\n"
"	teq	%H0, #0\n"
"	bmi	2f\n"
"	strexd	%1, %0, %H0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b\n"
"2:"
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter)
	: "cc");

	smp_mb();

	return result;
}

static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
{
	u64 val;
	unsigned long tmp;
	int ret = 1;

	smp_mb();

	__asm__ __volatile__("@ atomic64_add_unless\n"
"1:	ldrexd	%0, %H0, [%4]\n"
"	teq	%0, %5\n"
"	teqeq	%H0, %H5\n"
"	moveq	%1, #0\n"
"	beq	2f\n"
"	adds	%0, %0, %6\n"
"	adc	%H0, %H0, %H6\n"
"	strexd	%2, %0, %H0, [%4]\n"
"	teq	%2, #0\n"
"	bne	1b\n"
"2:"
	: "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "r" (u), "r" (a)
	: "cc");

	if (ret)
		smp_mb();

	return ret;
}

#define atomic64_add_negative(a, v)	(atomic64_add_return((a), (v)) < 0)
#define atomic64_inc(v)			atomic64_add(1LL, (v))
#define atomic64_inc_return(v)		atomic64_add_return(1LL, (v))
#define atomic64_inc_and_test(v)	(atomic64_inc_return(v) == 0)
#define atomic64_sub_and_test(a, v)	(atomic64_sub_return((a), (v)) == 0)
#define atomic64_dec(v)			atomic64_sub(1LL, (v))
#define atomic64_dec_return(v)		atomic64_sub_return(1LL, (v))
#define atomic64_dec_and_test(v)	(atomic64_dec_return((v)) == 0)
#define atomic64_inc_not_zero(v)	atomic64_add_unless((v), 1LL, 0LL)

#else /* !CONFIG_GENERIC_ATOMIC64 */
#include <asm-generic/atomic64.h>
#endif
#include <asm-generic/atomic-long.h>
#endif
#endif
Commit	Line	Data
1da177e4	1	/*
4baa9922	2	* arch/arm/include/asm/atomic.h
1da177e4 LT	3	*
	4	* Copyright (C) 1996 Russell King.
	5	* Copyright (C) 2002 Deep Blue Solutions Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#ifndef __ASM_ARM_ATOMIC_H
	12	#define __ASM_ARM_ATOMIC_H
	13
8dc39b88	14	#include <linux/compiler.h>
ea435467	15	#include <linux/types.h>
2856f5e3	16	#include <asm/system.h>
1da177e4	17
1da177e4 LT	18	#define ATOMIC_INIT(i) { (i) }
	19
	20	#ifdef __KERNEL__
	21
200b812d CM	22	/*
	23	* On ARM, ordinary assignment (str instruction) doesn't clear the local
	24	* strex/ldrex monitor on some implementations. The reason we can use it for
	25	* atomic_set() is the clrex or dummy strex done on every exception return.
	26	*/
f3d46f9d	27	#define atomic_read(v) ((volatile int )&(v)->counter)
200b812d	28	#define atomic_set(v,i) (((v)->counter) = (i))
1da177e4 LT	29
	30	#if __LINUX_ARM_ARCH__ >= 6
	31
	32	/*
	33	* ARMv6 UP and SMP safe atomic ops. We use load exclusive and
	34	* store exclusive to ensure that these are atomic. We may loop
200b812d	35	* to ensure that the update happens.
1da177e4	36	*/
bac4e960 RK	37	static inline void atomic_add(int i, atomic_t *v)
	38	{
	39	unsigned long tmp;
	40	int result;
	41
	42	__asm__ __volatile__("@ atomic_add\n"
398aa668 WD	43	"1: ldrex %0, [%3]\n"
	44	" add %0, %0, %4\n"
	45	" strex %1, %0, [%3]\n"
bac4e960 RK	46	" teq %1, #0\n"
bac4e960 RK	47	" bne 1b"
398aa668	48	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
bac4e960 RK	49	: "r" (&v->counter), "Ir" (i)
	50	: "cc");
	51	}
	52
1da177e4 LT	53	static inline int atomic_add_return(int i, atomic_t *v)
	54	{
	55	unsigned long tmp;
	56	int result;
	57
bac4e960 RK	58	smp_mb();
bac4e960 RK	59
1da177e4	60	__asm__ __volatile__("@ atomic_add_return\n"
398aa668 WD	61	"1: ldrex %0, [%3]\n"
	62	" add %0, %0, %4\n"
	63	" strex %1, %0, [%3]\n"
1da177e4 LT	64	" teq %1, #0\n"
1da177e4 LT	65	" bne 1b"
398aa668	66	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
1da177e4 LT	67	: "r" (&v->counter), "Ir" (i)
	68	: "cc");
	69
bac4e960 RK	70	smp_mb();
bac4e960 RK	71
1da177e4 LT	72	return result;
	73	}
	74
bac4e960 RK	75	static inline void atomic_sub(int i, atomic_t *v)
	76	{
	77	unsigned long tmp;
	78	int result;
	79
	80	__asm__ __volatile__("@ atomic_sub\n"
398aa668 WD	81	"1: ldrex %0, [%3]\n"
	82	" sub %0, %0, %4\n"
	83	" strex %1, %0, [%3]\n"
bac4e960 RK	84	" teq %1, #0\n"
bac4e960 RK	85	" bne 1b"
398aa668	86	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
bac4e960 RK	87	: "r" (&v->counter), "Ir" (i)
	88	: "cc");
	89	}
	90
1da177e4 LT	91	static inline int atomic_sub_return(int i, atomic_t *v)
	92	{
	93	unsigned long tmp;
	94	int result;
	95
bac4e960 RK	96	smp_mb();
bac4e960 RK	97
1da177e4	98	__asm__ __volatile__("@ atomic_sub_return\n"
398aa668 WD	99	"1: ldrex %0, [%3]\n"
	100	" sub %0, %0, %4\n"
	101	" strex %1, %0, [%3]\n"
1da177e4 LT	102	" teq %1, #0\n"
1da177e4 LT	103	" bne 1b"
398aa668	104	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
1da177e4 LT	105	: "r" (&v->counter), "Ir" (i)
	106	: "cc");
	107
bac4e960 RK	108	smp_mb();
bac4e960 RK	109
1da177e4 LT	110	return result;
	111	}
	112
4a6dae6d NP	113	static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
4a6dae6d NP	114	{
49ee57a3	115	unsigned long oldval, res;
4a6dae6d	116
bac4e960 RK	117	smp_mb();
bac4e960 RK	118
4a6dae6d NP	119	do {
4a6dae6d NP	120	__asm__ __volatile__("@ atomic_cmpxchg\n"
398aa668	121	"ldrex %1, [%3]\n"
a7d06833	122	"mov %0, #0\n"
398aa668 WD	123	"teq %1, %4\n"
	124	"strexeq %0, %5, [%3]\n"
	125	: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
4a6dae6d NP	126	: "r" (&ptr->counter), "Ir" (old), "r" (new)
	127	: "cc");
	128	} while (res);
	129
bac4e960 RK	130	smp_mb();
bac4e960 RK	131
4a6dae6d NP	132	return oldval;
	133	}
	134
1da177e4 LT	135	static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
	136	{
	137	unsigned long tmp, tmp2;
	138
	139	__asm__ __volatile__("@ atomic_clear_mask\n"
398aa668 WD	140	"1: ldrex %0, [%3]\n"
	141	" bic %0, %0, %4\n"
	142	" strex %1, %0, [%3]\n"
1da177e4 LT	143	" teq %1, #0\n"
1da177e4 LT	144	" bne 1b"
398aa668	145	: "=&r" (tmp), "=&r" (tmp2), "+Qo" (*addr)
1da177e4 LT	146	: "r" (addr), "Ir" (mask)
	147	: "cc");
	148	}
	149
	150	#else /* ARM_ARCH_6 */
	151
1da177e4 LT	152	#ifdef CONFIG_SMP
	153	#error SMP not supported on pre-ARMv6 CPUs
	154	#endif
	155
1da177e4 LT	156	static inline int atomic_add_return(int i, atomic_t *v)
	157	{
	158	unsigned long flags;
	159	int val;
	160
8dd5c845	161	raw_local_irq_save(flags);
1da177e4 LT	162	val = v->counter;
1da177e4 LT	163	v->counter = val += i;
8dd5c845	164	raw_local_irq_restore(flags);
1da177e4 LT	165
	166	return val;
	167	}
bac4e960	168	#define atomic_add(i, v) (void) atomic_add_return(i, v)
1da177e4 LT	169
	170	static inline int atomic_sub_return(int i, atomic_t *v)
	171	{
	172	unsigned long flags;
	173	int val;
	174
8dd5c845	175	raw_local_irq_save(flags);
1da177e4 LT	176	val = v->counter;
1da177e4 LT	177	v->counter = val -= i;
8dd5c845	178	raw_local_irq_restore(flags);
1da177e4 LT	179
	180	return val;
	181	}
bac4e960	182	#define atomic_sub(i, v) (void) atomic_sub_return(i, v)
1da177e4	183
4a6dae6d NP	184	static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
	185	{
	186	int ret;
	187	unsigned long flags;
	188
8dd5c845	189	raw_local_irq_save(flags);
4a6dae6d NP	190	ret = v->counter;
	191	if (likely(ret == old))
	192	v->counter = new;
8dd5c845	193	raw_local_irq_restore(flags);
4a6dae6d NP	194
	195	return ret;
	196	}
	197
1da177e4 LT	198	static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
	199	{
	200	unsigned long flags;
	201
8dd5c845	202	raw_local_irq_save(flags);
1da177e4	203	*addr &= ~mask;
8dd5c845	204	raw_local_irq_restore(flags);
1da177e4 LT	205	}
	206
	207	#endif /* __LINUX_ARM_ARCH__ */
	208
ffbf670f IM	209	#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
ffbf670f IM	210
8426e1f6 NP	211	static inline int atomic_add_unless(atomic_t *v, int a, int u)
	212	{
	213	int c, old;
	214
	215	c = atomic_read(v);
	216	while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
	217	c = old;
	218	return c != u;
	219	}
8426e1f6	220
bac4e960 RK	221	#define atomic_inc(v) atomic_add(1, v)
bac4e960 RK	222	#define atomic_dec(v) atomic_sub(1, v)
1da177e4 LT	223
	224	#define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
	225	#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
	226	#define atomic_inc_return(v) (atomic_add_return(1, v))
	227	#define atomic_dec_return(v) (atomic_sub_return(1, v))
	228	#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
	229
	230	#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
	231
bac4e960 RK	232	#define smp_mb__before_atomic_dec() smp_mb()
	233	#define smp_mb__after_atomic_dec() smp_mb()
	234	#define smp_mb__before_atomic_inc() smp_mb()
	235	#define smp_mb__after_atomic_inc() smp_mb()
1da177e4	236
24b44a66 WD	237	#ifndef CONFIG_GENERIC_ATOMIC64
	238	typedef struct {
	239	u64 __aligned(8) counter;
	240	} atomic64_t;
	241
	242	#define ATOMIC64_INIT(i) { (i) }
	243
	244	static inline u64 atomic64_read(atomic64_t *v)
	245	{
	246	u64 result;
	247
	248	__asm__ __volatile__("@ atomic64_read\n"
	249	" ldrexd %0, %H0, [%1]"
	250	: "=&r" (result)
398aa668	251	: "r" (&v->counter), "Qo" (v->counter)
24b44a66 WD	252	);
	253
	254	return result;
	255	}
	256
	257	static inline void atomic64_set(atomic64_t *v, u64 i)
	258	{
	259	u64 tmp;
	260
	261	__asm__ __volatile__("@ atomic64_set\n"
398aa668 WD	262	"1: ldrexd %0, %H0, [%2]\n"
398aa668 WD	263	" strexd %0, %3, %H3, [%2]\n"
24b44a66 WD	264	" teq %0, #0\n"
24b44a66 WD	265	" bne 1b"
398aa668	266	: "=&r" (tmp), "=Qo" (v->counter)
24b44a66 WD	267	: "r" (&v->counter), "r" (i)
	268	: "cc");
	269	}
	270
	271	static inline void atomic64_add(u64 i, atomic64_t *v)
	272	{
	273	u64 result;
	274	unsigned long tmp;
	275
	276	__asm__ __volatile__("@ atomic64_add\n"
398aa668 WD	277	"1: ldrexd %0, %H0, [%3]\n"
	278	" adds %0, %0, %4\n"
	279	" adc %H0, %H0, %H4\n"
	280	" strexd %1, %0, %H0, [%3]\n"
24b44a66 WD	281	" teq %1, #0\n"
24b44a66 WD	282	" bne 1b"
398aa668	283	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
24b44a66 WD	284	: "r" (&v->counter), "r" (i)
	285	: "cc");
	286	}
	287
	288	static inline u64 atomic64_add_return(u64 i, atomic64_t *v)
	289	{
	290	u64 result;
	291	unsigned long tmp;
	292
	293	smp_mb();
	294
	295	__asm__ __volatile__("@ atomic64_add_return\n"
398aa668 WD	296	"1: ldrexd %0, %H0, [%3]\n"
	297	" adds %0, %0, %4\n"
	298	" adc %H0, %H0, %H4\n"
	299	" strexd %1, %0, %H0, [%3]\n"
24b44a66 WD	300	" teq %1, #0\n"
24b44a66 WD	301	" bne 1b"
398aa668	302	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
24b44a66 WD	303	: "r" (&v->counter), "r" (i)
	304	: "cc");
	305
	306	smp_mb();
	307
	308	return result;
	309	}
	310
	311	static inline void atomic64_sub(u64 i, atomic64_t *v)
	312	{
	313	u64 result;
	314	unsigned long tmp;
	315
	316	__asm__ __volatile__("@ atomic64_sub\n"
398aa668 WD	317	"1: ldrexd %0, %H0, [%3]\n"
	318	" subs %0, %0, %4\n"
	319	" sbc %H0, %H0, %H4\n"
	320	" strexd %1, %0, %H0, [%3]\n"
24b44a66 WD	321	" teq %1, #0\n"
24b44a66 WD	322	" bne 1b"
398aa668	323	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
24b44a66 WD	324	: "r" (&v->counter), "r" (i)
	325	: "cc");
	326	}
	327
	328	static inline u64 atomic64_sub_return(u64 i, atomic64_t *v)
	329	{
	330	u64 result;
	331	unsigned long tmp;
	332
	333	smp_mb();
	334
	335	__asm__ __volatile__("@ atomic64_sub_return\n"
398aa668 WD	336	"1: ldrexd %0, %H0, [%3]\n"
	337	" subs %0, %0, %4\n"
	338	" sbc %H0, %H0, %H4\n"
	339	" strexd %1, %0, %H0, [%3]\n"
24b44a66 WD	340	" teq %1, #0\n"
24b44a66 WD	341	" bne 1b"
398aa668	342	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
24b44a66 WD	343	: "r" (&v->counter), "r" (i)
	344	: "cc");
	345
	346	smp_mb();
	347
	348	return result;
	349	}
	350
	351	static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new)
	352	{
	353	u64 oldval;
	354	unsigned long res;
	355
	356	smp_mb();
	357
	358	do {
	359	__asm__ __volatile__("@ atomic64_cmpxchg\n"
398aa668	360	"ldrexd %1, %H1, [%3]\n"
24b44a66	361	"mov %0, #0\n"
398aa668 WD	362	"teq %1, %4\n"
	363	"teqeq %H1, %H4\n"
	364	"strexdeq %0, %5, %H5, [%3]"
	365	: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
24b44a66 WD	366	: "r" (&ptr->counter), "r" (old), "r" (new)
	367	: "cc");
	368	} while (res);
	369
	370	smp_mb();
	371
	372	return oldval;
	373	}
	374
	375	static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new)
	376	{
	377	u64 result;
	378	unsigned long tmp;
	379
	380	smp_mb();
	381
	382	__asm__ __volatile__("@ atomic64_xchg\n"
398aa668 WD	383	"1: ldrexd %0, %H0, [%3]\n"
398aa668 WD	384	" strexd %1, %4, %H4, [%3]\n"
24b44a66 WD	385	" teq %1, #0\n"
24b44a66 WD	386	" bne 1b"
398aa668	387	: "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
24b44a66 WD	388	: "r" (&ptr->counter), "r" (new)
	389	: "cc");
	390
	391	smp_mb();
	392
	393	return result;
	394	}
	395
	396	static inline u64 atomic64_dec_if_positive(atomic64_t *v)
	397	{
	398	u64 result;
	399	unsigned long tmp;
	400
	401	smp_mb();
	402
	403	__asm__ __volatile__("@ atomic64_dec_if_positive\n"
398aa668	404	"1: ldrexd %0, %H0, [%3]\n"
24b44a66 WD	405	" subs %0, %0, #1\n"
	406	" sbc %H0, %H0, #0\n"
	407	" teq %H0, #0\n"
	408	" bmi 2f\n"
398aa668	409	" strexd %1, %0, %H0, [%3]\n"
24b44a66 WD	410	" teq %1, #0\n"
	411	" bne 1b\n"
	412	"2:"
398aa668	413	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
24b44a66 WD	414	: "r" (&v->counter)
	415	: "cc");
	416
	417	smp_mb();
	418
	419	return result;
	420	}
	421
	422	static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
	423	{
	424	u64 val;
	425	unsigned long tmp;
	426	int ret = 1;
	427
	428	smp_mb();
	429
	430	__asm__ __volatile__("@ atomic64_add_unless\n"
398aa668 WD	431	"1: ldrexd %0, %H0, [%4]\n"
	432	" teq %0, %5\n"
	433	" teqeq %H0, %H5\n"
24b44a66 WD	434	" moveq %1, #0\n"
24b44a66 WD	435	" beq 2f\n"
398aa668 WD	436	" adds %0, %0, %6\n"
	437	" adc %H0, %H0, %H6\n"
	438	" strexd %2, %0, %H0, [%4]\n"
24b44a66 WD	439	" teq %2, #0\n"
	440	" bne 1b\n"
	441	"2:"
398aa668	442	: "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)
24b44a66 WD	443	: "r" (&v->counter), "r" (u), "r" (a)
	444	: "cc");
	445
	446	if (ret)
	447	smp_mb();
	448
	449	return ret;
	450	}
	451
	452	#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
	453	#define atomic64_inc(v) atomic64_add(1LL, (v))
	454	#define atomic64_inc_return(v) atomic64_add_return(1LL, (v))
	455	#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
	456	#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
	457	#define atomic64_dec(v) atomic64_sub(1LL, (v))
	458	#define atomic64_dec_return(v) atomic64_sub_return(1LL, (v))
	459	#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
	460	#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
	461
	462	#else /* !CONFIG_GENERIC_ATOMIC64 */
	463	#include <asm-generic/atomic64.h>
	464	#endif
72099ed2	465	#include <asm-generic/atomic-long.h>
1da177e4 LT	466	#endif
1da177e4 LT	467	#endif