[people/ms/u-boot.git] / arch / arm / include / asm / fsl_secure_boot.h

/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __FSL_SECURE_BOOT_H
#define __FSL_SECURE_BOOT_H

#ifdef CONFIG_SECURE_BOOT

#ifndef CONFIG_FIT_SIGNATURE
#define CONFIG_CHAIN_OF_TRUST
#endif

#endif

#ifdef CONFIG_CHAIN_OF_TRUST
#define CONFIG_CMD_ESBC_VALIDATE
#define CONFIG_CMD_BLOB
#define CONFIG_CMD_HASH
#define CONFIG_FSL_SEC_MON
#define CONFIG_SHA_HW_ACCEL
#define CONFIG_SHA_PROG_HW_ACCEL
#define CONFIG_RSA_FREESCALE_EXP

#ifndef CONFIG_FSL_CAAM
#define CONFIG_FSL_CAAM
#endif

#define CONFIG_KEY_REVOCATION
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
 * is picked up from an Extension Table which has
 * been verified by the ISBC (Internal Secure boot Code)
 * in boot ROM of the SoC.
 * The feature is only applicable in case of NOR boot and is
 * not applicable in case of RAMBOOT (NAND, SD, SPI).
 */
#ifndef CONFIG_ESBC_HDR_LS
/* Current Key EXT feature not available in LS ESBC Header */
#define CONFIG_FSL_ISBC_KEY_EXT
#endif

#endif

#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A)
/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
 * Similiarly for LS2080
 */
#define CONFIG_ESBC_ADDR_64BIT
#endif

#ifdef CONFIG_LS2080A
#define CONFIG_EXTRA_ENV \
	"setenv fdt_high 0xa0000000;"	\
	"setenv initrd_high 0xcfffffff;"	\
	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
#else
#define CONFIG_EXTRA_ENV \
	"setenv fdt_high 0xcfffffff;"	\
	"setenv initrd_high 0xcfffffff;"	\
	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
#endif

/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
 * Non-XIP Memory (Nand/SD)*/
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A)
#define CONFIG_BOOTSCRIPT_COPY_RAM
#endif
/* The address needs to be modified according to NOR and DDR memory map */
#ifdef CONFIG_LS2080A
#define CONFIG_BS_HDR_ADDR_FLASH	0x583920000
#define CONFIG_BS_ADDR_FLASH		0x583900000
#define CONFIG_BS_HDR_ADDR_RAM		0xa3920000
#define CONFIG_BS_ADDR_RAM		0xa3900000
#else
#define CONFIG_BS_HDR_ADDR_FLASH	0x600a0000
#define CONFIG_BS_ADDR_FLASH		0x60060000
#define CONFIG_BS_HDR_ADDR_RAM		0xa0060000
#define CONFIG_BS_ADDR_RAM		0xa0060000
#endif

#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
#define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
#define CONFIG_BS_HDR_SIZE		0x00002000
#define CONFIG_BOOTSCRIPT_ADDR		CONFIG_BS_ADDR_RAM
#define CONFIG_BS_SIZE			0x00001000
#else
#define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_FLASH
/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */
#endif

#include <config_fsl_chain_trust.h>
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
#endif
Commit	Line	Data
98cb0efd	1	/*
	2	* Copyright 2015 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __FSL_SECURE_BOOT_H
	8	#define __FSL_SECURE_BOOT_H
	9
	10	#ifdef CONFIG_SECURE_BOOT
bdc22074 AB	11
	12	#ifndef CONFIG_FIT_SIGNATURE
	13	#define CONFIG_CHAIN_OF_TRUST
	14	#endif
	15
	16	#endif
	17
	18	#ifdef CONFIG_CHAIN_OF_TRUST
2ed948f4	19	#define CONFIG_CMD_ESBC_VALIDATE
74eecd82	20	#define CONFIG_CMD_BLOB
fcfdb6d5	21	#define CONFIG_CMD_HASH
2ed948f4	22	#define CONFIG_FSL_SEC_MON
fcfdb6d5	23	#define CONFIG_SHA_HW_ACCEL
2ed948f4	24	#define CONFIG_SHA_PROG_HW_ACCEL
2ed948f4	25	#define CONFIG_RSA_FREESCALE_EXP
9711f528	26
2ed948f4 AB	27	#ifndef CONFIG_FSL_CAAM
	28	#define CONFIG_FSL_CAAM
	29	#endif
	30
	31	#define CONFIG_KEY_REVOCATION
	32	#ifndef CONFIG_SYS_RAMBOOT
	33	/* The key used for verification of next level images
	34	* is picked up from an Extension Table which has
	35	* been verified by the ISBC (Internal Secure boot Code)
	36	* in boot ROM of the SoC.
	37	* The feature is only applicable in case of NOR boot and is
	38	* not applicable in case of RAMBOOT (NAND, SD, SPI).
	39	*/
fd6dbc98 SJ	40	#ifndef CONFIG_ESBC_HDR_LS
fd6dbc98 SJ	41	/* Current Key EXT feature not available in LS ESBC Header */
2ed948f4 AB	42	#define CONFIG_FSL_ISBC_KEY_EXT
	43	#endif
	44
fd6dbc98 SJ	45	#endif
fd6dbc98 SJ	46
3c1d218a	47	#if defined(CONFIG_LS1043A) \|\| defined(CONFIG_LS2080A)
fcfdb6d5	48	/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit
3c1d218a	49	* Similiarly for LS2080
fcfdb6d5	50	*/
ef6c55a2 AB	51	#define CONFIG_ESBC_ADDR_64BIT
	52	#endif
	53
3c1d218a	54	#ifdef CONFIG_LS2080A
bef238cb SJ	55	#define CONFIG_EXTRA_ENV \
	56	"setenv fdt_high 0xa0000000;" \
	57	"setenv initrd_high 0xcfffffff;" \
	58	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
	59	#else
98cb0efd	60	#define CONFIG_EXTRA_ENV \
	61	"setenv fdt_high 0xcfffffff;" \
	62	"setenv initrd_high 0xcfffffff;" \
	63	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
bef238cb	64	#endif
98cb0efd	65
3f701cc5 SJ	66	/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
3f701cc5 SJ	67	* Non-XIP Memory (Nand/SD)*/
3c1d218a	68	#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_LS2080A)
3f701cc5 SJ	69	#define CONFIG_BOOTSCRIPT_COPY_RAM
	70	#endif
	71	/* The address needs to be modified according to NOR and DDR memory map */
3c1d218a	72	#ifdef CONFIG_LS2080A
3f701cc5 SJ	73	#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000
	74	#define CONFIG_BS_ADDR_FLASH 0x583900000
	75	#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
	76	#define CONFIG_BS_ADDR_RAM 0xa3900000
	77	#else
	78	#define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000
	79	#define CONFIG_BS_ADDR_FLASH 0x60060000
	80	#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000
	81	#define CONFIG_BS_ADDR_RAM 0xa0060000
	82	#endif
	83
	84	#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
	85	#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
	86	#define CONFIG_BS_HDR_SIZE 0x00002000
	87	#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
	88	#define CONFIG_BS_SIZE 0x00001000
216e93a1	89	#else
3f701cc5 SJ	90	#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH
3f701cc5 SJ	91	/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */
216e93a1	92	#endif
98cb0efd	93
bdc22074 AB	94	#include <config_fsl_chain_trust.h>
bdc22074 AB	95	#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
98cb0efd	96	#endif