[thirdparty/u-boot.git] / arch / arm / include / asm / imx-common / dma.h

/*
 * Freescale i.MX28 APBH DMA
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * Based on code from LTIB:
 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __DMA_H__
#define __DMA_H__

#include <linux/list.h>
#include <linux/compiler.h>

#ifndef	CONFIG_ARCH_DMA_PIO_WORDS
#define	DMA_PIO_WORDS		15
#else
#define	DMA_PIO_WORDS		CONFIG_ARCH_DMA_PIO_WORDS
#endif

#define MXS_DMA_ALIGNMENT	32

/*
 * MXS DMA channels
 */
#if defined(CONFIG_MX23)
enum {
	MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
	MXS_DMA_CHANNEL_AHB_APBH_SSP0,
	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
	MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
	MXS_MAX_DMA_CHANNELS,
};
#elif defined(CONFIG_MX28)
enum {
	MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
	MXS_DMA_CHANNEL_AHB_APBH_SSP2,
	MXS_DMA_CHANNEL_AHB_APBH_SSP3,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
	MXS_DMA_CHANNEL_AHB_APBH_HSADC,
	MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
	MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
	MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
	MXS_MAX_DMA_CHANNELS,
};
#elif defined(CONFIG_MX6)
enum {
	MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
	MXS_MAX_DMA_CHANNELS,
};
#endif

/*
 * MXS DMA hardware command.
 *
 * This structure describes the in-memory layout of an entire DMA command,
 * including space for the maximum number of PIO accesses. See the appropriate
 * reference manual for a detailed description of what these fields mean to the
 * DMA hardware.
 */
#define	MXS_DMA_DESC_COMMAND_MASK	0x3
#define	MXS_DMA_DESC_COMMAND_OFFSET	0
#define	MXS_DMA_DESC_COMMAND_NO_DMAXFER	0x0
#define	MXS_DMA_DESC_COMMAND_DMA_WRITE	0x1
#define	MXS_DMA_DESC_COMMAND_DMA_READ	0x2
#define	MXS_DMA_DESC_COMMAND_DMA_SENSE	0x3
#define	MXS_DMA_DESC_CHAIN		(1 << 2)
#define	MXS_DMA_DESC_IRQ		(1 << 3)
#define	MXS_DMA_DESC_NAND_LOCK		(1 << 4)
#define	MXS_DMA_DESC_NAND_WAIT_4_READY	(1 << 5)
#define	MXS_DMA_DESC_DEC_SEM		(1 << 6)
#define	MXS_DMA_DESC_WAIT4END		(1 << 7)
#define	MXS_DMA_DESC_HALT_ON_TERMINATE	(1 << 8)
#define	MXS_DMA_DESC_TERMINATE_FLUSH	(1 << 9)
#define	MXS_DMA_DESC_PIO_WORDS_MASK	(0xf << 12)
#define	MXS_DMA_DESC_PIO_WORDS_OFFSET	12
#define	MXS_DMA_DESC_BYTES_MASK		(0xffff << 16)
#define	MXS_DMA_DESC_BYTES_OFFSET	16

struct mxs_dma_cmd {
	unsigned long		next;
	unsigned long		data;
	union {
		dma_addr_t	address;
		unsigned long	alternate;
	};
	unsigned long		pio_words[DMA_PIO_WORDS];
};

/*
 * MXS DMA command descriptor.
 *
 * This structure incorporates an MXS DMA hardware command structure, along
 * with metadata.
 */
#define	MXS_DMA_DESC_FIRST	(1 << 0)
#define	MXS_DMA_DESC_LAST	(1 << 1)
#define	MXS_DMA_DESC_READY	(1 << 31)

struct mxs_dma_desc {
	struct mxs_dma_cmd	cmd;
	unsigned int		flags;
	dma_addr_t		address;
	void			*buffer;
	struct list_head	node;
} __aligned(MXS_DMA_ALIGNMENT);

/**
 * MXS DMA channel
 *
 * This structure represents a single DMA channel. The MXS platform code
 * maintains an array of these structures to represent every DMA channel in the
 * system (see mxs_dma_channels).
 */
#define	MXS_DMA_FLAGS_IDLE	0
#define	MXS_DMA_FLAGS_BUSY	(1 << 0)
#define	MXS_DMA_FLAGS_FREE	0
#define	MXS_DMA_FLAGS_ALLOCATED	(1 << 16)
#define	MXS_DMA_FLAGS_VALID	(1 << 31)

struct mxs_dma_chan {
	const char *name;
	unsigned long dev;
	struct mxs_dma_device *dma;
	unsigned int flags;
	unsigned int active_num;
	unsigned int pending_num;
	struct list_head active;
	struct list_head done;
};

struct mxs_dma_desc *mxs_dma_desc_alloc(void);
void mxs_dma_desc_free(struct mxs_dma_desc *);
int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);

int mxs_dma_go(int chan);
void mxs_dma_init(void);
int mxs_dma_init_channel(int chan);
int mxs_dma_release(int chan);

#endif	/* __DMA_H__ */
Commit	Line	Data
31650d64 MV	1	/*
	2	* Freescale i.MX28 APBH DMA
	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
	7	* Based on code from LTIB:
	8	* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
31650d64 MV	11	*/
	12
	13	#ifndef __DMA_H__
	14	#define __DMA_H__
	15
	16	#include <linux/list.h>
615a4ad0	17	#include <linux/compiler.h>
31650d64 MV	18
	19	#ifndef CONFIG_ARCH_DMA_PIO_WORDS
	20	#define DMA_PIO_WORDS 15
	21	#else
	22	#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
	23	#endif
	24
	25	#define MXS_DMA_ALIGNMENT 32
	26
	27	/*
	28	* MXS DMA channels
	29	*/
3430e0bd MV	30	#if defined(CONFIG_MX23)
	31	enum {
	32	MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
	33	MXS_DMA_CHANNEL_AHB_APBH_SSP0,
	34	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
	35	MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
	36	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
	37	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
	38	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
	39	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
	40	MXS_MAX_DMA_CHANNELS,
	41	};
	42	#elif defined(CONFIG_MX28)
31650d64 MV	43	enum {
	44	MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
	45	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
	46	MXS_DMA_CHANNEL_AHB_APBH_SSP2,
	47	MXS_DMA_CHANNEL_AHB_APBH_SSP3,
	48	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
	49	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
	50	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
	51	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
	52	MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
	53	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
	54	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
	55	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
3430e0bd MV	56	MXS_DMA_CHANNEL_AHB_APBH_HSADC,
	57	MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
	58	MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
	59	MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
31650d64 MV	60	MXS_MAX_DMA_CHANNELS,
31650d64 MV	61	};
99193e30 SR	62	#elif defined(CONFIG_MX6)
	63	enum {
	64	MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
	65	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
	66	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
	67	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
	68	MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
	69	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
	70	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
	71	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
	72	MXS_MAX_DMA_CHANNELS,
	73	};
3430e0bd	74	#endif
31650d64 MV	75
	76	/*
	77	* MXS DMA hardware command.
	78	*
	79	* This structure describes the in-memory layout of an entire DMA command,
	80	* including space for the maximum number of PIO accesses. See the appropriate
	81	* reference manual for a detailed description of what these fields mean to the
	82	* DMA hardware.
	83	*/
	84	#define MXS_DMA_DESC_COMMAND_MASK 0x3
	85	#define MXS_DMA_DESC_COMMAND_OFFSET 0
	86	#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
	87	#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
	88	#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
	89	#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
	90	#define MXS_DMA_DESC_CHAIN (1 << 2)
	91	#define MXS_DMA_DESC_IRQ (1 << 3)
	92	#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
	93	#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
	94	#define MXS_DMA_DESC_DEC_SEM (1 << 6)
	95	#define MXS_DMA_DESC_WAIT4END (1 << 7)
	96	#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
	97	#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
	98	#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
	99	#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
	100	#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
	101	#define MXS_DMA_DESC_BYTES_OFFSET 16
	102
	103	struct mxs_dma_cmd {
	104	unsigned long next;
	105	unsigned long data;
	106	union {
	107	dma_addr_t address;
	108	unsigned long alternate;
	109	};
	110	unsigned long pio_words[DMA_PIO_WORDS];
	111	};
	112
	113	/*
	114	* MXS DMA command descriptor.
	115	*
	116	* This structure incorporates an MXS DMA hardware command structure, along
	117	* with metadata.
	118	*/
	119	#define MXS_DMA_DESC_FIRST (1 << 0)
	120	#define MXS_DMA_DESC_LAST (1 << 1)
	121	#define MXS_DMA_DESC_READY (1 << 31)
	122
	123	struct mxs_dma_desc {
	124	struct mxs_dma_cmd cmd;
	125	unsigned int flags;
	126	dma_addr_t address;
	127	void *buffer;
	128	struct list_head node;
615a4ad0	129	} __aligned(MXS_DMA_ALIGNMENT);
31650d64 MV	130
	131	/**
	132	* MXS DMA channel
	133	*
	134	* This structure represents a single DMA channel. The MXS platform code
	135	* maintains an array of these structures to represent every DMA channel in the
	136	* system (see mxs_dma_channels).
	137	*/
	138	#define MXS_DMA_FLAGS_IDLE 0
	139	#define MXS_DMA_FLAGS_BUSY (1 << 0)
	140	#define MXS_DMA_FLAGS_FREE 0
	141	#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
	142	#define MXS_DMA_FLAGS_VALID (1 << 31)
	143
	144	struct mxs_dma_chan {
	145	const char *name;
	146	unsigned long dev;
	147	struct mxs_dma_device *dma;
	148	unsigned int flags;
	149	unsigned int active_num;
	150	unsigned int pending_num;
	151	struct list_head active;
	152	struct list_head done;
	153	};
	154
31650d64 MV	155	struct mxs_dma_desc *mxs_dma_desc_alloc(void);
31650d64 MV	156	void mxs_dma_desc_free(struct mxs_dma_desc *);
31650d64 MV	157	int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
31650d64 MV	158
31650d64	159	int mxs_dma_go(int chan);
96666a39 MV	160	void mxs_dma_init(void);
	161	int mxs_dma_init_channel(int chan);
	162	int mxs_dma_release(int chan);
31650d64 MV	163
31650d64 MV	164	#endif /* __DMA_H__ */