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23608e23 JL |
1 | /* |
2 | * Based on Linux i.MX iomux-v3.h file: | |
3 | * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, | |
4 | * <armlinux@phytec.de> | |
5 | * | |
6 | * Copyright (C) 2011 Freescale Semiconductor, Inc. | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
23608e23 JL |
9 | */ |
10 | ||
11 | #ifndef __MACH_IOMUX_V3_H__ | |
12 | #define __MACH_IOMUX_V3_H__ | |
13 | ||
d73b9760 BT |
14 | #include <common.h> |
15 | ||
23608e23 JL |
16 | /* |
17 | * build IOMUX_PAD structure | |
18 | * | |
19 | * This iomux scheme is based around pads, which are the physical balls | |
20 | * on the processor. | |
21 | * | |
22 | * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls | |
23 | * things like driving strength and pullup/pulldown. | |
24 | * - Each pad can have but not necessarily does have an output routing register | |
25 | * (IOMUXC_SW_MUX_CTL_PAD_x). | |
26 | * - Each pad can have but not necessarily does have an input routing register | |
27 | * (IOMUXC_x_SELECT_INPUT) | |
28 | * | |
29 | * The three register sets do not have a fixed offset to each other, | |
30 | * hence we order this table by pad control registers (which all pads | |
31 | * have) and put the optional i/o routing registers into additional | |
32 | * fields. | |
33 | * | |
34 | * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode> | |
35 | * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> | |
36 | * | |
37 | * IOMUX/PAD Bit field definitions | |
38 | * | |
39 | * MUX_CTRL_OFS: 0..11 (12) | |
40 | * PAD_CTRL_OFS: 12..23 (12) | |
41 | * SEL_INPUT_OFS: 24..35 (12) | |
42 | * MUX_MODE + SION: 36..40 (5) | |
43 | * PAD_CTRL + NO_PAD_CTRL: 41..58 (18) | |
44 | * SEL_INP: 59..62 (4) | |
45 | * reserved: 63 (1) | |
46 | */ | |
47 | ||
48 | typedef u64 iomux_v3_cfg_t; | |
49 | ||
50 | #define MUX_CTRL_OFS_SHIFT 0 | |
51 | #define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) | |
52 | #define MUX_PAD_CTRL_OFS_SHIFT 12 | |
53 | #define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ | |
54 | MUX_PAD_CTRL_OFS_SHIFT) | |
55 | #define MUX_SEL_INPUT_OFS_SHIFT 24 | |
56 | #define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ | |
57 | MUX_SEL_INPUT_OFS_SHIFT) | |
58 | ||
59 | #define MUX_MODE_SHIFT 36 | |
60 | #define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) | |
61 | #define MUX_PAD_CTRL_SHIFT 41 | |
62 | #define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) | |
63 | #define MUX_SEL_INPUT_SHIFT 59 | |
64 | #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) | |
65 | ||
66 | #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) | |
67 | ||
68 | #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ | |
69 | sel_input, pad_ctrl) \ | |
70 | (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ | |
71 | ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ | |
72 | ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ | |
73 | ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ | |
74 | ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ | |
75 | ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) | |
76 | ||
24695208 BT |
77 | #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ |
78 | MUX_PAD_CTRL(pad)) | |
79 | ||
79a34d3c BT |
80 | #define __NA_ 0x000 |
81 | #define NO_MUX_I 0 | |
82 | #define NO_PAD_I 0 | |
83 | ||
23608e23 | 84 | #define NO_PAD_CTRL (1 << 17) |
23608e23 | 85 | |
d73b9760 BT |
86 | #ifdef CONFIG_MX6 |
87 | ||
dc88403e | 88 | #define PAD_CTL_HYS (1 << 16) |
79a34d3c | 89 | |
7e2173cf BT |
90 | #define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE) |
91 | #define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE) | |
92 | #define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE) | |
93 | #define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE) | |
94 | #define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE) | |
dc88403e | 95 | #define PAD_CTL_PKE (1 << 12) |
79a34d3c | 96 | |
dc88403e | 97 | #define PAD_CTL_ODE (1 << 11) |
79a34d3c | 98 | |
dc88403e FE |
99 | #define PAD_CTL_SPEED_LOW (1 << 6) |
100 | #define PAD_CTL_SPEED_MED (2 << 6) | |
101 | #define PAD_CTL_SPEED_HIGH (3 << 6) | |
79a34d3c | 102 | |
dc88403e FE |
103 | #define PAD_CTL_DSE_DISABLE (0 << 3) |
104 | #define PAD_CTL_DSE_240ohm (1 << 3) | |
105 | #define PAD_CTL_DSE_120ohm (2 << 3) | |
106 | #define PAD_CTL_DSE_80ohm (3 << 3) | |
107 | #define PAD_CTL_DSE_60ohm (4 << 3) | |
108 | #define PAD_CTL_DSE_48ohm (5 << 3) | |
109 | #define PAD_CTL_DSE_40ohm (6 << 3) | |
110 | #define PAD_CTL_DSE_34ohm (7 << 3) | |
d73b9760 | 111 | |
cfd701b5 AW |
112 | #elif defined(CONFIG_VF610) |
113 | ||
114 | #define PAD_MUX_MODE_SHIFT 20 | |
115 | ||
116 | #define PAD_CTL_SPEED_MED (1 << 12) | |
117 | #define PAD_CTL_SPEED_HIGH (3 << 12) | |
118 | ||
119 | #define PAD_CTL_DSE_50ohm (3 << 6) | |
120 | #define PAD_CTL_DSE_25ohm (6 << 6) | |
121 | #define PAD_CTL_DSE_20ohm (7 << 6) | |
122 | ||
123 | #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) | |
124 | #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) | |
125 | #define PAD_CTL_PKE (1 << 3) | |
126 | #define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) | |
127 | ||
128 | #define PAD_CTL_OBE_IBE_ENABLE (3 << 0) | |
129 | ||
d73b9760 BT |
130 | #else |
131 | ||
132 | #define PAD_CTL_DVS (1 << 13) | |
133 | #define PAD_CTL_INPUT_DDR (1 << 9) | |
134 | #define PAD_CTL_HYS (1 << 8) | |
135 | ||
136 | #define PAD_CTL_PKE (1 << 7) | |
137 | #define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) | |
138 | #define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) | |
139 | #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) | |
140 | #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) | |
141 | #define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) | |
142 | ||
143 | #define PAD_CTL_ODE (1 << 3) | |
144 | ||
145 | #define PAD_CTL_DSE_LOW (0 << 1) | |
146 | #define PAD_CTL_DSE_MED (1 << 1) | |
147 | #define PAD_CTL_DSE_HIGH (2 << 1) | |
148 | #define PAD_CTL_DSE_MAX (3 << 1) | |
149 | ||
150 | #endif | |
151 | ||
dc88403e | 152 | #define PAD_CTL_SRE_SLOW (0 << 0) |
79a34d3c | 153 | #define PAD_CTL_SRE_FAST (1 << 0) |
dc88403e FE |
154 | |
155 | #define IOMUX_CONFIG_SION 0x10 | |
79a34d3c BT |
156 | |
157 | #define GPIO_PIN_MASK 0x1f | |
158 | #define GPIO_PORT_SHIFT 5 | |
159 | #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) | |
160 | #define GPIO_PORTA (0 << GPIO_PORT_SHIFT) | |
161 | #define GPIO_PORTB (1 << GPIO_PORT_SHIFT) | |
162 | #define GPIO_PORTC (2 << GPIO_PORT_SHIFT) | |
163 | #define GPIO_PORTD (3 << GPIO_PORT_SHIFT) | |
164 | #define GPIO_PORTE (4 << GPIO_PORT_SHIFT) | |
165 | #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) | |
23608e23 | 166 | |
59efa051 SR |
167 | void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); |
168 | void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, | |
5ae28d2d | 169 | unsigned count); |
23608e23 JL |
170 | |
171 | #endif /* __MACH_IOMUX_V3_H__*/ |