[people/ms/u-boot.git] / arch / arm / include / asm / imx-common / iomux-v3.h

/*
 * Based on Linux i.MX iomux-v3.h file:
 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
 *			<armlinux@phytec.de>
 *
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MACH_IOMUX_V3_H__
#define __MACH_IOMUX_V3_H__

#include <common.h>

/*
 *	build IOMUX_PAD structure
 *
 * This iomux scheme is based around pads, which are the physical balls
 * on the processor.
 *
 * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
 *   things like driving strength and pullup/pulldown.
 * - Each pad can have but not necessarily does have an output routing register
 *   (IOMUXC_SW_MUX_CTL_PAD_x).
 * - Each pad can have but not necessarily does have an input routing register
 *   (IOMUXC_x_SELECT_INPUT)
 *
 * The three register sets do not have a fixed offset to each other,
 * hence we order this table by pad control registers (which all pads
 * have) and put the optional i/o routing registers into additional
 * fields.
 *
 * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
 *
 * IOMUX/PAD Bit field definitions
 *
 * MUX_CTRL_OFS:	    0..11 (12)
 * PAD_CTRL_OFS:	   12..23 (12)
 * SEL_INPUT_OFS:	   24..35 (12)
 * MUX_MODE + SION:	   36..40  (5)
 * PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
 * SEL_INP:		   59..62  (4)
 * reserved:		     63    (1)
*/

typedef u64 iomux_v3_cfg_t;

#define MUX_CTRL_OFS_SHIFT	0
#define MUX_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
#define MUX_PAD_CTRL_OFS_SHIFT	12
#define MUX_PAD_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << \
	MUX_PAD_CTRL_OFS_SHIFT)
#define MUX_SEL_INPUT_OFS_SHIFT	24
#define MUX_SEL_INPUT_OFS_MASK	((iomux_v3_cfg_t)0xfff << \
	MUX_SEL_INPUT_OFS_SHIFT)

#define MUX_MODE_SHIFT		36
#define MUX_MODE_MASK		((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
#define MUX_PAD_CTRL_SHIFT	41
#define MUX_PAD_CTRL_MASK	((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
#define MUX_SEL_INPUT_SHIFT	59
#define MUX_SEL_INPUT_MASK	((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)

#define MUX_MODE_SION		((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
	MUX_MODE_SHIFT)
#define MUX_PAD_CTRL(x)		((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)

#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,	\
		sel_input, pad_ctrl)					\
	(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT)     |	\
	((iomux_v3_cfg_t)(mux_mode)      << MUX_MODE_SHIFT)         |	\
	((iomux_v3_cfg_t)(pad_ctrl_ofs)  << MUX_PAD_CTRL_OFS_SHIFT) |	\
	((iomux_v3_cfg_t)(pad_ctrl)      << MUX_PAD_CTRL_SHIFT)     |	\
	((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)|	\
	((iomux_v3_cfg_t)(sel_input)     << MUX_SEL_INPUT_SHIFT))

#define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | \
					MUX_PAD_CTRL(pad))

#define __NA_			0x000
#define NO_MUX_I		0
#define NO_PAD_I		0

#define NO_PAD_CTRL		(1 << 17)

#ifdef CONFIG_MX6

#define PAD_CTL_HYS		(1 << 16)

#define PAD_CTL_PUS_100K_DOWN	(0 << 14 | PAD_CTL_PUE)
#define PAD_CTL_PUS_47K_UP	(1 << 14 | PAD_CTL_PUE)
#define PAD_CTL_PUS_100K_UP	(2 << 14 | PAD_CTL_PUE)
#define PAD_CTL_PUS_22K_UP	(3 << 14 | PAD_CTL_PUE)
#define PAD_CTL_PUE		(1 << 13 | PAD_CTL_PKE)
#define PAD_CTL_PKE		(1 << 12)

#define PAD_CTL_ODE		(1 << 11)

#define PAD_CTL_SPEED_LOW	(1 << 6)
#define PAD_CTL_SPEED_MED	(2 << 6)
#define PAD_CTL_SPEED_HIGH	(3 << 6)

#define PAD_CTL_DSE_DISABLE	(0 << 3)
#define PAD_CTL_DSE_240ohm	(1 << 3)
#define PAD_CTL_DSE_120ohm	(2 << 3)
#define PAD_CTL_DSE_80ohm	(3 << 3)
#define PAD_CTL_DSE_60ohm	(4 << 3)
#define PAD_CTL_DSE_48ohm	(5 << 3)
#define PAD_CTL_DSE_40ohm	(6 << 3)
#define PAD_CTL_DSE_34ohm	(7 << 3)

#if defined CONFIG_MX6SL
#define PAD_CTL_LVE		(1 << 1)
#define PAD_CTL_LVE_BIT		(1 << 22)
#endif

#elif defined(CONFIG_VF610)

#define PAD_MUX_MODE_SHIFT	20

#define PAD_CTL_SPEED_MED	(1 << 12)
#define PAD_CTL_SPEED_HIGH	(3 << 12)

#define PAD_CTL_DSE_50ohm	(3 << 6)
#define PAD_CTL_DSE_25ohm	(6 << 6)
#define PAD_CTL_DSE_20ohm	(7 << 6)

#define PAD_CTL_PUS_47K_UP	(1 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PUS_100K_UP	(2 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PKE		(1 << 3)
#define PAD_CTL_PUE		(1 << 2 | PAD_CTL_PKE)

#define PAD_CTL_OBE_IBE_ENABLE	(3 << 0)

#else

#define PAD_CTL_DVS		(1 << 13)
#define PAD_CTL_INPUT_DDR	(1 << 9)
#define PAD_CTL_HYS		(1 << 8)

#define PAD_CTL_PKE		(1 << 7)
#define PAD_CTL_PUE		(1 << 6 | PAD_CTL_PKE)
#define PAD_CTL_PUS_100K_DOWN	(0 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PUS_47K_UP	(1 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PUS_100K_UP	(2 << 4 | PAD_CTL_PUE)
#define PAD_CTL_PUS_22K_UP	(3 << 4 | PAD_CTL_PUE)

#define PAD_CTL_ODE		(1 << 3)

#define PAD_CTL_DSE_LOW		(0 << 1)
#define PAD_CTL_DSE_MED		(1 << 1)
#define PAD_CTL_DSE_HIGH	(2 << 1)
#define PAD_CTL_DSE_MAX		(3 << 1)

#endif

#define PAD_CTL_SRE_SLOW	(0 << 0)
#define PAD_CTL_SRE_FAST	(1 << 0)

#define IOMUX_CONFIG_SION	0x10

#define GPIO_PIN_MASK		0x1f
#define GPIO_PORT_SHIFT		5
#define GPIO_PORT_MASK		(0x7 << GPIO_PORT_SHIFT)
#define GPIO_PORTA		(0 << GPIO_PORT_SHIFT)
#define GPIO_PORTB		(1 << GPIO_PORT_SHIFT)
#define GPIO_PORTC		(2 << GPIO_PORT_SHIFT)
#define GPIO_PORTD		(3 << GPIO_PORT_SHIFT)
#define GPIO_PORTE		(4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF		(5 << GPIO_PORT_SHIFT)

void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
				     unsigned count);

#endif	/* __MACH_IOMUX_V3_H__*/
Commit	Line	Data
23608e23 JL	1	/*
	2	* Based on Linux i.MX iomux-v3.h file:
	3	* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
	4	* <armlinux@phytec.de>
	5	*
	6	* Copyright (C) 2011 Freescale Semiconductor, Inc.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
23608e23 JL	9	*/
	10
	11	#ifndef __MACH_IOMUX_V3_H__
	12	#define __MACH_IOMUX_V3_H__
	13
d73b9760 BT	14	#include <common.h>
d73b9760 BT	15
23608e23 JL	16	/*
	17	* build IOMUX_PAD structure
	18	*
	19	* This iomux scheme is based around pads, which are the physical balls
	20	* on the processor.
	21	*
	22	* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
	23	* things like driving strength and pullup/pulldown.
	24	* - Each pad can have but not necessarily does have an output routing register
	25	* (IOMUXC_SW_MUX_CTL_PAD_x).
	26	* - Each pad can have but not necessarily does have an input routing register
	27	* (IOMUXC_x_SELECT_INPUT)
	28	*
	29	* The three register sets do not have a fixed offset to each other,
	30	* hence we order this table by pad control registers (which all pads
	31	* have) and put the optional i/o routing registers into additional
	32	* fields.
	33	*
	34	* The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
	35	* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
	36	*
	37	* IOMUX/PAD Bit field definitions
	38	*
	39	* MUX_CTRL_OFS: 0..11 (12)
	40	* PAD_CTRL_OFS: 12..23 (12)
	41	* SEL_INPUT_OFS: 24..35 (12)
	42	* MUX_MODE + SION: 36..40 (5)
	43	* PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
	44	* SEL_INP: 59..62 (4)
	45	* reserved: 63 (1)
	46	*/
	47
	48	typedef u64 iomux_v3_cfg_t;
	49
	50	#define MUX_CTRL_OFS_SHIFT 0
	51	#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
	52	#define MUX_PAD_CTRL_OFS_SHIFT 12
	53	#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
	54	MUX_PAD_CTRL_OFS_SHIFT)
	55	#define MUX_SEL_INPUT_OFS_SHIFT 24
	56	#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
	57	MUX_SEL_INPUT_OFS_SHIFT)
	58
	59	#define MUX_MODE_SHIFT 36
	60	#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
	61	#define MUX_PAD_CTRL_SHIFT 41
	62	#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
	63	#define MUX_SEL_INPUT_SHIFT 59
	64	#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
	65
7773fd19 OS	66	#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
7773fd19 OS	67	MUX_MODE_SHIFT)
23608e23 JL	68	#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
	69
	70	#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
	71	sel_input, pad_ctrl) \
	72	(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) \| \
	73	((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) \| \
	74	((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) \| \
	75	((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) \| \
	76	((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)\| \
	77	((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
	78
24695208 BT	79	#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) \| \
	80	MUX_PAD_CTRL(pad))
	81
79a34d3c BT	82	#define __NA_ 0x000
	83	#define NO_MUX_I 0
	84	#define NO_PAD_I 0
	85
23608e23	86	#define NO_PAD_CTRL (1 << 17)
23608e23	87
d73b9760 BT	88	#ifdef CONFIG_MX6
d73b9760 BT	89
dc88403e	90	#define PAD_CTL_HYS (1 << 16)
79a34d3c	91
7e2173cf BT	92	#define PAD_CTL_PUS_100K_DOWN (0 << 14 \| PAD_CTL_PUE)
	93	#define PAD_CTL_PUS_47K_UP (1 << 14 \| PAD_CTL_PUE)
	94	#define PAD_CTL_PUS_100K_UP (2 << 14 \| PAD_CTL_PUE)
	95	#define PAD_CTL_PUS_22K_UP (3 << 14 \| PAD_CTL_PUE)
	96	#define PAD_CTL_PUE (1 << 13 \| PAD_CTL_PKE)
dc88403e	97	#define PAD_CTL_PKE (1 << 12)
79a34d3c	98
dc88403e	99	#define PAD_CTL_ODE (1 << 11)
79a34d3c	100
dc88403e FE	101	#define PAD_CTL_SPEED_LOW (1 << 6)
	102	#define PAD_CTL_SPEED_MED (2 << 6)
	103	#define PAD_CTL_SPEED_HIGH (3 << 6)
79a34d3c	104
dc88403e FE	105	#define PAD_CTL_DSE_DISABLE (0 << 3)
	106	#define PAD_CTL_DSE_240ohm (1 << 3)
	107	#define PAD_CTL_DSE_120ohm (2 << 3)
	108	#define PAD_CTL_DSE_80ohm (3 << 3)
	109	#define PAD_CTL_DSE_60ohm (4 << 3)
	110	#define PAD_CTL_DSE_48ohm (5 << 3)
	111	#define PAD_CTL_DSE_40ohm (6 << 3)
	112	#define PAD_CTL_DSE_34ohm (7 << 3)
d73b9760	113
98d2cffd FE	114	#if defined CONFIG_MX6SL
	115	#define PAD_CTL_LVE (1 << 1)
	116	#define PAD_CTL_LVE_BIT (1 << 22)
	117	#endif
	118
cfd701b5 AW	119	#elif defined(CONFIG_VF610)
	120
	121	#define PAD_MUX_MODE_SHIFT 20
	122
	123	#define PAD_CTL_SPEED_MED (1 << 12)
	124	#define PAD_CTL_SPEED_HIGH (3 << 12)
	125
	126	#define PAD_CTL_DSE_50ohm (3 << 6)
	127	#define PAD_CTL_DSE_25ohm (6 << 6)
	128	#define PAD_CTL_DSE_20ohm (7 << 6)
	129
	130	#define PAD_CTL_PUS_47K_UP (1 << 4 \| PAD_CTL_PUE)
	131	#define PAD_CTL_PUS_100K_UP (2 << 4 \| PAD_CTL_PUE)
	132	#define PAD_CTL_PKE (1 << 3)
	133	#define PAD_CTL_PUE (1 << 2 \| PAD_CTL_PKE)
	134
	135	#define PAD_CTL_OBE_IBE_ENABLE (3 << 0)
	136
d73b9760 BT	137	#else
	138
	139	#define PAD_CTL_DVS (1 << 13)
	140	#define PAD_CTL_INPUT_DDR (1 << 9)
	141	#define PAD_CTL_HYS (1 << 8)
	142
	143	#define PAD_CTL_PKE (1 << 7)
	144	#define PAD_CTL_PUE (1 << 6 \| PAD_CTL_PKE)
	145	#define PAD_CTL_PUS_100K_DOWN (0 << 4 \| PAD_CTL_PUE)
	146	#define PAD_CTL_PUS_47K_UP (1 << 4 \| PAD_CTL_PUE)
	147	#define PAD_CTL_PUS_100K_UP (2 << 4 \| PAD_CTL_PUE)
	148	#define PAD_CTL_PUS_22K_UP (3 << 4 \| PAD_CTL_PUE)
	149
	150	#define PAD_CTL_ODE (1 << 3)
	151
	152	#define PAD_CTL_DSE_LOW (0 << 1)
	153	#define PAD_CTL_DSE_MED (1 << 1)
	154	#define PAD_CTL_DSE_HIGH (2 << 1)
	155	#define PAD_CTL_DSE_MAX (3 << 1)
	156
	157	#endif
	158
dc88403e	159	#define PAD_CTL_SRE_SLOW (0 << 0)
79a34d3c	160	#define PAD_CTL_SRE_FAST (1 << 0)
dc88403e FE	161
dc88403e FE	162	#define IOMUX_CONFIG_SION 0x10
79a34d3c BT	163
	164	#define GPIO_PIN_MASK 0x1f
	165	#define GPIO_PORT_SHIFT 5
	166	#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
	167	#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
	168	#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
	169	#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
	170	#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
	171	#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
	172	#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
23608e23	173
59efa051 SR	174	void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
59efa051 SR	175	void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
5ae28d2d	176	unsigned count);
23608e23 JL	177
23608e23 JL	178	#endif /* __MACH_IOMUX_V3_H__*/