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fc684e87 PF |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Stefano Babic, DENX Software Engineering, sbabic@denx.de. | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef _SYS_PROTO_H_ | |
9 | #define _SYS_PROTO_H_ | |
10 | ||
11 | #include <asm/imx-common/regs-common.h> | |
12 | #include <common.h> | |
13 | #include "../arch-imx/cpu.h" | |
14 | ||
15 | #define soc_rev() (get_cpu_rev() & 0xFF) | |
16 | #define is_soc_rev(rev) (soc_rev() == rev) | |
17 | ||
18 | /* returns MXC_CPU_ value */ | |
19 | #define cpu_type(rev) (((rev) >> 12) & 0xff) | |
15c52b3d | 20 | #define soc_type(rev) (((rev) >> 12) & 0xf0) |
fc684e87 PF |
21 | /* both macros return/take MXC_CPU_ constants */ |
22 | #define get_cpu_type() (cpu_type(get_cpu_rev())) | |
15c52b3d | 23 | #define get_soc_type() (soc_type(get_cpu_rev())) |
fc684e87 | 24 | #define is_cpu_type(cpu) (get_cpu_type() == cpu) |
15c52b3d | 25 | #define is_soc_type(soc) (get_soc_type() == soc) |
fc684e87 | 26 | |
32ff58bb PF |
27 | #define is_mx6() (is_soc_type(MXC_SOC_MX6)) |
28 | #define is_mx7() (is_soc_type(MXC_SOC_MX7)) | |
29 | ||
fc684e87 | 30 | #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) |
32ff58bb PF |
31 | #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) |
32 | #define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL)) | |
f4b7532f | 33 | #define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL)) |
32ff58bb PF |
34 | #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX)) |
35 | #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) | |
f4b7532f | 36 | #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) |
32ff58bb | 37 | #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) |
bbd1b07d | 38 | #define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) |
7ce6d3c8 | 39 | #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) |
fc684e87 PF |
40 | |
41 | u32 get_nr_cpus(void); | |
42 | u32 get_cpu_rev(void); | |
43 | u32 get_cpu_speed_grade_hz(void); | |
44 | u32 get_cpu_temp_grade(int *minc, int *maxc); | |
45 | const char *get_imx_type(u32 imxtype); | |
46 | u32 imx_ddr_size(void); | |
47 | void sdelay(unsigned long); | |
48 | void set_chipselect_size(int const); | |
49 | ||
50a082a8 AA |
50 | void init_aips(void); |
51 | void init_src(void); | |
648539c9 | 52 | void imx_set_wdog_powerdown(bool enable); |
50a082a8 | 53 | |
fc684e87 PF |
54 | /* |
55 | * Initializes on-chip ethernet controllers. | |
56 | * to override, implement board_eth_init() | |
57 | */ | |
58 | int fecmxc_initialize(bd_t *bis); | |
59 | u32 get_ahb_clk(void); | |
60 | u32 get_periph_clk(void); | |
61 | ||
a3c252d6 PF |
62 | void lcdif_power_down(void); |
63 | ||
fc684e87 PF |
64 | int mxs_reset_block(struct mxs_register_32 *reg); |
65 | int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); | |
66 | int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); | |
67 | #endif |