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Commit | Line | Data |
---|---|---|
83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
d2f18c27 A |
2 | /* |
3 | * (C) Copyright 2010 | |
4 | * Texas Instruments, <www.ti.com> | |
5 | * | |
6 | * Aneesh V <aneesh@ti.com> | |
d2f18c27 A |
7 | */ |
8 | #ifndef _OMAP_COMMON_H_ | |
9 | #define _OMAP_COMMON_H_ | |
10 | ||
4a0eb757 S |
11 | #ifndef __ASSEMBLY__ |
12 | ||
01b753ff S |
13 | #include <common.h> |
14 | ||
97405d84 | 15 | #define NUM_SYS_CLKS 7 |
ee9447bf | 16 | |
01b753ff S |
17 | struct prcm_regs { |
18 | /* cm1.ckgen */ | |
19 | u32 cm_clksel_core; | |
20 | u32 cm_clksel_abe; | |
21 | u32 cm_dll_ctrl; | |
22 | u32 cm_clkmode_dpll_core; | |
23 | u32 cm_idlest_dpll_core; | |
24 | u32 cm_autoidle_dpll_core; | |
25 | u32 cm_clksel_dpll_core; | |
26 | u32 cm_div_m2_dpll_core; | |
27 | u32 cm_div_m3_dpll_core; | |
28 | u32 cm_div_h11_dpll_core; | |
29 | u32 cm_div_h12_dpll_core; | |
30 | u32 cm_div_h13_dpll_core; | |
31 | u32 cm_div_h14_dpll_core; | |
afc2f9dc S |
32 | u32 cm_div_h21_dpll_core; |
33 | u32 cm_div_h24_dpll_core; | |
01b753ff S |
34 | u32 cm_ssc_deltamstep_dpll_core; |
35 | u32 cm_ssc_modfreqdiv_dpll_core; | |
36 | u32 cm_emu_override_dpll_core; | |
37 | u32 cm_div_h22_dpllcore; | |
38 | u32 cm_div_h23_dpll_core; | |
39 | u32 cm_clkmode_dpll_mpu; | |
40 | u32 cm_idlest_dpll_mpu; | |
41 | u32 cm_autoidle_dpll_mpu; | |
42 | u32 cm_clksel_dpll_mpu; | |
43 | u32 cm_div_m2_dpll_mpu; | |
44 | u32 cm_ssc_deltamstep_dpll_mpu; | |
45 | u32 cm_ssc_modfreqdiv_dpll_mpu; | |
46 | u32 cm_bypclk_dpll_mpu; | |
47 | u32 cm_clkmode_dpll_iva; | |
48 | u32 cm_idlest_dpll_iva; | |
49 | u32 cm_autoidle_dpll_iva; | |
50 | u32 cm_clksel_dpll_iva; | |
51 | u32 cm_div_h11_dpll_iva; | |
52 | u32 cm_div_h12_dpll_iva; | |
53 | u32 cm_ssc_deltamstep_dpll_iva; | |
54 | u32 cm_ssc_modfreqdiv_dpll_iva; | |
55 | u32 cm_bypclk_dpll_iva; | |
56 | u32 cm_clkmode_dpll_abe; | |
57 | u32 cm_idlest_dpll_abe; | |
58 | u32 cm_autoidle_dpll_abe; | |
59 | u32 cm_clksel_dpll_abe; | |
60 | u32 cm_div_m2_dpll_abe; | |
61 | u32 cm_div_m3_dpll_abe; | |
62 | u32 cm_ssc_deltamstep_dpll_abe; | |
63 | u32 cm_ssc_modfreqdiv_dpll_abe; | |
64 | u32 cm_clkmode_dpll_ddrphy; | |
65 | u32 cm_idlest_dpll_ddrphy; | |
66 | u32 cm_autoidle_dpll_ddrphy; | |
67 | u32 cm_clksel_dpll_ddrphy; | |
68 | u32 cm_div_m2_dpll_ddrphy; | |
69 | u32 cm_div_h11_dpll_ddrphy; | |
70 | u32 cm_div_h12_dpll_ddrphy; | |
71 | u32 cm_div_h13_dpll_ddrphy; | |
72 | u32 cm_ssc_deltamstep_dpll_ddrphy; | |
d4e4129c | 73 | u32 cm_clkmode_dpll_dsp; |
01b753ff | 74 | u32 cm_shadow_freq_config1; |
65e9d56f | 75 | u32 cm_clkmode_dpll_gmac; |
01b753ff S |
76 | u32 cm_mpu_mpu_clkctrl; |
77 | ||
78 | /* cm1.dsp */ | |
79 | u32 cm_dsp_clkstctrl; | |
80 | u32 cm_dsp_dsp_clkctrl; | |
81 | ||
82 | /* cm1.abe */ | |
83 | u32 cm1_abe_clkstctrl; | |
84 | u32 cm1_abe_l4abe_clkctrl; | |
85 | u32 cm1_abe_aess_clkctrl; | |
86 | u32 cm1_abe_pdm_clkctrl; | |
87 | u32 cm1_abe_dmic_clkctrl; | |
88 | u32 cm1_abe_mcasp_clkctrl; | |
89 | u32 cm1_abe_mcbsp1_clkctrl; | |
90 | u32 cm1_abe_mcbsp2_clkctrl; | |
91 | u32 cm1_abe_mcbsp3_clkctrl; | |
92 | u32 cm1_abe_slimbus_clkctrl; | |
93 | u32 cm1_abe_timer5_clkctrl; | |
94 | u32 cm1_abe_timer6_clkctrl; | |
95 | u32 cm1_abe_timer7_clkctrl; | |
96 | u32 cm1_abe_timer8_clkctrl; | |
97 | u32 cm1_abe_wdt3_clkctrl; | |
98 | ||
99 | /* cm2.ckgen */ | |
100 | u32 cm_clksel_mpu_m3_iss_root; | |
101 | u32 cm_clksel_usb_60mhz; | |
102 | u32 cm_scale_fclk; | |
103 | u32 cm_core_dvfs_perf1; | |
104 | u32 cm_core_dvfs_perf2; | |
105 | u32 cm_core_dvfs_perf3; | |
106 | u32 cm_core_dvfs_perf4; | |
107 | u32 cm_core_dvfs_current; | |
108 | u32 cm_iva_dvfs_perf_tesla; | |
109 | u32 cm_iva_dvfs_perf_ivahd; | |
110 | u32 cm_iva_dvfs_perf_abe; | |
111 | u32 cm_iva_dvfs_current; | |
112 | u32 cm_clkmode_dpll_per; | |
113 | u32 cm_idlest_dpll_per; | |
114 | u32 cm_autoidle_dpll_per; | |
115 | u32 cm_clksel_dpll_per; | |
116 | u32 cm_div_m2_dpll_per; | |
117 | u32 cm_div_m3_dpll_per; | |
118 | u32 cm_div_h11_dpll_per; | |
119 | u32 cm_div_h12_dpll_per; | |
afc2f9dc | 120 | u32 cm_div_h13_dpll_per; |
01b753ff S |
121 | u32 cm_div_h14_dpll_per; |
122 | u32 cm_ssc_deltamstep_dpll_per; | |
123 | u32 cm_ssc_modfreqdiv_dpll_per; | |
124 | u32 cm_emu_override_dpll_per; | |
125 | u32 cm_clkmode_dpll_usb; | |
126 | u32 cm_idlest_dpll_usb; | |
127 | u32 cm_autoidle_dpll_usb; | |
128 | u32 cm_clksel_dpll_usb; | |
129 | u32 cm_div_m2_dpll_usb; | |
130 | u32 cm_ssc_deltamstep_dpll_usb; | |
131 | u32 cm_ssc_modfreqdiv_dpll_usb; | |
132 | u32 cm_clkdcoldo_dpll_usb; | |
d4e4129c LV |
133 | u32 cm_clkmode_dpll_pcie_ref; |
134 | u32 cm_clkmode_apll_pcie; | |
135 | u32 cm_idlest_apll_pcie; | |
136 | u32 cm_div_m2_apll_pcie; | |
137 | u32 cm_clkvcoldo_apll_pcie; | |
01b753ff S |
138 | u32 cm_clkmode_dpll_unipro; |
139 | u32 cm_idlest_dpll_unipro; | |
140 | u32 cm_autoidle_dpll_unipro; | |
141 | u32 cm_clksel_dpll_unipro; | |
142 | u32 cm_div_m2_dpll_unipro; | |
143 | u32 cm_ssc_deltamstep_dpll_unipro; | |
144 | u32 cm_ssc_modfreqdiv_dpll_unipro; | |
d3cfcb3e | 145 | u32 cm_coreaon_usb_phy1_core_clkctrl; |
834e91af | 146 | u32 cm_coreaon_usb_phy2_core_clkctrl; |
3599774e | 147 | u32 cm_coreaon_usb_phy3_core_clkctrl; |
7beaf8b6 | 148 | u32 cm_coreaon_l3init_60m_gfclk_clkctrl; |
01b753ff S |
149 | |
150 | /* cm2.core */ | |
151 | u32 cm_coreaon_bandgap_clkctrl; | |
d4d986ee | 152 | u32 cm_coreaon_io_srcomp_clkctrl; |
01b753ff S |
153 | u32 cm_l3_1_clkstctrl; |
154 | u32 cm_l3_1_dynamicdep; | |
155 | u32 cm_l3_1_l3_1_clkctrl; | |
156 | u32 cm_l3_2_clkstctrl; | |
157 | u32 cm_l3_2_dynamicdep; | |
158 | u32 cm_l3_2_l3_2_clkctrl; | |
d4e4129c | 159 | u32 cm_l3_gpmc_clkctrl; |
01b753ff S |
160 | u32 cm_l3_2_ocmc_ram_clkctrl; |
161 | u32 cm_mpu_m3_clkstctrl; | |
162 | u32 cm_mpu_m3_staticdep; | |
163 | u32 cm_mpu_m3_dynamicdep; | |
164 | u32 cm_mpu_m3_mpu_m3_clkctrl; | |
165 | u32 cm_sdma_clkstctrl; | |
166 | u32 cm_sdma_staticdep; | |
167 | u32 cm_sdma_dynamicdep; | |
168 | u32 cm_sdma_sdma_clkctrl; | |
169 | u32 cm_memif_clkstctrl; | |
170 | u32 cm_memif_dmm_clkctrl; | |
171 | u32 cm_memif_emif_fw_clkctrl; | |
172 | u32 cm_memif_emif_1_clkctrl; | |
173 | u32 cm_memif_emif_2_clkctrl; | |
174 | u32 cm_memif_dll_clkctrl; | |
175 | u32 cm_memif_emif_h1_clkctrl; | |
176 | u32 cm_memif_emif_h2_clkctrl; | |
177 | u32 cm_memif_dll_h_clkctrl; | |
178 | u32 cm_c2c_clkstctrl; | |
179 | u32 cm_c2c_staticdep; | |
180 | u32 cm_c2c_dynamicdep; | |
181 | u32 cm_c2c_sad2d_clkctrl; | |
182 | u32 cm_c2c_modem_icr_clkctrl; | |
183 | u32 cm_c2c_sad2d_fw_clkctrl; | |
184 | u32 cm_l4cfg_clkstctrl; | |
185 | u32 cm_l4cfg_dynamicdep; | |
186 | u32 cm_l4cfg_l4_cfg_clkctrl; | |
187 | u32 cm_l4cfg_hw_sem_clkctrl; | |
188 | u32 cm_l4cfg_mailbox_clkctrl; | |
189 | u32 cm_l4cfg_sar_rom_clkctrl; | |
190 | u32 cm_l3instr_clkstctrl; | |
191 | u32 cm_l3instr_l3_3_clkctrl; | |
192 | u32 cm_l3instr_l3_instr_clkctrl; | |
193 | u32 cm_l3instr_intrconn_wp1_clkctrl; | |
194 | ||
195 | /* cm2.ivahd */ | |
196 | u32 cm_ivahd_clkstctrl; | |
197 | u32 cm_ivahd_ivahd_clkctrl; | |
198 | u32 cm_ivahd_sl2_clkctrl; | |
199 | ||
200 | /* cm2.cam */ | |
201 | u32 cm_cam_clkstctrl; | |
202 | u32 cm_cam_iss_clkctrl; | |
203 | u32 cm_cam_fdif_clkctrl; | |
d4e4129c LV |
204 | u32 cm_cam_vip1_clkctrl; |
205 | u32 cm_cam_vip2_clkctrl; | |
206 | u32 cm_cam_vip3_clkctrl; | |
207 | u32 cm_cam_lvdsrx_clkctrl; | |
208 | u32 cm_cam_csi1_clkctrl; | |
209 | u32 cm_cam_csi2_clkctrl; | |
01b753ff S |
210 | |
211 | /* cm2.dss */ | |
212 | u32 cm_dss_clkstctrl; | |
213 | u32 cm_dss_dss_clkctrl; | |
214 | ||
215 | /* cm2.sgx */ | |
216 | u32 cm_sgx_clkstctrl; | |
217 | u32 cm_sgx_sgx_clkctrl; | |
218 | ||
219 | /* cm2.l3init */ | |
220 | u32 cm_l3init_clkstctrl; | |
221 | ||
222 | /* cm2.l3init */ | |
223 | u32 cm_l3init_hsmmc1_clkctrl; | |
224 | u32 cm_l3init_hsmmc2_clkctrl; | |
225 | u32 cm_l3init_hsi_clkctrl; | |
226 | u32 cm_l3init_hsusbhost_clkctrl; | |
227 | u32 cm_l3init_hsusbotg_clkctrl; | |
228 | u32 cm_l3init_hsusbtll_clkctrl; | |
229 | u32 cm_l3init_p1500_clkctrl; | |
8ffcf74b | 230 | u32 cm_l3init_sata_clkctrl; |
01b753ff S |
231 | u32 cm_l3init_fsusb_clkctrl; |
232 | u32 cm_l3init_ocp2scp1_clkctrl; | |
d861a333 | 233 | u32 cm_l3init_ocp2scp3_clkctrl; |
d3cfcb3e | 234 | u32 cm_l3init_usb_otg_ss1_clkctrl; |
7beaf8b6 | 235 | u32 cm_l3init_usb_otg_ss2_clkctrl; |
01b753ff | 236 | |
a818097a | 237 | u32 prm_irqstatus_mpu; |
4d0df9c1 AT |
238 | u32 prm_irqstatus_mpu_2; |
239 | ||
01b753ff S |
240 | /* cm2.l4per */ |
241 | u32 cm_l4per_clkstctrl; | |
242 | u32 cm_l4per_dynamicdep; | |
243 | u32 cm_l4per_adc_clkctrl; | |
244 | u32 cm_l4per_gptimer10_clkctrl; | |
245 | u32 cm_l4per_gptimer11_clkctrl; | |
246 | u32 cm_l4per_gptimer2_clkctrl; | |
247 | u32 cm_l4per_gptimer3_clkctrl; | |
248 | u32 cm_l4per_gptimer4_clkctrl; | |
249 | u32 cm_l4per_gptimer9_clkctrl; | |
250 | u32 cm_l4per_elm_clkctrl; | |
251 | u32 cm_l4per_gpio2_clkctrl; | |
252 | u32 cm_l4per_gpio3_clkctrl; | |
253 | u32 cm_l4per_gpio4_clkctrl; | |
254 | u32 cm_l4per_gpio5_clkctrl; | |
255 | u32 cm_l4per_gpio6_clkctrl; | |
256 | u32 cm_l4per_hdq1w_clkctrl; | |
257 | u32 cm_l4per_hecc1_clkctrl; | |
258 | u32 cm_l4per_hecc2_clkctrl; | |
259 | u32 cm_l4per_i2c1_clkctrl; | |
260 | u32 cm_l4per_i2c2_clkctrl; | |
261 | u32 cm_l4per_i2c3_clkctrl; | |
262 | u32 cm_l4per_i2c4_clkctrl; | |
263 | u32 cm_l4per_l4per_clkctrl; | |
264 | u32 cm_l4per_mcasp2_clkctrl; | |
265 | u32 cm_l4per_mcasp3_clkctrl; | |
266 | u32 cm_l4per_mgate_clkctrl; | |
267 | u32 cm_l4per_mcspi1_clkctrl; | |
268 | u32 cm_l4per_mcspi2_clkctrl; | |
269 | u32 cm_l4per_mcspi3_clkctrl; | |
270 | u32 cm_l4per_mcspi4_clkctrl; | |
271 | u32 cm_l4per_gpio7_clkctrl; | |
272 | u32 cm_l4per_gpio8_clkctrl; | |
273 | u32 cm_l4per_mmcsd3_clkctrl; | |
274 | u32 cm_l4per_mmcsd4_clkctrl; | |
275 | u32 cm_l4per_msprohg_clkctrl; | |
276 | u32 cm_l4per_slimbus2_clkctrl; | |
c97a9b32 | 277 | u32 cm_l4per_qspi_clkctrl; |
01b753ff S |
278 | u32 cm_l4per_uart1_clkctrl; |
279 | u32 cm_l4per_uart2_clkctrl; | |
280 | u32 cm_l4per_uart3_clkctrl; | |
281 | u32 cm_l4per_uart4_clkctrl; | |
282 | u32 cm_l4per_mmcsd5_clkctrl; | |
283 | u32 cm_l4per_i2c5_clkctrl; | |
284 | u32 cm_l4per_uart5_clkctrl; | |
285 | u32 cm_l4per_uart6_clkctrl; | |
286 | u32 cm_l4sec_clkstctrl; | |
287 | u32 cm_l4sec_staticdep; | |
288 | u32 cm_l4sec_dynamicdep; | |
289 | u32 cm_l4sec_aes1_clkctrl; | |
290 | u32 cm_l4sec_aes2_clkctrl; | |
291 | u32 cm_l4sec_des3des_clkctrl; | |
292 | u32 cm_l4sec_pkaeip29_clkctrl; | |
293 | u32 cm_l4sec_rng_clkctrl; | |
294 | u32 cm_l4sec_sha2md51_clkctrl; | |
295 | u32 cm_l4sec_cryptodma_clkctrl; | |
296 | ||
297 | /* l4 wkup regs */ | |
298 | u32 cm_abe_pll_ref_clksel; | |
299 | u32 cm_sys_clksel; | |
97405d84 | 300 | u32 cm_abe_pll_sys_clksel; |
01b753ff S |
301 | u32 cm_wkup_clkstctrl; |
302 | u32 cm_wkup_l4wkup_clkctrl; | |
303 | u32 cm_wkup_wdtimer1_clkctrl; | |
304 | u32 cm_wkup_wdtimer2_clkctrl; | |
305 | u32 cm_wkup_gpio1_clkctrl; | |
306 | u32 cm_wkup_gptimer1_clkctrl; | |
307 | u32 cm_wkup_gptimer12_clkctrl; | |
308 | u32 cm_wkup_synctimer_clkctrl; | |
309 | u32 cm_wkup_usim_clkctrl; | |
310 | u32 cm_wkup_sarram_clkctrl; | |
311 | u32 cm_wkup_keyboard_clkctrl; | |
312 | u32 cm_wkup_rtc_clkctrl; | |
313 | u32 cm_wkup_bandgap_clkctrl; | |
314 | u32 cm_wkupaon_scrm_clkctrl; | |
d4d986ee | 315 | u32 cm_wkupaon_io_srcomp_clkctrl; |
d4e4129c LV |
316 | u32 prm_rstctrl; |
317 | u32 prm_rstst; | |
0b1b60c7 | 318 | u32 prm_rsttime; |
eda6fbcc | 319 | u32 prm_io_pmctrl; |
01b753ff S |
320 | u32 prm_vc_val_bypass; |
321 | u32 prm_vc_cfg_i2c_mode; | |
322 | u32 prm_vc_cfg_i2c_clk; | |
4d0df9c1 AT |
323 | u32 prm_abbldo_mpu_setup; |
324 | u32 prm_abbldo_mpu_ctrl; | |
a818097a NM |
325 | u32 prm_abbldo_mm_setup; |
326 | u32 prm_abbldo_mm_ctrl; | |
e52e334e NM |
327 | u32 prm_abbldo_iva_setup; |
328 | u32 prm_abbldo_iva_ctrl; | |
329 | u32 prm_abbldo_eve_setup; | |
330 | u32 prm_abbldo_eve_ctrl; | |
331 | u32 prm_abbldo_gpu_setup; | |
332 | u32 prm_abbldo_gpu_ctrl; | |
01b753ff S |
333 | |
334 | u32 cm_div_m4_dpll_core; | |
335 | u32 cm_div_m5_dpll_core; | |
336 | u32 cm_div_m6_dpll_core; | |
337 | u32 cm_div_m7_dpll_core; | |
338 | u32 cm_div_m4_dpll_iva; | |
339 | u32 cm_div_m5_dpll_iva; | |
340 | u32 cm_div_m4_dpll_ddrphy; | |
341 | u32 cm_div_m5_dpll_ddrphy; | |
342 | u32 cm_div_m6_dpll_ddrphy; | |
343 | u32 cm_div_m4_dpll_per; | |
344 | u32 cm_div_m5_dpll_per; | |
345 | u32 cm_div_m6_dpll_per; | |
346 | u32 cm_div_m7_dpll_per; | |
347 | u32 cm_l3instr_intrconn_wp1_clkct; | |
348 | u32 cm_l3init_usbphy_clkctrl; | |
349 | u32 cm_l4per_mcbsp4_clkctrl; | |
350 | u32 prm_vc_cfg_channel; | |
ee28edac LP |
351 | |
352 | /* SCRM stuff, used by some boards */ | |
353 | u32 scrm_auxclk0; | |
354 | u32 scrm_auxclk1; | |
f986d972 M |
355 | |
356 | /* GMAC Clk Ctrl */ | |
357 | u32 cm_gmac_gmac_clkctrl; | |
358 | u32 cm_gmac_clkstctrl; | |
37be54fd LV |
359 | |
360 | /* IPU */ | |
361 | u32 cm_ipu_clkstctrl; | |
362 | u32 cm_ipu_i2c5_clkctrl; | |
8a09cfe1 V |
363 | |
364 | /*l3main1 edma*/ | |
365 | u32 cm_l3main1_tptc1_clkctrl; | |
366 | u32 cm_l3main1_tptc2_clkctrl; | |
01b753ff S |
367 | }; |
368 | ||
c43c8339 LV |
369 | struct omap_sys_ctrl_regs { |
370 | u32 control_status; | |
b1e26e3b M |
371 | u32 control_core_mac_id_0_lo; |
372 | u32 control_core_mac_id_0_hi; | |
373 | u32 control_core_mac_id_1_lo; | |
374 | u32 control_core_mac_id_1_hi; | |
d861a333 | 375 | u32 control_phy_power_usb; |
8b12f177 LV |
376 | u32 control_core_mmr_lock1; |
377 | u32 control_core_mmr_lock2; | |
378 | u32 control_core_mmr_lock3; | |
379 | u32 control_core_mmr_lock4; | |
380 | u32 control_core_mmr_lock5; | |
381 | u32 control_core_control_io1; | |
382 | u32 control_core_control_io2; | |
c43c8339 | 383 | u32 control_id_code; |
f12467d1 DK |
384 | u32 control_std_fuse_die_id_0; |
385 | u32 control_std_fuse_die_id_1; | |
386 | u32 control_std_fuse_die_id_2; | |
387 | u32 control_std_fuse_die_id_3; | |
c43c8339 LV |
388 | u32 control_std_fuse_opp_bgap; |
389 | u32 control_ldosram_iva_voltage_ctrl; | |
390 | u32 control_ldosram_mpu_voltage_ctrl; | |
391 | u32 control_ldosram_core_voltage_ctrl; | |
9239f5b6 | 392 | u32 control_usbotghs_ctrl; |
8ffcf74b | 393 | u32 control_phy_power_sata; |
8b12f177 | 394 | u32 control_padconf_core_base; |
c43c8339 LV |
395 | u32 control_paconf_global; |
396 | u32 control_paconf_mode; | |
397 | u32 control_smart1io_padconf_0; | |
398 | u32 control_smart1io_padconf_1; | |
399 | u32 control_smart1io_padconf_2; | |
400 | u32 control_smart2io_padconf_0; | |
401 | u32 control_smart2io_padconf_1; | |
402 | u32 control_smart2io_padconf_2; | |
403 | u32 control_smart3io_padconf_0; | |
404 | u32 control_smart3io_padconf_1; | |
405 | u32 control_pbias; | |
406 | u32 control_i2c_0; | |
407 | u32 control_camera_rx; | |
408 | u32 control_hdmi_tx_phy; | |
409 | u32 control_uniportm; | |
410 | u32 control_dsiphy; | |
411 | u32 control_mcbsplp; | |
412 | u32 control_usb2phycore; | |
413 | u32 control_hdmi_1; | |
414 | u32 control_hsi; | |
415 | u32 control_ddr3ch1_0; | |
416 | u32 control_ddr3ch2_0; | |
417 | u32 control_ddrch1_0; | |
418 | u32 control_ddrch1_1; | |
419 | u32 control_ddrch2_0; | |
420 | u32 control_ddrch2_1; | |
421 | u32 control_lpddr2ch1_0; | |
422 | u32 control_lpddr2ch1_1; | |
423 | u32 control_ddrio_0; | |
424 | u32 control_ddrio_1; | |
425 | u32 control_ddrio_2; | |
92b0482c | 426 | u32 control_ddr_control_ext_0; |
c43c8339 LV |
427 | u32 control_lpddr2io1_0; |
428 | u32 control_lpddr2io1_1; | |
429 | u32 control_lpddr2io1_2; | |
430 | u32 control_lpddr2io1_3; | |
431 | u32 control_lpddr2io2_0; | |
432 | u32 control_lpddr2io2_1; | |
433 | u32 control_lpddr2io2_2; | |
434 | u32 control_lpddr2io2_3; | |
435 | u32 control_hyst_1; | |
436 | u32 control_usbb_hsic_control; | |
437 | u32 control_c2c; | |
438 | u32 control_core_control_spare_rw; | |
439 | u32 control_core_control_spare_r; | |
440 | u32 control_core_control_spare_r_c0; | |
441 | u32 control_srcomp_north_side; | |
442 | u32 control_srcomp_south_side; | |
443 | u32 control_srcomp_east_side; | |
444 | u32 control_srcomp_west_side; | |
445 | u32 control_srcomp_code_latch; | |
446 | u32 control_pbiaslite; | |
447 | u32 control_port_emif1_sdram_config; | |
448 | u32 control_port_emif1_lpddr2_nvm_config; | |
449 | u32 control_port_emif2_sdram_config; | |
450 | u32 control_emif1_sdram_config_ext; | |
451 | u32 control_emif2_sdram_config_ext; | |
4d0df9c1 | 452 | u32 control_wkup_ldovbb_mpu_voltage_ctrl; |
a818097a | 453 | u32 control_wkup_ldovbb_mm_voltage_ctrl; |
e52e334e NM |
454 | u32 control_wkup_ldovbb_iva_voltage_ctrl; |
455 | u32 control_wkup_ldovbb_eve_voltage_ctrl; | |
456 | u32 control_wkup_ldovbb_gpu_voltage_ctrl; | |
c43c8339 LV |
457 | u32 control_smart1nopmio_padconf_0; |
458 | u32 control_smart1nopmio_padconf_1; | |
459 | u32 control_padconf_mode; | |
460 | u32 control_xtal_oscillator; | |
461 | u32 control_i2c_2; | |
462 | u32 control_ckobuffer; | |
463 | u32 control_wkup_control_spare_rw; | |
464 | u32 control_wkup_control_spare_r; | |
465 | u32 control_wkup_control_spare_r_c0; | |
466 | u32 control_srcomp_east_side_wkup; | |
467 | u32 control_efuse_1; | |
468 | u32 control_efuse_2; | |
469 | u32 control_efuse_3; | |
470 | u32 control_efuse_4; | |
471 | u32 control_efuse_5; | |
472 | u32 control_efuse_6; | |
473 | u32 control_efuse_7; | |
474 | u32 control_efuse_8; | |
475 | u32 control_efuse_9; | |
476 | u32 control_efuse_10; | |
477 | u32 control_efuse_11; | |
478 | u32 control_efuse_12; | |
479 | u32 control_efuse_13; | |
8b12f177 | 480 | u32 control_padconf_wkup_base; |
eda6fbcc LV |
481 | u32 iodelay_config_base; |
482 | u32 ctrl_core_sma_sw_0; | |
76cff2b1 | 483 | u32 ctrl_core_sma_sw_1; |
c43c8339 LV |
484 | }; |
485 | ||
00bbe96e | 486 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) |
ee9447bf S |
487 | struct dpll_params { |
488 | u32 m; | |
489 | u32 n; | |
490 | s8 m2; | |
491 | s8 m3; | |
492 | s8 m4_h11; | |
493 | s8 m5_h12; | |
494 | s8 m6_h13; | |
495 | s8 m7_h14; | |
47abc3df | 496 | s8 h21; |
ee9447bf S |
497 | s8 h22; |
498 | s8 h23; | |
47abc3df | 499 | s8 h24; |
ee9447bf S |
500 | }; |
501 | ||
502 | struct dpll_regs { | |
503 | u32 cm_clkmode_dpll; | |
504 | u32 cm_idlest_dpll; | |
505 | u32 cm_autoidle_dpll; | |
506 | u32 cm_clksel_dpll; | |
507 | u32 cm_div_m2_dpll; | |
508 | u32 cm_div_m3_dpll; | |
509 | u32 cm_div_m4_h11_dpll; | |
510 | u32 cm_div_m5_h12_dpll; | |
511 | u32 cm_div_m6_h13_dpll; | |
512 | u32 cm_div_m7_h14_dpll; | |
47abc3df S |
513 | u32 reserved[2]; |
514 | u32 cm_div_h21_dpll; | |
ee9447bf S |
515 | u32 cm_div_h22_dpll; |
516 | u32 cm_div_h23_dpll; | |
47abc3df | 517 | u32 cm_div_h24_dpll; |
ee9447bf | 518 | }; |
00bbe96e | 519 | #endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ |
ee9447bf S |
520 | |
521 | struct dplls { | |
522 | const struct dpll_params *mpu; | |
523 | const struct dpll_params *core; | |
524 | const struct dpll_params *per; | |
525 | const struct dpll_params *abe; | |
526 | const struct dpll_params *iva; | |
527 | const struct dpll_params *usb; | |
ea8eff1f | 528 | const struct dpll_params *ddr; |
65e9d56f | 529 | const struct dpll_params *gmac; |
ee9447bf S |
530 | }; |
531 | ||
3fcdd4a5 S |
532 | struct pmic_data { |
533 | u32 base_offset; | |
534 | u32 step; | |
535 | u32 start_code; | |
536 | unsigned gpio; | |
537 | int gpio_en; | |
4ca94d81 LV |
538 | u32 i2c_slave_addr; |
539 | void (*pmic_bus_init)(void); | |
540 | int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); | |
3fcdd4a5 S |
541 | }; |
542 | ||
00bbe96e | 543 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) |
beb71279 LV |
544 | enum { |
545 | OPP_LOW, | |
546 | OPP_NOM, | |
547 | OPP_OD, | |
548 | OPP_HIGH, | |
549 | NUM_OPPS, | |
550 | }; | |
551 | ||
18c9d55a NM |
552 | /** |
553 | * struct volts_efuse_data - efuse definition for voltage | |
554 | * @reg: register address for efuse | |
555 | * @reg_bits: Number of bits in a register address, mandatory. | |
556 | */ | |
557 | struct volts_efuse_data { | |
beb71279 | 558 | u32 reg[NUM_OPPS]; |
18c9d55a | 559 | u8 reg_bits; |
3fcdd4a5 S |
560 | }; |
561 | ||
562 | struct volts { | |
beb71279 | 563 | u32 value[NUM_OPPS]; |
3fcdd4a5 | 564 | u32 addr; |
18c9d55a | 565 | struct volts_efuse_data efuse; |
3fcdd4a5 | 566 | struct pmic_data *pmic; |
3708e78c NM |
567 | |
568 | u32 abb_tx_done_mask; | |
3fcdd4a5 S |
569 | }; |
570 | ||
beb71279 LV |
571 | enum { |
572 | VOLT_MPU, | |
573 | VOLT_CORE, | |
574 | VOLT_MM, | |
575 | VOLT_GPU, | |
576 | VOLT_EVE, | |
577 | VOLT_IVA, | |
578 | NUM_VOLT_RAILS, | |
579 | }; | |
580 | ||
3fcdd4a5 S |
581 | struct vcores_data { |
582 | struct volts mpu; | |
583 | struct volts core; | |
584 | struct volts mm; | |
63fc0c77 LV |
585 | struct volts gpu; |
586 | struct volts eve; | |
587 | struct volts iva; | |
3fcdd4a5 | 588 | }; |
00bbe96e | 589 | #endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ |
3fcdd4a5 | 590 | |
01b753ff S |
591 | extern struct prcm_regs const **prcm; |
592 | extern struct prcm_regs const omap5_es1_prcm; | |
afc2f9dc | 593 | extern struct prcm_regs const omap5_es2_prcm; |
01b753ff | 594 | extern struct prcm_regs const omap4_prcm; |
d4e4129c | 595 | extern struct prcm_regs const dra7xx_prcm; |
ee9447bf | 596 | extern struct dplls const **dplls_data; |
56fe4055 | 597 | extern struct dplls dra7xx_dplls; |
209742fa | 598 | extern struct dplls dra72x_dplls; |
10f430f3 | 599 | extern struct dplls dra76x_dplls; |
3fcdd4a5 | 600 | extern struct vcores_data const **omap_vcores; |
ee9447bf | 601 | extern const u32 sys_clk_array[8]; |
c43c8339 | 602 | extern struct omap_sys_ctrl_regs const **ctrl; |
00bbe96e SP |
603 | extern struct omap_sys_ctrl_regs const am33xx_ctrl; |
604 | extern struct omap_sys_ctrl_regs const omap3_ctrl; | |
c43c8339 LV |
605 | extern struct omap_sys_ctrl_regs const omap4_ctrl; |
606 | extern struct omap_sys_ctrl_regs const omap5_ctrl; | |
8b12f177 | 607 | extern struct omap_sys_ctrl_regs const dra7xx_ctrl; |
01b753ff | 608 | |
56fe4055 | 609 | extern struct pmic_data tps659038; |
f56e6350 | 610 | extern struct pmic_data lp8733; |
c2476055 | 611 | extern struct pmic_data lp87565; |
56fe4055 | 612 | |
01b753ff | 613 | void hw_data_init(void); |
ee9447bf S |
614 | |
615 | const struct dpll_params *get_mpu_dpll_params(struct dplls const *); | |
616 | const struct dpll_params *get_core_dpll_params(struct dplls const *); | |
617 | const struct dpll_params *get_per_dpll_params(struct dplls const *); | |
618 | const struct dpll_params *get_iva_dpll_params(struct dplls const *); | |
619 | const struct dpll_params *get_usb_dpll_params(struct dplls const *); | |
620 | const struct dpll_params *get_abe_dpll_params(struct dplls const *); | |
621 | ||
00bbe96e | 622 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) |
ee9447bf S |
623 | void do_enable_clocks(u32 const *clk_domains, |
624 | u32 const *clk_modules_hw_auto, | |
625 | u32 const *clk_modules_explicit_en, | |
626 | u8 wait_for_enable); | |
627 | ||
16ca1d09 KVA |
628 | void do_disable_clocks(u32 const *clk_domains, |
629 | u32 const *clk_modules_disable, | |
630 | u8 wait_for_disable); | |
00bbe96e | 631 | #endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ |
16ca1d09 | 632 | |
ee9447bf S |
633 | void setup_post_dividers(u32 const base, |
634 | const struct dpll_params *params); | |
635 | u32 omap_ddr_clk(void); | |
636 | u32 get_sys_clk_index(void); | |
637 | void enable_basic_clocks(void); | |
638 | void enable_basic_uboot_clocks(void); | |
ca5a0f17 KVA |
639 | |
640 | void enable_usb_clocks(int index); | |
641 | void disable_usb_clocks(int index); | |
642 | ||
00bbe96e | 643 | #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) |
3fcdd4a5 | 644 | void scale_vcores(struct vcores_data const *); |
00bbe96e | 645 | #endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ |
beb71279 | 646 | int get_voltrail_opp(int rail_offset); |
3fcdd4a5 S |
647 | u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); |
648 | void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); | |
4d0df9c1 AT |
649 | void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, |
650 | u32 txdone, u32 txdone_mask, u32 opp); | |
651 | s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); | |
3776801d | 652 | |
5d982856 SG |
653 | struct tag_serialnr; |
654 | ||
07815eb9 | 655 | void omap_die_id_serial(void); |
2da87ab3 | 656 | void omap_die_id_get_board_serial(struct tag_serialnr *serialnr); |
07815eb9 | 657 | void omap_die_id_usbethaddr(void); |
679f82c3 | 658 | void omap_die_id_display(void); |
07815eb9 | 659 | |
fa24eca1 SP |
660 | #ifdef CONFIG_FASTBOOT_FLASH |
661 | void omap_set_fastboot_vars(void); | |
662 | #else | |
663 | static inline void omap_set_fastboot_vars(void) { } | |
664 | #endif | |
665 | ||
eda6fbcc | 666 | void recalibrate_iodelay(void); |
8a0c6d6f | 667 | |
6d8abe6a NM |
668 | void omap_smc1(u32 service, u32 val); |
669 | ||
51d06386 DA |
670 | /* |
671 | * Low-level helper function used when performing secure ROM calls on high- | |
672 | * security (HS) device variants by doing a specially-formed smc entry. | |
673 | */ | |
674 | u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params); | |
4c158b9a | 675 | u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params); |
51d06386 | 676 | |
8a09cfe1 V |
677 | void enable_edma3_clocks(void); |
678 | void disable_edma3_clocks(void); | |
679 | ||
72931b15 PK |
680 | void omap_die_id(unsigned int *die_id); |
681 | ||
725700dc KS |
682 | /* Initialize general purpose I2C(0) on the SoC */ |
683 | void gpi2c_init(void); | |
684 | ||
03750231 AD |
685 | /* Common FDT Fixups */ |
686 | int ft_hs_disable_rng(void *fdt, bd_t *bd); | |
687 | int ft_hs_fixup_dram(void *fdt, bd_t *bd); | |
688 | int ft_hs_add_tee(void *fdt, bd_t *bd); | |
689 | ||
4d0df9c1 AT |
690 | /* ABB */ |
691 | #define OMAP_ABB_NOMINAL_OPP 0 | |
692 | #define OMAP_ABB_FAST_OPP 1 | |
693 | #define OMAP_ABB_SLOW_OPP 3 | |
694 | #define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0) | |
695 | #define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1) | |
696 | #define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2) | |
697 | #define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6) | |
698 | #define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0) | |
699 | #define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2) | |
700 | #define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1) | |
701 | #define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8) | |
702 | ||
087189fb S |
703 | static inline u32 omap_revision(void) |
704 | { | |
705 | extern u32 *const omap_si_rev; | |
706 | return *omap_si_rev; | |
707 | } | |
e9d6cd04 | 708 | |
8c16dd6f RN |
709 | #define OMAP44xx 0x44000000 |
710 | ||
711 | static inline u8 is_omap44xx(void) | |
712 | { | |
713 | extern u32 *const omap_si_rev; | |
714 | return (*omap_si_rev & 0xFF000000) == OMAP44xx; | |
715 | }; | |
716 | ||
e9d6cd04 LV |
717 | #define OMAP54xx 0x54000000 |
718 | ||
719 | static inline u8 is_omap54xx(void) | |
720 | { | |
721 | extern u32 *const omap_si_rev; | |
722 | return ((*omap_si_rev & 0xFF000000) == OMAP54xx); | |
723 | } | |
39302dcd S |
724 | |
725 | #define DRA7XX 0x07000000 | |
c7400e48 | 726 | #define DRA72X 0x07200000 |
0f9e6aee | 727 | #define DRA76X 0x07600000 |
39302dcd S |
728 | |
729 | static inline u8 is_dra7xx(void) | |
730 | { | |
731 | extern u32 *const omap_si_rev; | |
732 | return ((*omap_si_rev & 0xFF000000) == DRA7XX); | |
733 | } | |
c7400e48 LV |
734 | |
735 | static inline u8 is_dra72x(void) | |
736 | { | |
737 | extern u32 *const omap_si_rev; | |
738 | return (*omap_si_rev & 0xFFF00000) == DRA72X; | |
739 | } | |
0f9e6aee PB |
740 | |
741 | static inline u8 is_dra76x(void) | |
742 | { | |
743 | extern u32 *const omap_si_rev; | |
744 | return (*omap_si_rev & 0xFFF00000) == DRA76X; | |
745 | } | |
941f2fcc LV |
746 | |
747 | static inline u8 is_dra76x_abz(void) | |
748 | { | |
749 | extern u32 *const omap_si_rev; | |
750 | return (*omap_si_rev & 0xF) == 2; | |
751 | } | |
752 | ||
753 | static inline u8 is_dra76x_acd(void) | |
754 | { | |
755 | extern u32 *const omap_si_rev; | |
756 | return (*omap_si_rev & 0xF) == 3; | |
757 | } | |
4a0eb757 | 758 | #endif |
087189fb | 759 | |
508a58fa S |
760 | /* |
761 | * silicon revisions. | |
762 | * Moving this to common, so that most of code can be moved to common, | |
763 | * directories. | |
764 | */ | |
765 | ||
766 | /* omap4 */ | |
767 | #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF | |
768 | #define OMAP4430_ES1_0 0x44300100 | |
769 | #define OMAP4430_ES2_0 0x44300200 | |
770 | #define OMAP4430_ES2_1 0x44300210 | |
771 | #define OMAP4430_ES2_2 0x44300220 | |
772 | #define OMAP4430_ES2_3 0x44300230 | |
773 | #define OMAP4460_ES1_0 0x44600100 | |
9404758e | 774 | #define OMAP4460_ES1_1 0x44600110 |
696f81f9 | 775 | #define OMAP4470_ES1_0 0x44700100 |
508a58fa S |
776 | |
777 | /* omap5 */ | |
778 | #define OMAP5430_SILICON_ID_INVALID 0 | |
779 | #define OMAP5430_ES1_0 0x54300100 | |
0a0bf7b2 | 780 | #define OMAP5432_ES1_0 0x54320100 |
eed7c0f7 S |
781 | #define OMAP5430_ES2_0 0x54300200 |
782 | #define OMAP5432_ES2_0 0x54320200 | |
de62688b LV |
783 | |
784 | /* DRA7XX */ | |
0f9e6aee | 785 | #define DRA762_ES1_0 0x07620100 |
de62688b | 786 | #define DRA752_ES1_0 0x07520100 |
3ac8c0bf | 787 | #define DRA752_ES1_1 0x07520110 |
c1ea3bec | 788 | #define DRA752_ES2_0 0x07520200 |
ee77a238 | 789 | #define DRA722_ES1_0 0x07220100 |
d851ad3a | 790 | #define DRA722_ES2_0 0x07220200 |
ba396081 | 791 | #define DRA722_ES2_1 0x07220210 |
f92f2277 | 792 | |
941f2fcc LV |
793 | #define DRA762_ABZ_ES1_0 0x07620102 |
794 | #define DRA762_ACD_ES1_0 0x07620103 | |
47c331ed DA |
795 | /* |
796 | * silicon device type | |
797 | * Moving to common from cpu.h, since it is shared by various omap devices | |
798 | */ | |
47c331ed DA |
799 | #define TST_DEVICE 0x0 |
800 | #define EMU_DEVICE 0x1 | |
801 | #define HS_DEVICE 0x2 | |
802 | #define GP_DEVICE 0x3 | |
803 | ||
804 | ||
f92f2277 S |
805 | /* |
806 | * SRAM scratch space entries | |
807 | */ | |
f92f2277 S |
808 | #define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR |
809 | #define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) | |
810 | #define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) | |
811 | #define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) | |
812 | #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) | |
813 | #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) | |
814 | #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) | |
815 | #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) | |
fda06812 | 816 | #define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24) |
63989286 LV |
817 | #ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START |
818 | #define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28) | |
819 | #define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) | |
820 | #endif | |
821 | #define OMAP_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) | |
fda06812 | 822 | |
60c7c30a PK |
823 | /* Boot parameters */ |
824 | #define DEVICE_DATA_OFFSET 0x18 | |
825 | #define BOOT_MODE_OFFSET 0x8 | |
826 | ||
827 | #define CH_FLAGS_CHSETTINGS (1 << 0) | |
828 | #define CH_FLAGS_CHRAM (1 << 1) | |
829 | #define CH_FLAGS_CHFLASH (1 << 2) | |
830 | #define CH_FLAGS_CHMMCSD (1 << 3) | |
831 | ||
ed19bdae PK |
832 | #ifndef __ASSEMBLY__ |
833 | u32 omap_sys_boot_device(void); | |
834 | #endif | |
835 | ||
d2f18c27 | 836 | #endif /* _OMAP_COMMON_H_ */ |