[people/ms/u-boot.git] / arch / arm / include / asm / omap_common.h

/*
 * (C) Copyright 2010
 * Texas Instruments, <www.ti.com>
 *
 * Aneesh V <aneesh@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef	_OMAP_COMMON_H_
#define	_OMAP_COMMON_H_

#ifndef __ASSEMBLY__

#include <common.h>

#define NUM_SYS_CLKS	8

struct prcm_regs {
	/* cm1.ckgen */
	u32 cm_clksel_core;
	u32 cm_clksel_abe;
	u32 cm_dll_ctrl;
	u32 cm_clkmode_dpll_core;
	u32 cm_idlest_dpll_core;
	u32 cm_autoidle_dpll_core;
	u32 cm_clksel_dpll_core;
	u32 cm_div_m2_dpll_core;
	u32 cm_div_m3_dpll_core;
	u32 cm_div_h11_dpll_core;
	u32 cm_div_h12_dpll_core;
	u32 cm_div_h13_dpll_core;
	u32 cm_div_h14_dpll_core;
	u32 cm_div_h21_dpll_core;
	u32 cm_div_h24_dpll_core;
	u32 cm_ssc_deltamstep_dpll_core;
	u32 cm_ssc_modfreqdiv_dpll_core;
	u32 cm_emu_override_dpll_core;
	u32 cm_div_h22_dpllcore;
	u32 cm_div_h23_dpll_core;
	u32 cm_clkmode_dpll_mpu;
	u32 cm_idlest_dpll_mpu;
	u32 cm_autoidle_dpll_mpu;
	u32 cm_clksel_dpll_mpu;
	u32 cm_div_m2_dpll_mpu;
	u32 cm_ssc_deltamstep_dpll_mpu;
	u32 cm_ssc_modfreqdiv_dpll_mpu;
	u32 cm_bypclk_dpll_mpu;
	u32 cm_clkmode_dpll_iva;
	u32 cm_idlest_dpll_iva;
	u32 cm_autoidle_dpll_iva;
	u32 cm_clksel_dpll_iva;
	u32 cm_div_h11_dpll_iva;
	u32 cm_div_h12_dpll_iva;
	u32 cm_ssc_deltamstep_dpll_iva;
	u32 cm_ssc_modfreqdiv_dpll_iva;
	u32 cm_bypclk_dpll_iva;
	u32 cm_clkmode_dpll_abe;
	u32 cm_idlest_dpll_abe;
	u32 cm_autoidle_dpll_abe;
	u32 cm_clksel_dpll_abe;
	u32 cm_div_m2_dpll_abe;
	u32 cm_div_m3_dpll_abe;
	u32 cm_ssc_deltamstep_dpll_abe;
	u32 cm_ssc_modfreqdiv_dpll_abe;
	u32 cm_clkmode_dpll_ddrphy;
	u32 cm_idlest_dpll_ddrphy;
	u32 cm_autoidle_dpll_ddrphy;
	u32 cm_clksel_dpll_ddrphy;
	u32 cm_div_m2_dpll_ddrphy;
	u32 cm_div_h11_dpll_ddrphy;
	u32 cm_div_h12_dpll_ddrphy;
	u32 cm_div_h13_dpll_ddrphy;
	u32 cm_ssc_deltamstep_dpll_ddrphy;
	u32 cm_clkmode_dpll_dsp;
	u32 cm_shadow_freq_config1;
	u32 cm_mpu_mpu_clkctrl;

	/* cm1.dsp */
	u32 cm_dsp_clkstctrl;
	u32 cm_dsp_dsp_clkctrl;

	/* cm1.abe */
	u32 cm1_abe_clkstctrl;
	u32 cm1_abe_l4abe_clkctrl;
	u32 cm1_abe_aess_clkctrl;
	u32 cm1_abe_pdm_clkctrl;
	u32 cm1_abe_dmic_clkctrl;
	u32 cm1_abe_mcasp_clkctrl;
	u32 cm1_abe_mcbsp1_clkctrl;
	u32 cm1_abe_mcbsp2_clkctrl;
	u32 cm1_abe_mcbsp3_clkctrl;
	u32 cm1_abe_slimbus_clkctrl;
	u32 cm1_abe_timer5_clkctrl;
	u32 cm1_abe_timer6_clkctrl;
	u32 cm1_abe_timer7_clkctrl;
	u32 cm1_abe_timer8_clkctrl;
	u32 cm1_abe_wdt3_clkctrl;

	/* cm2.ckgen */
	u32 cm_clksel_mpu_m3_iss_root;
	u32 cm_clksel_usb_60mhz;
	u32 cm_scale_fclk;
	u32 cm_core_dvfs_perf1;
	u32 cm_core_dvfs_perf2;
	u32 cm_core_dvfs_perf3;
	u32 cm_core_dvfs_perf4;
	u32 cm_core_dvfs_current;
	u32 cm_iva_dvfs_perf_tesla;
	u32 cm_iva_dvfs_perf_ivahd;
	u32 cm_iva_dvfs_perf_abe;
	u32 cm_iva_dvfs_current;
	u32 cm_clkmode_dpll_per;
	u32 cm_idlest_dpll_per;
	u32 cm_autoidle_dpll_per;
	u32 cm_clksel_dpll_per;
	u32 cm_div_m2_dpll_per;
	u32 cm_div_m3_dpll_per;
	u32 cm_div_h11_dpll_per;
	u32 cm_div_h12_dpll_per;
	u32 cm_div_h13_dpll_per;
	u32 cm_div_h14_dpll_per;
	u32 cm_ssc_deltamstep_dpll_per;
	u32 cm_ssc_modfreqdiv_dpll_per;
	u32 cm_emu_override_dpll_per;
	u32 cm_clkmode_dpll_usb;
	u32 cm_idlest_dpll_usb;
	u32 cm_autoidle_dpll_usb;
	u32 cm_clksel_dpll_usb;
	u32 cm_div_m2_dpll_usb;
	u32 cm_ssc_deltamstep_dpll_usb;
	u32 cm_ssc_modfreqdiv_dpll_usb;
	u32 cm_clkdcoldo_dpll_usb;
	u32 cm_clkmode_dpll_pcie_ref;
	u32 cm_clkmode_apll_pcie;
	u32 cm_idlest_apll_pcie;
	u32 cm_div_m2_apll_pcie;
	u32 cm_clkvcoldo_apll_pcie;
	u32 cm_clkmode_dpll_unipro;
	u32 cm_idlest_dpll_unipro;
	u32 cm_autoidle_dpll_unipro;
	u32 cm_clksel_dpll_unipro;
	u32 cm_div_m2_dpll_unipro;
	u32 cm_ssc_deltamstep_dpll_unipro;
	u32 cm_ssc_modfreqdiv_dpll_unipro;

	/* cm2.core */
	u32 cm_coreaon_bandgap_clkctrl;
	u32 cm_coreaon_io_srcomp_clkctrl;
	u32 cm_l3_1_clkstctrl;
	u32 cm_l3_1_dynamicdep;
	u32 cm_l3_1_l3_1_clkctrl;
	u32 cm_l3_2_clkstctrl;
	u32 cm_l3_2_dynamicdep;
	u32 cm_l3_2_l3_2_clkctrl;
	u32 cm_l3_gpmc_clkctrl;
	u32 cm_l3_2_ocmc_ram_clkctrl;
	u32 cm_mpu_m3_clkstctrl;
	u32 cm_mpu_m3_staticdep;
	u32 cm_mpu_m3_dynamicdep;
	u32 cm_mpu_m3_mpu_m3_clkctrl;
	u32 cm_sdma_clkstctrl;
	u32 cm_sdma_staticdep;
	u32 cm_sdma_dynamicdep;
	u32 cm_sdma_sdma_clkctrl;
	u32 cm_memif_clkstctrl;
	u32 cm_memif_dmm_clkctrl;
	u32 cm_memif_emif_fw_clkctrl;
	u32 cm_memif_emif_1_clkctrl;
	u32 cm_memif_emif_2_clkctrl;
	u32 cm_memif_dll_clkctrl;
	u32 cm_memif_emif_h1_clkctrl;
	u32 cm_memif_emif_h2_clkctrl;
	u32 cm_memif_dll_h_clkctrl;
	u32 cm_c2c_clkstctrl;
	u32 cm_c2c_staticdep;
	u32 cm_c2c_dynamicdep;
	u32 cm_c2c_sad2d_clkctrl;
	u32 cm_c2c_modem_icr_clkctrl;
	u32 cm_c2c_sad2d_fw_clkctrl;
	u32 cm_l4cfg_clkstctrl;
	u32 cm_l4cfg_dynamicdep;
	u32 cm_l4cfg_l4_cfg_clkctrl;
	u32 cm_l4cfg_hw_sem_clkctrl;
	u32 cm_l4cfg_mailbox_clkctrl;
	u32 cm_l4cfg_sar_rom_clkctrl;
	u32 cm_l3instr_clkstctrl;
	u32 cm_l3instr_l3_3_clkctrl;
	u32 cm_l3instr_l3_instr_clkctrl;
	u32 cm_l3instr_intrconn_wp1_clkctrl;

	/* cm2.ivahd */
	u32 cm_ivahd_clkstctrl;
	u32 cm_ivahd_ivahd_clkctrl;
	u32 cm_ivahd_sl2_clkctrl;

	/* cm2.cam */
	u32 cm_cam_clkstctrl;
	u32 cm_cam_iss_clkctrl;
	u32 cm_cam_fdif_clkctrl;
	u32 cm_cam_vip1_clkctrl;
	u32 cm_cam_vip2_clkctrl;
	u32 cm_cam_vip3_clkctrl;
	u32 cm_cam_lvdsrx_clkctrl;
	u32 cm_cam_csi1_clkctrl;
	u32 cm_cam_csi2_clkctrl;

	/* cm2.dss */
	u32 cm_dss_clkstctrl;
	u32 cm_dss_dss_clkctrl;

	/* cm2.sgx */
	u32 cm_sgx_clkstctrl;
	u32 cm_sgx_sgx_clkctrl;

	/* cm2.l3init */
	u32 cm_l3init_clkstctrl;

	/* cm2.l3init */
	u32 cm_l3init_hsmmc1_clkctrl;
	u32 cm_l3init_hsmmc2_clkctrl;
	u32 cm_l3init_hsi_clkctrl;
	u32 cm_l3init_hsusbhost_clkctrl;
	u32 cm_l3init_hsusbotg_clkctrl;
	u32 cm_l3init_hsusbtll_clkctrl;
	u32 cm_l3init_p1500_clkctrl;
	u32 cm_l3init_fsusb_clkctrl;
	u32 cm_l3init_ocp2scp1_clkctrl;

	u32 prm_irqstatus_mpu_2;

	/* cm2.l4per */
	u32 cm_l4per_clkstctrl;
	u32 cm_l4per_dynamicdep;
	u32 cm_l4per_adc_clkctrl;
	u32 cm_l4per_gptimer10_clkctrl;
	u32 cm_l4per_gptimer11_clkctrl;
	u32 cm_l4per_gptimer2_clkctrl;
	u32 cm_l4per_gptimer3_clkctrl;
	u32 cm_l4per_gptimer4_clkctrl;
	u32 cm_l4per_gptimer9_clkctrl;
	u32 cm_l4per_elm_clkctrl;
	u32 cm_l4per_gpio2_clkctrl;
	u32 cm_l4per_gpio3_clkctrl;
	u32 cm_l4per_gpio4_clkctrl;
	u32 cm_l4per_gpio5_clkctrl;
	u32 cm_l4per_gpio6_clkctrl;
	u32 cm_l4per_hdq1w_clkctrl;
	u32 cm_l4per_hecc1_clkctrl;
	u32 cm_l4per_hecc2_clkctrl;
	u32 cm_l4per_i2c1_clkctrl;
	u32 cm_l4per_i2c2_clkctrl;
	u32 cm_l4per_i2c3_clkctrl;
	u32 cm_l4per_i2c4_clkctrl;
	u32 cm_l4per_l4per_clkctrl;
	u32 cm_l4per_mcasp2_clkctrl;
	u32 cm_l4per_mcasp3_clkctrl;
	u32 cm_l4per_mgate_clkctrl;
	u32 cm_l4per_mcspi1_clkctrl;
	u32 cm_l4per_mcspi2_clkctrl;
	u32 cm_l4per_mcspi3_clkctrl;
	u32 cm_l4per_mcspi4_clkctrl;
	u32 cm_l4per_gpio7_clkctrl;
	u32 cm_l4per_gpio8_clkctrl;
	u32 cm_l4per_mmcsd3_clkctrl;
	u32 cm_l4per_mmcsd4_clkctrl;
	u32 cm_l4per_msprohg_clkctrl;
	u32 cm_l4per_slimbus2_clkctrl;
	u32 cm_l4per_uart1_clkctrl;
	u32 cm_l4per_uart2_clkctrl;
	u32 cm_l4per_uart3_clkctrl;
	u32 cm_l4per_uart4_clkctrl;
	u32 cm_l4per_mmcsd5_clkctrl;
	u32 cm_l4per_i2c5_clkctrl;
	u32 cm_l4per_uart5_clkctrl;
	u32 cm_l4per_uart6_clkctrl;
	u32 cm_l4sec_clkstctrl;
	u32 cm_l4sec_staticdep;
	u32 cm_l4sec_dynamicdep;
	u32 cm_l4sec_aes1_clkctrl;
	u32 cm_l4sec_aes2_clkctrl;
	u32 cm_l4sec_des3des_clkctrl;
	u32 cm_l4sec_pkaeip29_clkctrl;
	u32 cm_l4sec_rng_clkctrl;
	u32 cm_l4sec_sha2md51_clkctrl;
	u32 cm_l4sec_cryptodma_clkctrl;

	/* l4 wkup regs */
	u32 cm_abe_pll_ref_clksel;
	u32 cm_sys_clksel;
	u32 cm_wkup_clkstctrl;
	u32 cm_wkup_l4wkup_clkctrl;
	u32 cm_wkup_wdtimer1_clkctrl;
	u32 cm_wkup_wdtimer2_clkctrl;
	u32 cm_wkup_gpio1_clkctrl;
	u32 cm_wkup_gptimer1_clkctrl;
	u32 cm_wkup_gptimer12_clkctrl;
	u32 cm_wkup_synctimer_clkctrl;
	u32 cm_wkup_usim_clkctrl;
	u32 cm_wkup_sarram_clkctrl;
	u32 cm_wkup_keyboard_clkctrl;
	u32 cm_wkup_rtc_clkctrl;
	u32 cm_wkup_bandgap_clkctrl;
	u32 cm_wkupaon_scrm_clkctrl;
	u32 cm_wkupaon_io_srcomp_clkctrl;
	u32 prm_rstctrl;
	u32 prm_rstst;
	u32 prm_rsttime;
	u32 prm_vc_val_bypass;
	u32 prm_vc_cfg_i2c_mode;
	u32 prm_vc_cfg_i2c_clk;
	u32 prm_sldo_core_setup;
	u32 prm_sldo_core_ctrl;
	u32 prm_sldo_mpu_setup;
	u32 prm_sldo_mpu_ctrl;
	u32 prm_sldo_mm_setup;
	u32 prm_sldo_mm_ctrl;
	u32 prm_abbldo_mpu_setup;
	u32 prm_abbldo_mpu_ctrl;

	u32 cm_div_m4_dpll_core;
	u32 cm_div_m5_dpll_core;
	u32 cm_div_m6_dpll_core;
	u32 cm_div_m7_dpll_core;
	u32 cm_div_m4_dpll_iva;
	u32 cm_div_m5_dpll_iva;
	u32 cm_div_m4_dpll_ddrphy;
	u32 cm_div_m5_dpll_ddrphy;
	u32 cm_div_m6_dpll_ddrphy;
	u32 cm_div_m4_dpll_per;
	u32 cm_div_m5_dpll_per;
	u32 cm_div_m6_dpll_per;
	u32 cm_div_m7_dpll_per;
	u32 cm_l3instr_intrconn_wp1_clkct;
	u32 cm_l3init_usbphy_clkctrl;
	u32 cm_l4per_mcbsp4_clkctrl;
	u32 prm_vc_cfg_channel;
};

struct omap_sys_ctrl_regs {
	u32 control_status;
	u32 control_std_fuse_opp_vdd_mpu_2;
	u32 control_core_mmr_lock1;
	u32 control_core_mmr_lock2;
	u32 control_core_mmr_lock3;
	u32 control_core_mmr_lock4;
	u32 control_core_mmr_lock5;
	u32 control_core_control_io1;
	u32 control_core_control_io2;
	u32 control_id_code;
	u32 control_std_fuse_opp_bgap;
	u32 control_ldosram_iva_voltage_ctrl;
	u32 control_ldosram_mpu_voltage_ctrl;
	u32 control_ldosram_core_voltage_ctrl;
	u32 control_padconf_core_base;
	u32 control_paconf_global;
	u32 control_paconf_mode;
	u32 control_smart1io_padconf_0;
	u32 control_smart1io_padconf_1;
	u32 control_smart1io_padconf_2;
	u32 control_smart2io_padconf_0;
	u32 control_smart2io_padconf_1;
	u32 control_smart2io_padconf_2;
	u32 control_smart3io_padconf_0;
	u32 control_smart3io_padconf_1;
	u32 control_pbias;
	u32 control_i2c_0;
	u32 control_camera_rx;
	u32 control_hdmi_tx_phy;
	u32 control_uniportm;
	u32 control_dsiphy;
	u32 control_mcbsplp;
	u32 control_usb2phycore;
	u32 control_hdmi_1;
	u32 control_hsi;
	u32 control_ddr3ch1_0;
	u32 control_ddr3ch2_0;
	u32 control_ddrch1_0;
	u32 control_ddrch1_1;
	u32 control_ddrch2_0;
	u32 control_ddrch2_1;
	u32 control_lpddr2ch1_0;
	u32 control_lpddr2ch1_1;
	u32 control_ddrio_0;
	u32 control_ddrio_1;
	u32 control_ddrio_2;
	u32 control_lpddr2io1_0;
	u32 control_lpddr2io1_1;
	u32 control_lpddr2io1_2;
	u32 control_lpddr2io1_3;
	u32 control_lpddr2io2_0;
	u32 control_lpddr2io2_1;
	u32 control_lpddr2io2_2;
	u32 control_lpddr2io2_3;
	u32 control_hyst_1;
	u32 control_usbb_hsic_control;
	u32 control_c2c;
	u32 control_core_control_spare_rw;
	u32 control_core_control_spare_r;
	u32 control_core_control_spare_r_c0;
	u32 control_srcomp_north_side;
	u32 control_srcomp_south_side;
	u32 control_srcomp_east_side;
	u32 control_srcomp_west_side;
	u32 control_srcomp_code_latch;
	u32 control_pbiaslite;
	u32 control_port_emif1_sdram_config;
	u32 control_port_emif1_lpddr2_nvm_config;
	u32 control_port_emif2_sdram_config;
	u32 control_emif1_sdram_config_ext;
	u32 control_emif2_sdram_config_ext;
	u32 control_wkup_ldovbb_mpu_voltage_ctrl;
	u32 control_smart1nopmio_padconf_0;
	u32 control_smart1nopmio_padconf_1;
	u32 control_padconf_mode;
	u32 control_xtal_oscillator;
	u32 control_i2c_2;
	u32 control_ckobuffer;
	u32 control_wkup_control_spare_rw;
	u32 control_wkup_control_spare_r;
	u32 control_wkup_control_spare_r_c0;
	u32 control_srcomp_east_side_wkup;
	u32 control_efuse_1;
	u32 control_efuse_2;
	u32 control_efuse_3;
	u32 control_efuse_4;
	u32 control_efuse_5;
	u32 control_efuse_6;
	u32 control_efuse_7;
	u32 control_efuse_8;
	u32 control_efuse_9;
	u32 control_efuse_10;
	u32 control_efuse_11;
	u32 control_efuse_12;
	u32 control_efuse_13;
	u32 control_padconf_wkup_base;
};

struct dpll_params {
	u32 m;
	u32 n;
	s8 m2;
	s8 m3;
	s8 m4_h11;
	s8 m5_h12;
	s8 m6_h13;
	s8 m7_h14;
	s8 h21;
	s8 h22;
	s8 h23;
	s8 h24;
};

struct dpll_regs {
	u32 cm_clkmode_dpll;
	u32 cm_idlest_dpll;
	u32 cm_autoidle_dpll;
	u32 cm_clksel_dpll;
	u32 cm_div_m2_dpll;
	u32 cm_div_m3_dpll;
	u32 cm_div_m4_h11_dpll;
	u32 cm_div_m5_h12_dpll;
	u32 cm_div_m6_h13_dpll;
	u32 cm_div_m7_h14_dpll;
	u32 reserved[2];
	u32 cm_div_h21_dpll;
	u32 cm_div_h22_dpll;
	u32 cm_div_h23_dpll;
	u32 cm_div_h24_dpll;
};

struct dplls {
	const struct dpll_params *mpu;
	const struct dpll_params *core;
	const struct dpll_params *per;
	const struct dpll_params *abe;
	const struct dpll_params *iva;
	const struct dpll_params *usb;
	const struct dpll_params *ddr;
};

struct pmic_data {
	u32 base_offset;
	u32 step;
	u32 start_code;
	unsigned gpio;
	int gpio_en;
};

struct volts {
	u32 value;
	u32 addr;
	struct pmic_data *pmic;
};

struct vcores_data {
	struct volts mpu;
	struct volts core;
	struct volts mm;
};

extern struct prcm_regs const **prcm;
extern struct prcm_regs const omap5_es1_prcm;
extern struct prcm_regs const omap5_es2_prcm;
extern struct prcm_regs const omap4_prcm;
extern struct prcm_regs const dra7xx_prcm;
extern struct dplls const **dplls_data;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
extern struct omap_sys_ctrl_regs const omap4_ctrl;
extern struct omap_sys_ctrl_regs const omap5_ctrl;
extern struct omap_sys_ctrl_regs const dra7xx_ctrl;

void hw_data_init(void);

const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
const struct dpll_params *get_core_dpll_params(struct dplls const *);
const struct dpll_params *get_per_dpll_params(struct dplls const *);
const struct dpll_params *get_iva_dpll_params(struct dplls const *);
const struct dpll_params *get_usb_dpll_params(struct dplls const *);
const struct dpll_params *get_abe_dpll_params(struct dplls const *);

void do_enable_clocks(u32 const *clk_domains,
		      u32 const *clk_modules_hw_auto,
		      u32 const *clk_modules_explicit_en,
		      u8 wait_for_enable);

void setup_post_dividers(u32 const base,
			const struct dpll_params *params);
u32 omap_ddr_clk(void);
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
void enable_non_essential_clocks(void);
void scale_vcores(struct vcores_data const *);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
	       u32 txdone, u32 txdone_mask, u32 opp);
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);

/* Max value for DPLL multiplier M */
#define OMAP_DPLL_MAX_N	127

/* HW Init Context */
#define OMAP_INIT_CONTEXT_SPL			0
#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1
#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3

/* ABB */
#define OMAP_ABB_NOMINAL_OPP		0
#define OMAP_ABB_FAST_OPP		1
#define OMAP_ABB_SLOW_OPP		3
#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK		(0x1 << 0)
#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK		(0x1 << 1)
#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK		(0x1 << 2)
#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK		(0x1 << 6)
#define OMAP_ABB_SETUP_SR2EN_MASK			(0x1 << 0)
#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK		(0x1 << 2)
#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK		(0x1 << 1)
#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK		(0xff << 8)

static inline u32 omap_revision(void)
{
	extern u32 *const omap_si_rev;
	return *omap_si_rev;
}
#endif

/*
 * silicon revisions.
 * Moving this to common, so that most of code can be moved to common,
 * directories.
 */

/* omap4 */
#define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
#define OMAP4430_ES1_0	0x44300100
#define OMAP4430_ES2_0	0x44300200
#define OMAP4430_ES2_1	0x44300210
#define OMAP4430_ES2_2	0x44300220
#define OMAP4430_ES2_3	0x44300230
#define OMAP4460_ES1_0	0x44600100
#define OMAP4460_ES1_1	0x44600110

/* omap5 */
#define OMAP5430_SILICON_ID_INVALID	0
#define OMAP5430_ES1_0	0x54300100
#define OMAP5432_ES1_0	0x54320100
#define OMAP5430_ES2_0  0x54300200
#define OMAP5432_ES2_0  0x54320200

/* DRA7XX */
#define DRA752_ES1_0	0x07520100

/*
 * SRAM scratch space entries
 */
#define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
#define OMAP_SRAM_SCRATCH_OMAP_REV	SRAM_SCRATCH_SPACE_ADDR
#define OMAP_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
#define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
#define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
#define OMAP_SRAM_SCRATCH_BOOT_PARAMS	(SRAM_SCRATCH_SPACE_ADDR + 0x24)
#define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x28)

#endif /* _OMAP_COMMON_H_ */
Commit	Line	Data
d2f18c27 A	1	/*
	2	* (C) Copyright 2010
	3	* Texas Instruments, <www.ti.com>
	4	*
	5	* Aneesh V <aneesh@ti.com>
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25	#ifndef _OMAP_COMMON_H_
	26	#define _OMAP_COMMON_H_
	27
4a0eb757 S	28	#ifndef __ASSEMBLY__
4a0eb757 S	29
01b753ff S	30	#include <common.h>
01b753ff S	31
ea8eff1f	32	#define NUM_SYS_CLKS 8
ee9447bf	33
01b753ff S	34	struct prcm_regs {
	35	/* cm1.ckgen */
	36	u32 cm_clksel_core;
	37	u32 cm_clksel_abe;
	38	u32 cm_dll_ctrl;
	39	u32 cm_clkmode_dpll_core;
	40	u32 cm_idlest_dpll_core;
	41	u32 cm_autoidle_dpll_core;
	42	u32 cm_clksel_dpll_core;
	43	u32 cm_div_m2_dpll_core;
	44	u32 cm_div_m3_dpll_core;
	45	u32 cm_div_h11_dpll_core;
	46	u32 cm_div_h12_dpll_core;
	47	u32 cm_div_h13_dpll_core;
	48	u32 cm_div_h14_dpll_core;
afc2f9dc S	49	u32 cm_div_h21_dpll_core;
afc2f9dc S	50	u32 cm_div_h24_dpll_core;
01b753ff S	51	u32 cm_ssc_deltamstep_dpll_core;
	52	u32 cm_ssc_modfreqdiv_dpll_core;
	53	u32 cm_emu_override_dpll_core;
	54	u32 cm_div_h22_dpllcore;
	55	u32 cm_div_h23_dpll_core;
	56	u32 cm_clkmode_dpll_mpu;
	57	u32 cm_idlest_dpll_mpu;
	58	u32 cm_autoidle_dpll_mpu;
	59	u32 cm_clksel_dpll_mpu;
	60	u32 cm_div_m2_dpll_mpu;
	61	u32 cm_ssc_deltamstep_dpll_mpu;
	62	u32 cm_ssc_modfreqdiv_dpll_mpu;
	63	u32 cm_bypclk_dpll_mpu;
	64	u32 cm_clkmode_dpll_iva;
	65	u32 cm_idlest_dpll_iva;
	66	u32 cm_autoidle_dpll_iva;
	67	u32 cm_clksel_dpll_iva;
	68	u32 cm_div_h11_dpll_iva;
	69	u32 cm_div_h12_dpll_iva;
	70	u32 cm_ssc_deltamstep_dpll_iva;
	71	u32 cm_ssc_modfreqdiv_dpll_iva;
	72	u32 cm_bypclk_dpll_iva;
	73	u32 cm_clkmode_dpll_abe;
	74	u32 cm_idlest_dpll_abe;
	75	u32 cm_autoidle_dpll_abe;
	76	u32 cm_clksel_dpll_abe;
	77	u32 cm_div_m2_dpll_abe;
	78	u32 cm_div_m3_dpll_abe;
	79	u32 cm_ssc_deltamstep_dpll_abe;
	80	u32 cm_ssc_modfreqdiv_dpll_abe;
	81	u32 cm_clkmode_dpll_ddrphy;
	82	u32 cm_idlest_dpll_ddrphy;
	83	u32 cm_autoidle_dpll_ddrphy;
	84	u32 cm_clksel_dpll_ddrphy;
	85	u32 cm_div_m2_dpll_ddrphy;
	86	u32 cm_div_h11_dpll_ddrphy;
	87	u32 cm_div_h12_dpll_ddrphy;
	88	u32 cm_div_h13_dpll_ddrphy;
	89	u32 cm_ssc_deltamstep_dpll_ddrphy;
d4e4129c	90	u32 cm_clkmode_dpll_dsp;
01b753ff S	91	u32 cm_shadow_freq_config1;
	92	u32 cm_mpu_mpu_clkctrl;
	93
	94	/* cm1.dsp */
	95	u32 cm_dsp_clkstctrl;
	96	u32 cm_dsp_dsp_clkctrl;
	97
	98	/* cm1.abe */
	99	u32 cm1_abe_clkstctrl;
	100	u32 cm1_abe_l4abe_clkctrl;
	101	u32 cm1_abe_aess_clkctrl;
	102	u32 cm1_abe_pdm_clkctrl;
	103	u32 cm1_abe_dmic_clkctrl;
	104	u32 cm1_abe_mcasp_clkctrl;
	105	u32 cm1_abe_mcbsp1_clkctrl;
	106	u32 cm1_abe_mcbsp2_clkctrl;
	107	u32 cm1_abe_mcbsp3_clkctrl;
	108	u32 cm1_abe_slimbus_clkctrl;
	109	u32 cm1_abe_timer5_clkctrl;
	110	u32 cm1_abe_timer6_clkctrl;
	111	u32 cm1_abe_timer7_clkctrl;
	112	u32 cm1_abe_timer8_clkctrl;
	113	u32 cm1_abe_wdt3_clkctrl;
	114
	115	/* cm2.ckgen */
	116	u32 cm_clksel_mpu_m3_iss_root;
	117	u32 cm_clksel_usb_60mhz;
	118	u32 cm_scale_fclk;
	119	u32 cm_core_dvfs_perf1;
	120	u32 cm_core_dvfs_perf2;
	121	u32 cm_core_dvfs_perf3;
	122	u32 cm_core_dvfs_perf4;
	123	u32 cm_core_dvfs_current;
	124	u32 cm_iva_dvfs_perf_tesla;
	125	u32 cm_iva_dvfs_perf_ivahd;
	126	u32 cm_iva_dvfs_perf_abe;
	127	u32 cm_iva_dvfs_current;
	128	u32 cm_clkmode_dpll_per;
	129	u32 cm_idlest_dpll_per;
	130	u32 cm_autoidle_dpll_per;
	131	u32 cm_clksel_dpll_per;
	132	u32 cm_div_m2_dpll_per;
	133	u32 cm_div_m3_dpll_per;
	134	u32 cm_div_h11_dpll_per;
	135	u32 cm_div_h12_dpll_per;
afc2f9dc	136	u32 cm_div_h13_dpll_per;
01b753ff S	137	u32 cm_div_h14_dpll_per;
	138	u32 cm_ssc_deltamstep_dpll_per;
	139	u32 cm_ssc_modfreqdiv_dpll_per;
	140	u32 cm_emu_override_dpll_per;
	141	u32 cm_clkmode_dpll_usb;
	142	u32 cm_idlest_dpll_usb;
	143	u32 cm_autoidle_dpll_usb;
	144	u32 cm_clksel_dpll_usb;
	145	u32 cm_div_m2_dpll_usb;
	146	u32 cm_ssc_deltamstep_dpll_usb;
	147	u32 cm_ssc_modfreqdiv_dpll_usb;
	148	u32 cm_clkdcoldo_dpll_usb;
d4e4129c LV	149	u32 cm_clkmode_dpll_pcie_ref;
	150	u32 cm_clkmode_apll_pcie;
	151	u32 cm_idlest_apll_pcie;
	152	u32 cm_div_m2_apll_pcie;
	153	u32 cm_clkvcoldo_apll_pcie;
01b753ff S	154	u32 cm_clkmode_dpll_unipro;
	155	u32 cm_idlest_dpll_unipro;
	156	u32 cm_autoidle_dpll_unipro;
	157	u32 cm_clksel_dpll_unipro;
	158	u32 cm_div_m2_dpll_unipro;
	159	u32 cm_ssc_deltamstep_dpll_unipro;
	160	u32 cm_ssc_modfreqdiv_dpll_unipro;
	161
	162	/* cm2.core */
	163	u32 cm_coreaon_bandgap_clkctrl;
d4d986ee	164	u32 cm_coreaon_io_srcomp_clkctrl;
01b753ff S	165	u32 cm_l3_1_clkstctrl;
	166	u32 cm_l3_1_dynamicdep;
	167	u32 cm_l3_1_l3_1_clkctrl;
	168	u32 cm_l3_2_clkstctrl;
	169	u32 cm_l3_2_dynamicdep;
	170	u32 cm_l3_2_l3_2_clkctrl;
d4e4129c	171	u32 cm_l3_gpmc_clkctrl;
01b753ff S	172	u32 cm_l3_2_ocmc_ram_clkctrl;
	173	u32 cm_mpu_m3_clkstctrl;
	174	u32 cm_mpu_m3_staticdep;
	175	u32 cm_mpu_m3_dynamicdep;
	176	u32 cm_mpu_m3_mpu_m3_clkctrl;
	177	u32 cm_sdma_clkstctrl;
	178	u32 cm_sdma_staticdep;
	179	u32 cm_sdma_dynamicdep;
	180	u32 cm_sdma_sdma_clkctrl;
	181	u32 cm_memif_clkstctrl;
	182	u32 cm_memif_dmm_clkctrl;
	183	u32 cm_memif_emif_fw_clkctrl;
	184	u32 cm_memif_emif_1_clkctrl;
	185	u32 cm_memif_emif_2_clkctrl;
	186	u32 cm_memif_dll_clkctrl;
	187	u32 cm_memif_emif_h1_clkctrl;
	188	u32 cm_memif_emif_h2_clkctrl;
	189	u32 cm_memif_dll_h_clkctrl;
	190	u32 cm_c2c_clkstctrl;
	191	u32 cm_c2c_staticdep;
	192	u32 cm_c2c_dynamicdep;
	193	u32 cm_c2c_sad2d_clkctrl;
	194	u32 cm_c2c_modem_icr_clkctrl;
	195	u32 cm_c2c_sad2d_fw_clkctrl;
	196	u32 cm_l4cfg_clkstctrl;
	197	u32 cm_l4cfg_dynamicdep;
	198	u32 cm_l4cfg_l4_cfg_clkctrl;
	199	u32 cm_l4cfg_hw_sem_clkctrl;
	200	u32 cm_l4cfg_mailbox_clkctrl;
	201	u32 cm_l4cfg_sar_rom_clkctrl;
	202	u32 cm_l3instr_clkstctrl;
	203	u32 cm_l3instr_l3_3_clkctrl;
	204	u32 cm_l3instr_l3_instr_clkctrl;
	205	u32 cm_l3instr_intrconn_wp1_clkctrl;
	206
	207	/* cm2.ivahd */
	208	u32 cm_ivahd_clkstctrl;
	209	u32 cm_ivahd_ivahd_clkctrl;
	210	u32 cm_ivahd_sl2_clkctrl;
	211
	212	/* cm2.cam */
	213	u32 cm_cam_clkstctrl;
	214	u32 cm_cam_iss_clkctrl;
	215	u32 cm_cam_fdif_clkctrl;
d4e4129c LV	216	u32 cm_cam_vip1_clkctrl;
	217	u32 cm_cam_vip2_clkctrl;
	218	u32 cm_cam_vip3_clkctrl;
	219	u32 cm_cam_lvdsrx_clkctrl;
	220	u32 cm_cam_csi1_clkctrl;
	221	u32 cm_cam_csi2_clkctrl;
01b753ff S	222
	223	/* cm2.dss */
	224	u32 cm_dss_clkstctrl;
	225	u32 cm_dss_dss_clkctrl;
	226
	227	/* cm2.sgx */
	228	u32 cm_sgx_clkstctrl;
	229	u32 cm_sgx_sgx_clkctrl;
	230
	231	/* cm2.l3init */
	232	u32 cm_l3init_clkstctrl;
	233
	234	/* cm2.l3init */
	235	u32 cm_l3init_hsmmc1_clkctrl;
	236	u32 cm_l3init_hsmmc2_clkctrl;
	237	u32 cm_l3init_hsi_clkctrl;
	238	u32 cm_l3init_hsusbhost_clkctrl;
	239	u32 cm_l3init_hsusbotg_clkctrl;
	240	u32 cm_l3init_hsusbtll_clkctrl;
	241	u32 cm_l3init_p1500_clkctrl;
	242	u32 cm_l3init_fsusb_clkctrl;
	243	u32 cm_l3init_ocp2scp1_clkctrl;
	244
4d0df9c1 AT	245	u32 prm_irqstatus_mpu_2;
4d0df9c1 AT	246
01b753ff S	247	/* cm2.l4per */
	248	u32 cm_l4per_clkstctrl;
	249	u32 cm_l4per_dynamicdep;
	250	u32 cm_l4per_adc_clkctrl;
	251	u32 cm_l4per_gptimer10_clkctrl;
	252	u32 cm_l4per_gptimer11_clkctrl;
	253	u32 cm_l4per_gptimer2_clkctrl;
	254	u32 cm_l4per_gptimer3_clkctrl;
	255	u32 cm_l4per_gptimer4_clkctrl;
	256	u32 cm_l4per_gptimer9_clkctrl;
	257	u32 cm_l4per_elm_clkctrl;
	258	u32 cm_l4per_gpio2_clkctrl;
	259	u32 cm_l4per_gpio3_clkctrl;
	260	u32 cm_l4per_gpio4_clkctrl;
	261	u32 cm_l4per_gpio5_clkctrl;
	262	u32 cm_l4per_gpio6_clkctrl;
	263	u32 cm_l4per_hdq1w_clkctrl;
	264	u32 cm_l4per_hecc1_clkctrl;
	265	u32 cm_l4per_hecc2_clkctrl;
	266	u32 cm_l4per_i2c1_clkctrl;
	267	u32 cm_l4per_i2c2_clkctrl;
	268	u32 cm_l4per_i2c3_clkctrl;
	269	u32 cm_l4per_i2c4_clkctrl;
	270	u32 cm_l4per_l4per_clkctrl;
	271	u32 cm_l4per_mcasp2_clkctrl;
	272	u32 cm_l4per_mcasp3_clkctrl;
	273	u32 cm_l4per_mgate_clkctrl;
	274	u32 cm_l4per_mcspi1_clkctrl;
	275	u32 cm_l4per_mcspi2_clkctrl;
	276	u32 cm_l4per_mcspi3_clkctrl;
	277	u32 cm_l4per_mcspi4_clkctrl;
	278	u32 cm_l4per_gpio7_clkctrl;
	279	u32 cm_l4per_gpio8_clkctrl;
	280	u32 cm_l4per_mmcsd3_clkctrl;
	281	u32 cm_l4per_mmcsd4_clkctrl;
	282	u32 cm_l4per_msprohg_clkctrl;
	283	u32 cm_l4per_slimbus2_clkctrl;
	284	u32 cm_l4per_uart1_clkctrl;
	285	u32 cm_l4per_uart2_clkctrl;
	286	u32 cm_l4per_uart3_clkctrl;
	287	u32 cm_l4per_uart4_clkctrl;
	288	u32 cm_l4per_mmcsd5_clkctrl;
	289	u32 cm_l4per_i2c5_clkctrl;
	290	u32 cm_l4per_uart5_clkctrl;
	291	u32 cm_l4per_uart6_clkctrl;
	292	u32 cm_l4sec_clkstctrl;
	293	u32 cm_l4sec_staticdep;
	294	u32 cm_l4sec_dynamicdep;
	295	u32 cm_l4sec_aes1_clkctrl;
	296	u32 cm_l4sec_aes2_clkctrl;
	297	u32 cm_l4sec_des3des_clkctrl;
	298	u32 cm_l4sec_pkaeip29_clkctrl;
	299	u32 cm_l4sec_rng_clkctrl;
	300	u32 cm_l4sec_sha2md51_clkctrl;
	301	u32 cm_l4sec_cryptodma_clkctrl;
	302
	303	/* l4 wkup regs */
	304	u32 cm_abe_pll_ref_clksel;
	305	u32 cm_sys_clksel;
	306	u32 cm_wkup_clkstctrl;
	307	u32 cm_wkup_l4wkup_clkctrl;
	308	u32 cm_wkup_wdtimer1_clkctrl;
	309	u32 cm_wkup_wdtimer2_clkctrl;
	310	u32 cm_wkup_gpio1_clkctrl;
311	u32 cm_wkup_gptimer1_clkctrl;
312	u32 cm_wkup_gptimer12_clkctrl;
313	u32 cm_wkup_synctimer_clkctrl;
314	u32 cm_wkup_usim_clkctrl;
315	u32 cm_wkup_sarram_clkctrl;
316	u32 cm_wkup_keyboard_clkctrl;
317	u32 cm_wkup_rtc_clkctrl;
318	u32 cm_wkup_bandgap_clkctrl;
319	u32 cm_wkupaon_scrm_clkctrl;
d4d986ee	320	u32 cm_wkupaon_io_srcomp_clkctrl;
d4e4129c LV	321	u32 prm_rstctrl;
d4e4129c LV	322	u32 prm_rstst;
0b1b60c7	323	u32 prm_rsttime;
01b753ff S	324	u32 prm_vc_val_bypass;
	325	u32 prm_vc_cfg_i2c_mode;
	326	u32 prm_vc_cfg_i2c_clk;
	327	u32 prm_sldo_core_setup;
	328	u32 prm_sldo_core_ctrl;
	329	u32 prm_sldo_mpu_setup;
	330	u32 prm_sldo_mpu_ctrl;
	331	u32 prm_sldo_mm_setup;
	332	u32 prm_sldo_mm_ctrl;
4d0df9c1 AT	333	u32 prm_abbldo_mpu_setup;
4d0df9c1 AT	334	u32 prm_abbldo_mpu_ctrl;
01b753ff S	335
	336	u32 cm_div_m4_dpll_core;
	337	u32 cm_div_m5_dpll_core;
	338	u32 cm_div_m6_dpll_core;
	339	u32 cm_div_m7_dpll_core;
	340	u32 cm_div_m4_dpll_iva;
	341	u32 cm_div_m5_dpll_iva;
	342	u32 cm_div_m4_dpll_ddrphy;
	343	u32 cm_div_m5_dpll_ddrphy;
	344	u32 cm_div_m6_dpll_ddrphy;
	345	u32 cm_div_m4_dpll_per;
	346	u32 cm_div_m5_dpll_per;
	347	u32 cm_div_m6_dpll_per;
	348	u32 cm_div_m7_dpll_per;
	349	u32 cm_l3instr_intrconn_wp1_clkct;
	350	u32 cm_l3init_usbphy_clkctrl;
	351	u32 cm_l4per_mcbsp4_clkctrl;
	352	u32 prm_vc_cfg_channel;
	353	};
	354
c43c8339 LV	355	struct omap_sys_ctrl_regs {
c43c8339 LV	356	u32 control_status;
4d0df9c1	357	u32 control_std_fuse_opp_vdd_mpu_2;
8b12f177 LV	358	u32 control_core_mmr_lock1;
	359	u32 control_core_mmr_lock2;
	360	u32 control_core_mmr_lock3;
	361	u32 control_core_mmr_lock4;
	362	u32 control_core_mmr_lock5;
	363	u32 control_core_control_io1;
	364	u32 control_core_control_io2;
c43c8339 LV	365	u32 control_id_code;
	366	u32 control_std_fuse_opp_bgap;
	367	u32 control_ldosram_iva_voltage_ctrl;
	368	u32 control_ldosram_mpu_voltage_ctrl;
	369	u32 control_ldosram_core_voltage_ctrl;
8b12f177	370	u32 control_padconf_core_base;
c43c8339 LV	371	u32 control_paconf_global;
	372	u32 control_paconf_mode;
	373	u32 control_smart1io_padconf_0;
	374	u32 control_smart1io_padconf_1;
	375	u32 control_smart1io_padconf_2;
	376	u32 control_smart2io_padconf_0;
	377	u32 control_smart2io_padconf_1;
	378	u32 control_smart2io_padconf_2;
	379	u32 control_smart3io_padconf_0;
	380	u32 control_smart3io_padconf_1;
	381	u32 control_pbias;
	382	u32 control_i2c_0;
	383	u32 control_camera_rx;
	384	u32 control_hdmi_tx_phy;
	385	u32 control_uniportm;
	386	u32 control_dsiphy;
	387	u32 control_mcbsplp;
	388	u32 control_usb2phycore;
	389	u32 control_hdmi_1;
	390	u32 control_hsi;
	391	u32 control_ddr3ch1_0;
	392	u32 control_ddr3ch2_0;
	393	u32 control_ddrch1_0;
	394	u32 control_ddrch1_1;
	395	u32 control_ddrch2_0;
	396	u32 control_ddrch2_1;
	397	u32 control_lpddr2ch1_0;
	398	u32 control_lpddr2ch1_1;
	399	u32 control_ddrio_0;
	400	u32 control_ddrio_1;
	401	u32 control_ddrio_2;
	402	u32 control_lpddr2io1_0;
	403	u32 control_lpddr2io1_1;
	404	u32 control_lpddr2io1_2;
	405	u32 control_lpddr2io1_3;
	406	u32 control_lpddr2io2_0;
	407	u32 control_lpddr2io2_1;
	408	u32 control_lpddr2io2_2;
	409	u32 control_lpddr2io2_3;
	410	u32 control_hyst_1;
	411	u32 control_usbb_hsic_control;
	412	u32 control_c2c;
	413	u32 control_core_control_spare_rw;
	414	u32 control_core_control_spare_r;
	415	u32 control_core_control_spare_r_c0;
	416	u32 control_srcomp_north_side;
	417	u32 control_srcomp_south_side;
	418	u32 control_srcomp_east_side;
	419	u32 control_srcomp_west_side;
	420	u32 control_srcomp_code_latch;
	421	u32 control_pbiaslite;
	422	u32 control_port_emif1_sdram_config;
	423	u32 control_port_emif1_lpddr2_nvm_config;
	424	u32 control_port_emif2_sdram_config;
	425	u32 control_emif1_sdram_config_ext;
	426	u32 control_emif2_sdram_config_ext;
4d0df9c1	427	u32 control_wkup_ldovbb_mpu_voltage_ctrl;
c43c8339 LV	428	u32 control_smart1nopmio_padconf_0;
	429	u32 control_smart1nopmio_padconf_1;
	430	u32 control_padconf_mode;
	431	u32 control_xtal_oscillator;
	432	u32 control_i2c_2;
	433	u32 control_ckobuffer;
	434	u32 control_wkup_control_spare_rw;
	435	u32 control_wkup_control_spare_r;
	436	u32 control_wkup_control_spare_r_c0;
	437	u32 control_srcomp_east_side_wkup;
	438	u32 control_efuse_1;
	439	u32 control_efuse_2;
	440	u32 control_efuse_3;
	441	u32 control_efuse_4;
	442	u32 control_efuse_5;
	443	u32 control_efuse_6;
	444	u32 control_efuse_7;
	445	u32 control_efuse_8;
	446	u32 control_efuse_9;
	447	u32 control_efuse_10;
	448	u32 control_efuse_11;
	449	u32 control_efuse_12;
	450	u32 control_efuse_13;
8b12f177	451	u32 control_padconf_wkup_base;
c43c8339 LV	452	};
c43c8339 LV	453
ee9447bf S	454	struct dpll_params {
	455	u32 m;
	456	u32 n;
	457	s8 m2;
	458	s8 m3;
	459	s8 m4_h11;
	460	s8 m5_h12;
	461	s8 m6_h13;
	462	s8 m7_h14;
47abc3df	463	s8 h21;
ee9447bf S	464	s8 h22;
ee9447bf S	465	s8 h23;
47abc3df	466	s8 h24;
ee9447bf S	467	};
	468
	469	struct dpll_regs {
	470	u32 cm_clkmode_dpll;
	471	u32 cm_idlest_dpll;
	472	u32 cm_autoidle_dpll;
	473	u32 cm_clksel_dpll;
	474	u32 cm_div_m2_dpll;
	475	u32 cm_div_m3_dpll;
	476	u32 cm_div_m4_h11_dpll;
	477	u32 cm_div_m5_h12_dpll;
	478	u32 cm_div_m6_h13_dpll;
	479	u32 cm_div_m7_h14_dpll;
47abc3df S	480	u32 reserved[2];
47abc3df S	481	u32 cm_div_h21_dpll;
ee9447bf S	482	u32 cm_div_h22_dpll;
ee9447bf S	483	u32 cm_div_h23_dpll;
47abc3df	484	u32 cm_div_h24_dpll;
ee9447bf S	485	};
	486
	487	struct dplls {
	488	const struct dpll_params *mpu;
	489	const struct dpll_params *core;
	490	const struct dpll_params *per;
	491	const struct dpll_params *abe;
	492	const struct dpll_params *iva;
	493	const struct dpll_params *usb;
ea8eff1f	494	const struct dpll_params *ddr;
ee9447bf S	495	};
ee9447bf S	496
3fcdd4a5 S	497	struct pmic_data {
	498	u32 base_offset;
	499	u32 step;
	500	u32 start_code;
	501	unsigned gpio;
	502	int gpio_en;
	503	};
	504
	505	struct volts {
	506	u32 value;
	507	u32 addr;
	508	struct pmic_data *pmic;
	509	};
	510
	511	struct vcores_data {
	512	struct volts mpu;
	513	struct volts core;
	514	struct volts mm;
	515	};
	516
01b753ff S	517	extern struct prcm_regs const **prcm;
01b753ff S	518	extern struct prcm_regs const omap5_es1_prcm;
afc2f9dc	519	extern struct prcm_regs const omap5_es2_prcm;
01b753ff	520	extern struct prcm_regs const omap4_prcm;
d4e4129c	521	extern struct prcm_regs const dra7xx_prcm;
ee9447bf	522	extern struct dplls const **dplls_data;
3fcdd4a5	523	extern struct vcores_data const **omap_vcores;
ee9447bf	524	extern const u32 sys_clk_array[8];
c43c8339 LV	525	extern struct omap_sys_ctrl_regs const **ctrl;
	526	extern struct omap_sys_ctrl_regs const omap4_ctrl;
	527	extern struct omap_sys_ctrl_regs const omap5_ctrl;
8b12f177	528	extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
01b753ff S	529
01b753ff S	530	void hw_data_init(void);
ee9447bf S	531
	532	const struct dpll_params get_mpu_dpll_params(struct dplls const );
	533	const struct dpll_params get_core_dpll_params(struct dplls const );
	534	const struct dpll_params get_per_dpll_params(struct dplls const );
	535	const struct dpll_params get_iva_dpll_params(struct dplls const );
	536	const struct dpll_params get_usb_dpll_params(struct dplls const );
	537	const struct dpll_params get_abe_dpll_params(struct dplls const );
	538
	539	void do_enable_clocks(u32 const *clk_domains,
	540	u32 const *clk_modules_hw_auto,
	541	u32 const *clk_modules_explicit_en,
	542	u8 wait_for_enable);
	543
	544	void setup_post_dividers(u32 const base,
	545	const struct dpll_params *params);
	546	u32 omap_ddr_clk(void);
	547	u32 get_sys_clk_index(void);
	548	void enable_basic_clocks(void);
	549	void enable_basic_uboot_clocks(void);
	550	void enable_non_essential_clocks(void);
3fcdd4a5 S	551	void scale_vcores(struct vcores_data const *);
	552	u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
	553	void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
4d0df9c1 AT	554	void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
	555	u32 txdone, u32 txdone_mask, u32 opp);
	556	s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
ee9447bf	557
3776801d A	558	/* Max value for DPLL multiplier M */
	559	#define OMAP_DPLL_MAX_N 127
	560
d2f18c27 A	561	/* HW Init Context */
	562	#define OMAP_INIT_CONTEXT_SPL 0
	563	#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1
	564	#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2
	565	#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3
	566
4d0df9c1 AT	567	/* ABB */
	568	#define OMAP_ABB_NOMINAL_OPP 0
	569	#define OMAP_ABB_FAST_OPP 1
	570	#define OMAP_ABB_SLOW_OPP 3
	571	#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK (0x1 << 0)
	572	#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK (0x1 << 1)
	573	#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK (0x1 << 2)
	574	#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK (0x1 << 6)
	575	#define OMAP_ABB_SETUP_SR2EN_MASK (0x1 << 0)
	576	#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK (0x1 << 2)
	577	#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK (0x1 << 1)
	578	#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK (0xff << 8)
	579
087189fb S	580	static inline u32 omap_revision(void)
	581	{
	582	extern u32 *const omap_si_rev;
	583	return *omap_si_rev;
	584	}
4a0eb757	585	#endif
087189fb	586
508a58fa S	587	/*
	588	* silicon revisions.
	589	* Moving this to common, so that most of code can be moved to common,
	590	* directories.
	591	*/
	592
	593	/* omap4 */
	594	#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
	595	#define OMAP4430_ES1_0 0x44300100
	596	#define OMAP4430_ES2_0 0x44300200
	597	#define OMAP4430_ES2_1 0x44300210
	598	#define OMAP4430_ES2_2 0x44300220
	599	#define OMAP4430_ES2_3 0x44300230
	600	#define OMAP4460_ES1_0 0x44600100
9404758e	601	#define OMAP4460_ES1_1 0x44600110
508a58fa S	602
	603	/* omap5 */
	604	#define OMAP5430_SILICON_ID_INVALID 0
	605	#define OMAP5430_ES1_0 0x54300100
0a0bf7b2	606	#define OMAP5432_ES1_0 0x54320100
eed7c0f7 S	607	#define OMAP5430_ES2_0 0x54300200
eed7c0f7 S	608	#define OMAP5432_ES2_0 0x54320200
de62688b LV	609
	610	/* DRA7XX */
	611	#define DRA752_ES1_0 0x07520100
f92f2277 S	612
	613	/*
	614	* SRAM scratch space entries
	615	*/
	616	#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
	617	#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR
	618	#define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
	619	#define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
	620	#define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
	621	#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
	622	#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
	623	#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
	624	#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
fda06812 S	625	#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
	626	#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28)
	627
d2f18c27	628	#endif /* _OMAP_COMMON_H_ */