]>
Commit | Line | Data |
---|---|---|
d2f18c27 A |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * | |
5 | * Aneesh V <aneesh@ti.com> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | #ifndef _OMAP_COMMON_H_ | |
26 | #define _OMAP_COMMON_H_ | |
27 | ||
01b753ff S |
28 | #include <common.h> |
29 | ||
ea8eff1f | 30 | #define NUM_SYS_CLKS 8 |
ee9447bf | 31 | |
01b753ff S |
32 | struct prcm_regs { |
33 | /* cm1.ckgen */ | |
34 | u32 cm_clksel_core; | |
35 | u32 cm_clksel_abe; | |
36 | u32 cm_dll_ctrl; | |
37 | u32 cm_clkmode_dpll_core; | |
38 | u32 cm_idlest_dpll_core; | |
39 | u32 cm_autoidle_dpll_core; | |
40 | u32 cm_clksel_dpll_core; | |
41 | u32 cm_div_m2_dpll_core; | |
42 | u32 cm_div_m3_dpll_core; | |
43 | u32 cm_div_h11_dpll_core; | |
44 | u32 cm_div_h12_dpll_core; | |
45 | u32 cm_div_h13_dpll_core; | |
46 | u32 cm_div_h14_dpll_core; | |
afc2f9dc S |
47 | u32 cm_div_h21_dpll_core; |
48 | u32 cm_div_h24_dpll_core; | |
01b753ff S |
49 | u32 cm_ssc_deltamstep_dpll_core; |
50 | u32 cm_ssc_modfreqdiv_dpll_core; | |
51 | u32 cm_emu_override_dpll_core; | |
52 | u32 cm_div_h22_dpllcore; | |
53 | u32 cm_div_h23_dpll_core; | |
54 | u32 cm_clkmode_dpll_mpu; | |
55 | u32 cm_idlest_dpll_mpu; | |
56 | u32 cm_autoidle_dpll_mpu; | |
57 | u32 cm_clksel_dpll_mpu; | |
58 | u32 cm_div_m2_dpll_mpu; | |
59 | u32 cm_ssc_deltamstep_dpll_mpu; | |
60 | u32 cm_ssc_modfreqdiv_dpll_mpu; | |
61 | u32 cm_bypclk_dpll_mpu; | |
62 | u32 cm_clkmode_dpll_iva; | |
63 | u32 cm_idlest_dpll_iva; | |
64 | u32 cm_autoidle_dpll_iva; | |
65 | u32 cm_clksel_dpll_iva; | |
66 | u32 cm_div_h11_dpll_iva; | |
67 | u32 cm_div_h12_dpll_iva; | |
68 | u32 cm_ssc_deltamstep_dpll_iva; | |
69 | u32 cm_ssc_modfreqdiv_dpll_iva; | |
70 | u32 cm_bypclk_dpll_iva; | |
71 | u32 cm_clkmode_dpll_abe; | |
72 | u32 cm_idlest_dpll_abe; | |
73 | u32 cm_autoidle_dpll_abe; | |
74 | u32 cm_clksel_dpll_abe; | |
75 | u32 cm_div_m2_dpll_abe; | |
76 | u32 cm_div_m3_dpll_abe; | |
77 | u32 cm_ssc_deltamstep_dpll_abe; | |
78 | u32 cm_ssc_modfreqdiv_dpll_abe; | |
79 | u32 cm_clkmode_dpll_ddrphy; | |
80 | u32 cm_idlest_dpll_ddrphy; | |
81 | u32 cm_autoidle_dpll_ddrphy; | |
82 | u32 cm_clksel_dpll_ddrphy; | |
83 | u32 cm_div_m2_dpll_ddrphy; | |
84 | u32 cm_div_h11_dpll_ddrphy; | |
85 | u32 cm_div_h12_dpll_ddrphy; | |
86 | u32 cm_div_h13_dpll_ddrphy; | |
87 | u32 cm_ssc_deltamstep_dpll_ddrphy; | |
d4e4129c | 88 | u32 cm_clkmode_dpll_dsp; |
01b753ff S |
89 | u32 cm_shadow_freq_config1; |
90 | u32 cm_mpu_mpu_clkctrl; | |
91 | ||
92 | /* cm1.dsp */ | |
93 | u32 cm_dsp_clkstctrl; | |
94 | u32 cm_dsp_dsp_clkctrl; | |
95 | ||
96 | /* cm1.abe */ | |
97 | u32 cm1_abe_clkstctrl; | |
98 | u32 cm1_abe_l4abe_clkctrl; | |
99 | u32 cm1_abe_aess_clkctrl; | |
100 | u32 cm1_abe_pdm_clkctrl; | |
101 | u32 cm1_abe_dmic_clkctrl; | |
102 | u32 cm1_abe_mcasp_clkctrl; | |
103 | u32 cm1_abe_mcbsp1_clkctrl; | |
104 | u32 cm1_abe_mcbsp2_clkctrl; | |
105 | u32 cm1_abe_mcbsp3_clkctrl; | |
106 | u32 cm1_abe_slimbus_clkctrl; | |
107 | u32 cm1_abe_timer5_clkctrl; | |
108 | u32 cm1_abe_timer6_clkctrl; | |
109 | u32 cm1_abe_timer7_clkctrl; | |
110 | u32 cm1_abe_timer8_clkctrl; | |
111 | u32 cm1_abe_wdt3_clkctrl; | |
112 | ||
113 | /* cm2.ckgen */ | |
114 | u32 cm_clksel_mpu_m3_iss_root; | |
115 | u32 cm_clksel_usb_60mhz; | |
116 | u32 cm_scale_fclk; | |
117 | u32 cm_core_dvfs_perf1; | |
118 | u32 cm_core_dvfs_perf2; | |
119 | u32 cm_core_dvfs_perf3; | |
120 | u32 cm_core_dvfs_perf4; | |
121 | u32 cm_core_dvfs_current; | |
122 | u32 cm_iva_dvfs_perf_tesla; | |
123 | u32 cm_iva_dvfs_perf_ivahd; | |
124 | u32 cm_iva_dvfs_perf_abe; | |
125 | u32 cm_iva_dvfs_current; | |
126 | u32 cm_clkmode_dpll_per; | |
127 | u32 cm_idlest_dpll_per; | |
128 | u32 cm_autoidle_dpll_per; | |
129 | u32 cm_clksel_dpll_per; | |
130 | u32 cm_div_m2_dpll_per; | |
131 | u32 cm_div_m3_dpll_per; | |
132 | u32 cm_div_h11_dpll_per; | |
133 | u32 cm_div_h12_dpll_per; | |
afc2f9dc | 134 | u32 cm_div_h13_dpll_per; |
01b753ff S |
135 | u32 cm_div_h14_dpll_per; |
136 | u32 cm_ssc_deltamstep_dpll_per; | |
137 | u32 cm_ssc_modfreqdiv_dpll_per; | |
138 | u32 cm_emu_override_dpll_per; | |
139 | u32 cm_clkmode_dpll_usb; | |
140 | u32 cm_idlest_dpll_usb; | |
141 | u32 cm_autoidle_dpll_usb; | |
142 | u32 cm_clksel_dpll_usb; | |
143 | u32 cm_div_m2_dpll_usb; | |
144 | u32 cm_ssc_deltamstep_dpll_usb; | |
145 | u32 cm_ssc_modfreqdiv_dpll_usb; | |
146 | u32 cm_clkdcoldo_dpll_usb; | |
d4e4129c LV |
147 | u32 cm_clkmode_dpll_pcie_ref; |
148 | u32 cm_clkmode_apll_pcie; | |
149 | u32 cm_idlest_apll_pcie; | |
150 | u32 cm_div_m2_apll_pcie; | |
151 | u32 cm_clkvcoldo_apll_pcie; | |
01b753ff S |
152 | u32 cm_clkmode_dpll_unipro; |
153 | u32 cm_idlest_dpll_unipro; | |
154 | u32 cm_autoidle_dpll_unipro; | |
155 | u32 cm_clksel_dpll_unipro; | |
156 | u32 cm_div_m2_dpll_unipro; | |
157 | u32 cm_ssc_deltamstep_dpll_unipro; | |
158 | u32 cm_ssc_modfreqdiv_dpll_unipro; | |
159 | ||
160 | /* cm2.core */ | |
161 | u32 cm_coreaon_bandgap_clkctrl; | |
d4d986ee | 162 | u32 cm_coreaon_io_srcomp_clkctrl; |
01b753ff S |
163 | u32 cm_l3_1_clkstctrl; |
164 | u32 cm_l3_1_dynamicdep; | |
165 | u32 cm_l3_1_l3_1_clkctrl; | |
166 | u32 cm_l3_2_clkstctrl; | |
167 | u32 cm_l3_2_dynamicdep; | |
168 | u32 cm_l3_2_l3_2_clkctrl; | |
d4e4129c | 169 | u32 cm_l3_gpmc_clkctrl; |
01b753ff S |
170 | u32 cm_l3_2_ocmc_ram_clkctrl; |
171 | u32 cm_mpu_m3_clkstctrl; | |
172 | u32 cm_mpu_m3_staticdep; | |
173 | u32 cm_mpu_m3_dynamicdep; | |
174 | u32 cm_mpu_m3_mpu_m3_clkctrl; | |
175 | u32 cm_sdma_clkstctrl; | |
176 | u32 cm_sdma_staticdep; | |
177 | u32 cm_sdma_dynamicdep; | |
178 | u32 cm_sdma_sdma_clkctrl; | |
179 | u32 cm_memif_clkstctrl; | |
180 | u32 cm_memif_dmm_clkctrl; | |
181 | u32 cm_memif_emif_fw_clkctrl; | |
182 | u32 cm_memif_emif_1_clkctrl; | |
183 | u32 cm_memif_emif_2_clkctrl; | |
184 | u32 cm_memif_dll_clkctrl; | |
185 | u32 cm_memif_emif_h1_clkctrl; | |
186 | u32 cm_memif_emif_h2_clkctrl; | |
187 | u32 cm_memif_dll_h_clkctrl; | |
188 | u32 cm_c2c_clkstctrl; | |
189 | u32 cm_c2c_staticdep; | |
190 | u32 cm_c2c_dynamicdep; | |
191 | u32 cm_c2c_sad2d_clkctrl; | |
192 | u32 cm_c2c_modem_icr_clkctrl; | |
193 | u32 cm_c2c_sad2d_fw_clkctrl; | |
194 | u32 cm_l4cfg_clkstctrl; | |
195 | u32 cm_l4cfg_dynamicdep; | |
196 | u32 cm_l4cfg_l4_cfg_clkctrl; | |
197 | u32 cm_l4cfg_hw_sem_clkctrl; | |
198 | u32 cm_l4cfg_mailbox_clkctrl; | |
199 | u32 cm_l4cfg_sar_rom_clkctrl; | |
200 | u32 cm_l3instr_clkstctrl; | |
201 | u32 cm_l3instr_l3_3_clkctrl; | |
202 | u32 cm_l3instr_l3_instr_clkctrl; | |
203 | u32 cm_l3instr_intrconn_wp1_clkctrl; | |
204 | ||
205 | /* cm2.ivahd */ | |
206 | u32 cm_ivahd_clkstctrl; | |
207 | u32 cm_ivahd_ivahd_clkctrl; | |
208 | u32 cm_ivahd_sl2_clkctrl; | |
209 | ||
210 | /* cm2.cam */ | |
211 | u32 cm_cam_clkstctrl; | |
212 | u32 cm_cam_iss_clkctrl; | |
213 | u32 cm_cam_fdif_clkctrl; | |
d4e4129c LV |
214 | u32 cm_cam_vip1_clkctrl; |
215 | u32 cm_cam_vip2_clkctrl; | |
216 | u32 cm_cam_vip3_clkctrl; | |
217 | u32 cm_cam_lvdsrx_clkctrl; | |
218 | u32 cm_cam_csi1_clkctrl; | |
219 | u32 cm_cam_csi2_clkctrl; | |
01b753ff S |
220 | |
221 | /* cm2.dss */ | |
222 | u32 cm_dss_clkstctrl; | |
223 | u32 cm_dss_dss_clkctrl; | |
224 | ||
225 | /* cm2.sgx */ | |
226 | u32 cm_sgx_clkstctrl; | |
227 | u32 cm_sgx_sgx_clkctrl; | |
228 | ||
229 | /* cm2.l3init */ | |
230 | u32 cm_l3init_clkstctrl; | |
231 | ||
232 | /* cm2.l3init */ | |
233 | u32 cm_l3init_hsmmc1_clkctrl; | |
234 | u32 cm_l3init_hsmmc2_clkctrl; | |
235 | u32 cm_l3init_hsi_clkctrl; | |
236 | u32 cm_l3init_hsusbhost_clkctrl; | |
237 | u32 cm_l3init_hsusbotg_clkctrl; | |
238 | u32 cm_l3init_hsusbtll_clkctrl; | |
239 | u32 cm_l3init_p1500_clkctrl; | |
240 | u32 cm_l3init_fsusb_clkctrl; | |
241 | u32 cm_l3init_ocp2scp1_clkctrl; | |
242 | ||
243 | /* cm2.l4per */ | |
244 | u32 cm_l4per_clkstctrl; | |
245 | u32 cm_l4per_dynamicdep; | |
246 | u32 cm_l4per_adc_clkctrl; | |
247 | u32 cm_l4per_gptimer10_clkctrl; | |
248 | u32 cm_l4per_gptimer11_clkctrl; | |
249 | u32 cm_l4per_gptimer2_clkctrl; | |
250 | u32 cm_l4per_gptimer3_clkctrl; | |
251 | u32 cm_l4per_gptimer4_clkctrl; | |
252 | u32 cm_l4per_gptimer9_clkctrl; | |
253 | u32 cm_l4per_elm_clkctrl; | |
254 | u32 cm_l4per_gpio2_clkctrl; | |
255 | u32 cm_l4per_gpio3_clkctrl; | |
256 | u32 cm_l4per_gpio4_clkctrl; | |
257 | u32 cm_l4per_gpio5_clkctrl; | |
258 | u32 cm_l4per_gpio6_clkctrl; | |
259 | u32 cm_l4per_hdq1w_clkctrl; | |
260 | u32 cm_l4per_hecc1_clkctrl; | |
261 | u32 cm_l4per_hecc2_clkctrl; | |
262 | u32 cm_l4per_i2c1_clkctrl; | |
263 | u32 cm_l4per_i2c2_clkctrl; | |
264 | u32 cm_l4per_i2c3_clkctrl; | |
265 | u32 cm_l4per_i2c4_clkctrl; | |
266 | u32 cm_l4per_l4per_clkctrl; | |
267 | u32 cm_l4per_mcasp2_clkctrl; | |
268 | u32 cm_l4per_mcasp3_clkctrl; | |
269 | u32 cm_l4per_mgate_clkctrl; | |
270 | u32 cm_l4per_mcspi1_clkctrl; | |
271 | u32 cm_l4per_mcspi2_clkctrl; | |
272 | u32 cm_l4per_mcspi3_clkctrl; | |
273 | u32 cm_l4per_mcspi4_clkctrl; | |
274 | u32 cm_l4per_gpio7_clkctrl; | |
275 | u32 cm_l4per_gpio8_clkctrl; | |
276 | u32 cm_l4per_mmcsd3_clkctrl; | |
277 | u32 cm_l4per_mmcsd4_clkctrl; | |
278 | u32 cm_l4per_msprohg_clkctrl; | |
279 | u32 cm_l4per_slimbus2_clkctrl; | |
280 | u32 cm_l4per_uart1_clkctrl; | |
281 | u32 cm_l4per_uart2_clkctrl; | |
282 | u32 cm_l4per_uart3_clkctrl; | |
283 | u32 cm_l4per_uart4_clkctrl; | |
284 | u32 cm_l4per_mmcsd5_clkctrl; | |
285 | u32 cm_l4per_i2c5_clkctrl; | |
286 | u32 cm_l4per_uart5_clkctrl; | |
287 | u32 cm_l4per_uart6_clkctrl; | |
288 | u32 cm_l4sec_clkstctrl; | |
289 | u32 cm_l4sec_staticdep; | |
290 | u32 cm_l4sec_dynamicdep; | |
291 | u32 cm_l4sec_aes1_clkctrl; | |
292 | u32 cm_l4sec_aes2_clkctrl; | |
293 | u32 cm_l4sec_des3des_clkctrl; | |
294 | u32 cm_l4sec_pkaeip29_clkctrl; | |
295 | u32 cm_l4sec_rng_clkctrl; | |
296 | u32 cm_l4sec_sha2md51_clkctrl; | |
297 | u32 cm_l4sec_cryptodma_clkctrl; | |
298 | ||
299 | /* l4 wkup regs */ | |
300 | u32 cm_abe_pll_ref_clksel; | |
301 | u32 cm_sys_clksel; | |
302 | u32 cm_wkup_clkstctrl; | |
303 | u32 cm_wkup_l4wkup_clkctrl; | |
304 | u32 cm_wkup_wdtimer1_clkctrl; | |
305 | u32 cm_wkup_wdtimer2_clkctrl; | |
306 | u32 cm_wkup_gpio1_clkctrl; | |
307 | u32 cm_wkup_gptimer1_clkctrl; | |
308 | u32 cm_wkup_gptimer12_clkctrl; | |
309 | u32 cm_wkup_synctimer_clkctrl; | |
310 | u32 cm_wkup_usim_clkctrl; | |
311 | u32 cm_wkup_sarram_clkctrl; | |
312 | u32 cm_wkup_keyboard_clkctrl; | |
313 | u32 cm_wkup_rtc_clkctrl; | |
314 | u32 cm_wkup_bandgap_clkctrl; | |
315 | u32 cm_wkupaon_scrm_clkctrl; | |
d4d986ee | 316 | u32 cm_wkupaon_io_srcomp_clkctrl; |
d4e4129c LV |
317 | u32 prm_rstctrl; |
318 | u32 prm_rstst; | |
01b753ff S |
319 | u32 prm_vc_val_bypass; |
320 | u32 prm_vc_cfg_i2c_mode; | |
321 | u32 prm_vc_cfg_i2c_clk; | |
322 | u32 prm_sldo_core_setup; | |
323 | u32 prm_sldo_core_ctrl; | |
324 | u32 prm_sldo_mpu_setup; | |
325 | u32 prm_sldo_mpu_ctrl; | |
326 | u32 prm_sldo_mm_setup; | |
327 | u32 prm_sldo_mm_ctrl; | |
328 | ||
329 | u32 cm_div_m4_dpll_core; | |
330 | u32 cm_div_m5_dpll_core; | |
331 | u32 cm_div_m6_dpll_core; | |
332 | u32 cm_div_m7_dpll_core; | |
333 | u32 cm_div_m4_dpll_iva; | |
334 | u32 cm_div_m5_dpll_iva; | |
335 | u32 cm_div_m4_dpll_ddrphy; | |
336 | u32 cm_div_m5_dpll_ddrphy; | |
337 | u32 cm_div_m6_dpll_ddrphy; | |
338 | u32 cm_div_m4_dpll_per; | |
339 | u32 cm_div_m5_dpll_per; | |
340 | u32 cm_div_m6_dpll_per; | |
341 | u32 cm_div_m7_dpll_per; | |
342 | u32 cm_l3instr_intrconn_wp1_clkct; | |
343 | u32 cm_l3init_usbphy_clkctrl; | |
344 | u32 cm_l4per_mcbsp4_clkctrl; | |
345 | u32 prm_vc_cfg_channel; | |
346 | }; | |
347 | ||
c43c8339 LV |
348 | struct omap_sys_ctrl_regs { |
349 | u32 control_status; | |
350 | u32 control_id_code; | |
351 | u32 control_std_fuse_opp_bgap; | |
352 | u32 control_ldosram_iva_voltage_ctrl; | |
353 | u32 control_ldosram_mpu_voltage_ctrl; | |
354 | u32 control_ldosram_core_voltage_ctrl; | |
355 | u32 control_paconf_global; | |
356 | u32 control_paconf_mode; | |
357 | u32 control_smart1io_padconf_0; | |
358 | u32 control_smart1io_padconf_1; | |
359 | u32 control_smart1io_padconf_2; | |
360 | u32 control_smart2io_padconf_0; | |
361 | u32 control_smart2io_padconf_1; | |
362 | u32 control_smart2io_padconf_2; | |
363 | u32 control_smart3io_padconf_0; | |
364 | u32 control_smart3io_padconf_1; | |
365 | u32 control_pbias; | |
366 | u32 control_i2c_0; | |
367 | u32 control_camera_rx; | |
368 | u32 control_hdmi_tx_phy; | |
369 | u32 control_uniportm; | |
370 | u32 control_dsiphy; | |
371 | u32 control_mcbsplp; | |
372 | u32 control_usb2phycore; | |
373 | u32 control_hdmi_1; | |
374 | u32 control_hsi; | |
375 | u32 control_ddr3ch1_0; | |
376 | u32 control_ddr3ch2_0; | |
377 | u32 control_ddrch1_0; | |
378 | u32 control_ddrch1_1; | |
379 | u32 control_ddrch2_0; | |
380 | u32 control_ddrch2_1; | |
381 | u32 control_lpddr2ch1_0; | |
382 | u32 control_lpddr2ch1_1; | |
383 | u32 control_ddrio_0; | |
384 | u32 control_ddrio_1; | |
385 | u32 control_ddrio_2; | |
386 | u32 control_lpddr2io1_0; | |
387 | u32 control_lpddr2io1_1; | |
388 | u32 control_lpddr2io1_2; | |
389 | u32 control_lpddr2io1_3; | |
390 | u32 control_lpddr2io2_0; | |
391 | u32 control_lpddr2io2_1; | |
392 | u32 control_lpddr2io2_2; | |
393 | u32 control_lpddr2io2_3; | |
394 | u32 control_hyst_1; | |
395 | u32 control_usbb_hsic_control; | |
396 | u32 control_c2c; | |
397 | u32 control_core_control_spare_rw; | |
398 | u32 control_core_control_spare_r; | |
399 | u32 control_core_control_spare_r_c0; | |
400 | u32 control_srcomp_north_side; | |
401 | u32 control_srcomp_south_side; | |
402 | u32 control_srcomp_east_side; | |
403 | u32 control_srcomp_west_side; | |
404 | u32 control_srcomp_code_latch; | |
405 | u32 control_pbiaslite; | |
406 | u32 control_port_emif1_sdram_config; | |
407 | u32 control_port_emif1_lpddr2_nvm_config; | |
408 | u32 control_port_emif2_sdram_config; | |
409 | u32 control_emif1_sdram_config_ext; | |
410 | u32 control_emif2_sdram_config_ext; | |
411 | u32 control_smart1nopmio_padconf_0; | |
412 | u32 control_smart1nopmio_padconf_1; | |
413 | u32 control_padconf_mode; | |
414 | u32 control_xtal_oscillator; | |
415 | u32 control_i2c_2; | |
416 | u32 control_ckobuffer; | |
417 | u32 control_wkup_control_spare_rw; | |
418 | u32 control_wkup_control_spare_r; | |
419 | u32 control_wkup_control_spare_r_c0; | |
420 | u32 control_srcomp_east_side_wkup; | |
421 | u32 control_efuse_1; | |
422 | u32 control_efuse_2; | |
423 | u32 control_efuse_3; | |
424 | u32 control_efuse_4; | |
425 | u32 control_efuse_5; | |
426 | u32 control_efuse_6; | |
427 | u32 control_efuse_7; | |
428 | u32 control_efuse_8; | |
429 | u32 control_efuse_9; | |
430 | u32 control_efuse_10; | |
431 | u32 control_efuse_11; | |
432 | u32 control_efuse_12; | |
433 | u32 control_efuse_13; | |
434 | }; | |
435 | ||
ee9447bf S |
436 | struct dpll_params { |
437 | u32 m; | |
438 | u32 n; | |
439 | s8 m2; | |
440 | s8 m3; | |
441 | s8 m4_h11; | |
442 | s8 m5_h12; | |
443 | s8 m6_h13; | |
444 | s8 m7_h14; | |
47abc3df | 445 | s8 h21; |
ee9447bf S |
446 | s8 h22; |
447 | s8 h23; | |
47abc3df | 448 | s8 h24; |
ee9447bf S |
449 | }; |
450 | ||
451 | struct dpll_regs { | |
452 | u32 cm_clkmode_dpll; | |
453 | u32 cm_idlest_dpll; | |
454 | u32 cm_autoidle_dpll; | |
455 | u32 cm_clksel_dpll; | |
456 | u32 cm_div_m2_dpll; | |
457 | u32 cm_div_m3_dpll; | |
458 | u32 cm_div_m4_h11_dpll; | |
459 | u32 cm_div_m5_h12_dpll; | |
460 | u32 cm_div_m6_h13_dpll; | |
461 | u32 cm_div_m7_h14_dpll; | |
47abc3df S |
462 | u32 reserved[2]; |
463 | u32 cm_div_h21_dpll; | |
ee9447bf S |
464 | u32 cm_div_h22_dpll; |
465 | u32 cm_div_h23_dpll; | |
47abc3df | 466 | u32 cm_div_h24_dpll; |
ee9447bf S |
467 | }; |
468 | ||
469 | struct dplls { | |
470 | const struct dpll_params *mpu; | |
471 | const struct dpll_params *core; | |
472 | const struct dpll_params *per; | |
473 | const struct dpll_params *abe; | |
474 | const struct dpll_params *iva; | |
475 | const struct dpll_params *usb; | |
ea8eff1f | 476 | const struct dpll_params *ddr; |
ee9447bf S |
477 | }; |
478 | ||
3fcdd4a5 S |
479 | struct pmic_data { |
480 | u32 base_offset; | |
481 | u32 step; | |
482 | u32 start_code; | |
483 | unsigned gpio; | |
484 | int gpio_en; | |
485 | }; | |
486 | ||
487 | struct volts { | |
488 | u32 value; | |
489 | u32 addr; | |
490 | struct pmic_data *pmic; | |
491 | }; | |
492 | ||
493 | struct vcores_data { | |
494 | struct volts mpu; | |
495 | struct volts core; | |
496 | struct volts mm; | |
497 | }; | |
498 | ||
01b753ff S |
499 | extern struct prcm_regs const **prcm; |
500 | extern struct prcm_regs const omap5_es1_prcm; | |
afc2f9dc | 501 | extern struct prcm_regs const omap5_es2_prcm; |
01b753ff | 502 | extern struct prcm_regs const omap4_prcm; |
d4e4129c | 503 | extern struct prcm_regs const dra7xx_prcm; |
ee9447bf | 504 | extern struct dplls const **dplls_data; |
3fcdd4a5 | 505 | extern struct vcores_data const **omap_vcores; |
ee9447bf | 506 | extern const u32 sys_clk_array[8]; |
c43c8339 LV |
507 | extern struct omap_sys_ctrl_regs const **ctrl; |
508 | extern struct omap_sys_ctrl_regs const omap4_ctrl; | |
509 | extern struct omap_sys_ctrl_regs const omap5_ctrl; | |
01b753ff S |
510 | |
511 | void hw_data_init(void); | |
ee9447bf S |
512 | |
513 | const struct dpll_params *get_mpu_dpll_params(struct dplls const *); | |
514 | const struct dpll_params *get_core_dpll_params(struct dplls const *); | |
515 | const struct dpll_params *get_per_dpll_params(struct dplls const *); | |
516 | const struct dpll_params *get_iva_dpll_params(struct dplls const *); | |
517 | const struct dpll_params *get_usb_dpll_params(struct dplls const *); | |
518 | const struct dpll_params *get_abe_dpll_params(struct dplls const *); | |
519 | ||
520 | void do_enable_clocks(u32 const *clk_domains, | |
521 | u32 const *clk_modules_hw_auto, | |
522 | u32 const *clk_modules_explicit_en, | |
523 | u8 wait_for_enable); | |
524 | ||
525 | void setup_post_dividers(u32 const base, | |
526 | const struct dpll_params *params); | |
527 | u32 omap_ddr_clk(void); | |
528 | u32 get_sys_clk_index(void); | |
529 | void enable_basic_clocks(void); | |
530 | void enable_basic_uboot_clocks(void); | |
531 | void enable_non_essential_clocks(void); | |
3fcdd4a5 S |
532 | void scale_vcores(struct vcores_data const *); |
533 | u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); | |
534 | void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); | |
ee9447bf | 535 | |
3776801d A |
536 | /* Max value for DPLL multiplier M */ |
537 | #define OMAP_DPLL_MAX_N 127 | |
538 | ||
d2f18c27 A |
539 | /* HW Init Context */ |
540 | #define OMAP_INIT_CONTEXT_SPL 0 | |
541 | #define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 | |
542 | #define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 | |
543 | #define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 | |
544 | ||
087189fb S |
545 | static inline u32 omap_revision(void) |
546 | { | |
547 | extern u32 *const omap_si_rev; | |
548 | return *omap_si_rev; | |
549 | } | |
550 | ||
508a58fa S |
551 | /* |
552 | * silicon revisions. | |
553 | * Moving this to common, so that most of code can be moved to common, | |
554 | * directories. | |
555 | */ | |
556 | ||
557 | /* omap4 */ | |
558 | #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF | |
559 | #define OMAP4430_ES1_0 0x44300100 | |
560 | #define OMAP4430_ES2_0 0x44300200 | |
561 | #define OMAP4430_ES2_1 0x44300210 | |
562 | #define OMAP4430_ES2_2 0x44300220 | |
563 | #define OMAP4430_ES2_3 0x44300230 | |
564 | #define OMAP4460_ES1_0 0x44600100 | |
9404758e | 565 | #define OMAP4460_ES1_1 0x44600110 |
508a58fa S |
566 | |
567 | /* omap5 */ | |
568 | #define OMAP5430_SILICON_ID_INVALID 0 | |
569 | #define OMAP5430_ES1_0 0x54300100 | |
0a0bf7b2 | 570 | #define OMAP5432_ES1_0 0x54320100 |
eed7c0f7 S |
571 | #define OMAP5430_ES2_0 0x54300200 |
572 | #define OMAP5432_ES2_0 0x54320200 | |
d2f18c27 | 573 | #endif /* _OMAP_COMMON_H_ */ |