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f81ef4a9 WD |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License version 2 as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
14 | * | |
15 | * Copyright (C) 2009, 2010 ARM Limited | |
16 | * | |
17 | * Author: Will Deacon <will.deacon@arm.com> | |
18 | */ | |
19 | ||
20 | /* | |
21 | * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, | |
22 | * using the CPU's debug registers. | |
23 | */ | |
24 | #define pr_fmt(fmt) "hw-breakpoint: " fmt | |
25 | ||
26 | #include <linux/errno.h> | |
7e202696 | 27 | #include <linux/hardirq.h> |
f81ef4a9 WD |
28 | #include <linux/perf_event.h> |
29 | #include <linux/hw_breakpoint.h> | |
30 | #include <linux/smp.h> | |
31 | ||
32 | #include <asm/cacheflush.h> | |
33 | #include <asm/cputype.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/hw_breakpoint.h> | |
36 | #include <asm/kdebug.h> | |
f81ef4a9 | 37 | #include <asm/traps.h> |
02051ead | 38 | #include <asm/hardware/coresight.h> |
f81ef4a9 WD |
39 | |
40 | /* Breakpoint currently in use for each BRP. */ | |
41 | static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); | |
42 | ||
43 | /* Watchpoint currently in use for each WRP. */ | |
44 | static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); | |
45 | ||
46 | /* Number of BRP/WRP registers on this CPU. */ | |
47 | static int core_num_brps; | |
48 | static int core_num_wrps; | |
49 | ||
50 | /* Debug architecture version. */ | |
51 | static u8 debug_arch; | |
52 | ||
53 | /* Maximum supported watchpoint length. */ | |
54 | static u8 max_watchpoint_len; | |
55 | ||
9e962f76 DE |
56 | #define READ_WB_REG_CASE(OP2, M, VAL) \ |
57 | case ((OP2 << 4) + M): \ | |
58 | ARM_DBG_READ(c0, c ## M, OP2, VAL); \ | |
f81ef4a9 WD |
59 | break |
60 | ||
9e962f76 DE |
61 | #define WRITE_WB_REG_CASE(OP2, M, VAL) \ |
62 | case ((OP2 << 4) + M): \ | |
63 | ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \ | |
f81ef4a9 WD |
64 | break |
65 | ||
66 | #define GEN_READ_WB_REG_CASES(OP2, VAL) \ | |
67 | READ_WB_REG_CASE(OP2, 0, VAL); \ | |
68 | READ_WB_REG_CASE(OP2, 1, VAL); \ | |
69 | READ_WB_REG_CASE(OP2, 2, VAL); \ | |
70 | READ_WB_REG_CASE(OP2, 3, VAL); \ | |
71 | READ_WB_REG_CASE(OP2, 4, VAL); \ | |
72 | READ_WB_REG_CASE(OP2, 5, VAL); \ | |
73 | READ_WB_REG_CASE(OP2, 6, VAL); \ | |
74 | READ_WB_REG_CASE(OP2, 7, VAL); \ | |
75 | READ_WB_REG_CASE(OP2, 8, VAL); \ | |
76 | READ_WB_REG_CASE(OP2, 9, VAL); \ | |
77 | READ_WB_REG_CASE(OP2, 10, VAL); \ | |
78 | READ_WB_REG_CASE(OP2, 11, VAL); \ | |
79 | READ_WB_REG_CASE(OP2, 12, VAL); \ | |
80 | READ_WB_REG_CASE(OP2, 13, VAL); \ | |
81 | READ_WB_REG_CASE(OP2, 14, VAL); \ | |
82 | READ_WB_REG_CASE(OP2, 15, VAL) | |
83 | ||
84 | #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \ | |
85 | WRITE_WB_REG_CASE(OP2, 0, VAL); \ | |
86 | WRITE_WB_REG_CASE(OP2, 1, VAL); \ | |
87 | WRITE_WB_REG_CASE(OP2, 2, VAL); \ | |
88 | WRITE_WB_REG_CASE(OP2, 3, VAL); \ | |
89 | WRITE_WB_REG_CASE(OP2, 4, VAL); \ | |
90 | WRITE_WB_REG_CASE(OP2, 5, VAL); \ | |
91 | WRITE_WB_REG_CASE(OP2, 6, VAL); \ | |
92 | WRITE_WB_REG_CASE(OP2, 7, VAL); \ | |
93 | WRITE_WB_REG_CASE(OP2, 8, VAL); \ | |
94 | WRITE_WB_REG_CASE(OP2, 9, VAL); \ | |
95 | WRITE_WB_REG_CASE(OP2, 10, VAL); \ | |
96 | WRITE_WB_REG_CASE(OP2, 11, VAL); \ | |
97 | WRITE_WB_REG_CASE(OP2, 12, VAL); \ | |
98 | WRITE_WB_REG_CASE(OP2, 13, VAL); \ | |
99 | WRITE_WB_REG_CASE(OP2, 14, VAL); \ | |
100 | WRITE_WB_REG_CASE(OP2, 15, VAL) | |
101 | ||
102 | static u32 read_wb_reg(int n) | |
103 | { | |
104 | u32 val = 0; | |
105 | ||
106 | switch (n) { | |
107 | GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val); | |
108 | GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val); | |
109 | GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val); | |
110 | GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val); | |
111 | default: | |
112 | pr_warning("attempt to read from unknown breakpoint " | |
113 | "register %d\n", n); | |
114 | } | |
115 | ||
116 | return val; | |
117 | } | |
118 | ||
119 | static void write_wb_reg(int n, u32 val) | |
120 | { | |
121 | switch (n) { | |
122 | GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val); | |
123 | GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val); | |
124 | GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val); | |
125 | GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val); | |
126 | default: | |
127 | pr_warning("attempt to write to unknown breakpoint " | |
128 | "register %d\n", n); | |
129 | } | |
130 | isb(); | |
131 | } | |
132 | ||
0017ff42 WD |
133 | /* Determine debug architecture. */ |
134 | static u8 get_debug_arch(void) | |
135 | { | |
136 | u32 didr; | |
137 | ||
138 | /* Do we implement the extended CPUID interface? */ | |
d1244336 | 139 | if (((read_cpuid_id() >> 16) & 0xf) != 0xf) { |
5ad29ea2 WD |
140 | pr_warn_once("CPUID feature registers not supported. " |
141 | "Assuming v6 debug is present.\n"); | |
0017ff42 | 142 | return ARM_DEBUG_ARCH_V6; |
d1244336 | 143 | } |
0017ff42 | 144 | |
9e962f76 | 145 | ARM_DBG_READ(c0, c0, 0, didr); |
0017ff42 WD |
146 | return (didr >> 16) & 0xf; |
147 | } | |
148 | ||
149 | u8 arch_get_debug_arch(void) | |
150 | { | |
151 | return debug_arch; | |
152 | } | |
153 | ||
66e1cfe6 WD |
154 | static int debug_arch_supported(void) |
155 | { | |
156 | u8 arch = get_debug_arch(); | |
b5d5b8f9 WD |
157 | |
158 | /* We don't support the memory-mapped interface. */ | |
159 | return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) || | |
160 | arch >= ARM_DEBUG_ARCH_V7_1; | |
66e1cfe6 WD |
161 | } |
162 | ||
bf880114 WD |
163 | /* Can we determine the watchpoint access type from the fsr? */ |
164 | static int debug_exception_updates_fsr(void) | |
165 | { | |
166 | return 0; | |
167 | } | |
168 | ||
c512de95 WD |
169 | /* Determine number of WRP registers available. */ |
170 | static int get_num_wrp_resources(void) | |
171 | { | |
172 | u32 didr; | |
9e962f76 | 173 | ARM_DBG_READ(c0, c0, 0, didr); |
c512de95 WD |
174 | return ((didr >> 28) & 0xf) + 1; |
175 | } | |
176 | ||
177 | /* Determine number of BRP registers available. */ | |
0017ff42 WD |
178 | static int get_num_brp_resources(void) |
179 | { | |
180 | u32 didr; | |
9e962f76 | 181 | ARM_DBG_READ(c0, c0, 0, didr); |
0017ff42 WD |
182 | return ((didr >> 24) & 0xf) + 1; |
183 | } | |
184 | ||
185 | /* Does this core support mismatch breakpoints? */ | |
186 | static int core_has_mismatch_brps(void) | |
187 | { | |
188 | return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 && | |
189 | get_num_brp_resources() > 1); | |
190 | } | |
191 | ||
192 | /* Determine number of usable WRPs available. */ | |
193 | static int get_num_wrps(void) | |
194 | { | |
195 | /* | |
c512de95 WD |
196 | * On debug architectures prior to 7.1, when a watchpoint fires, the |
197 | * only way to work out which watchpoint it was is by disassembling | |
198 | * the faulting instruction and working out the address of the memory | |
199 | * access. | |
0017ff42 WD |
200 | * |
201 | * Furthermore, we can only do this if the watchpoint was precise | |
202 | * since imprecise watchpoints prevent us from calculating register | |
203 | * based addresses. | |
204 | * | |
205 | * Providing we have more than 1 breakpoint register, we only report | |
206 | * a single watchpoint register for the time being. This way, we always | |
207 | * know which watchpoint fired. In the future we can either add a | |
208 | * disassembler and address generation emulator, or we can insert a | |
209 | * check to see if the DFAR is set on watchpoint exception entry | |
210 | * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows | |
211 | * that it is set on some implementations]. | |
212 | */ | |
c512de95 WD |
213 | if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1) |
214 | return 1; | |
0017ff42 | 215 | |
c512de95 | 216 | return get_num_wrp_resources(); |
0017ff42 WD |
217 | } |
218 | ||
219 | /* Determine number of usable BRPs available. */ | |
220 | static int get_num_brps(void) | |
221 | { | |
222 | int brps = get_num_brp_resources(); | |
c512de95 | 223 | return core_has_mismatch_brps() ? brps - 1 : brps; |
0017ff42 WD |
224 | } |
225 | ||
f81ef4a9 WD |
226 | /* |
227 | * In order to access the breakpoint/watchpoint control registers, | |
228 | * we must be running in debug monitor mode. Unfortunately, we can | |
229 | * be put into halting debug mode at any time by an external debugger | |
230 | * but there is nothing we can do to prevent that. | |
231 | */ | |
0daa034e WD |
232 | static int monitor_mode_enabled(void) |
233 | { | |
234 | u32 dscr; | |
9e962f76 | 235 | ARM_DBG_READ(c0, c1, 0, dscr); |
0daa034e WD |
236 | return !!(dscr & ARM_DSCR_MDBGEN); |
237 | } | |
238 | ||
f81ef4a9 WD |
239 | static int enable_monitor_mode(void) |
240 | { | |
241 | u32 dscr; | |
9e962f76 | 242 | ARM_DBG_READ(c0, c1, 0, dscr); |
f81ef4a9 | 243 | |
8fbf397c WD |
244 | /* If monitor mode is already enabled, just return. */ |
245 | if (dscr & ARM_DSCR_MDBGEN) | |
246 | goto out; | |
247 | ||
f81ef4a9 | 248 | /* Write to the corresponding DSCR. */ |
8fbf397c | 249 | switch (get_debug_arch()) { |
f81ef4a9 WD |
250 | case ARM_DEBUG_ARCH_V6: |
251 | case ARM_DEBUG_ARCH_V6_1: | |
9e962f76 | 252 | ARM_DBG_WRITE(c0, c1, 0, (dscr | ARM_DSCR_MDBGEN)); |
f81ef4a9 WD |
253 | break; |
254 | case ARM_DEBUG_ARCH_V7_ECP14: | |
b5d5b8f9 | 255 | case ARM_DEBUG_ARCH_V7_1: |
9e962f76 | 256 | ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN)); |
b59a540c | 257 | isb(); |
f81ef4a9 WD |
258 | break; |
259 | default: | |
614bea50 | 260 | return -ENODEV; |
f81ef4a9 WD |
261 | } |
262 | ||
263 | /* Check that the write made it through. */ | |
9e962f76 | 264 | ARM_DBG_READ(c0, c1, 0, dscr); |
f435ab79 WD |
265 | if (!(dscr & ARM_DSCR_MDBGEN)) { |
266 | pr_warn_once("Failed to enable monitor mode on CPU %d.\n", | |
267 | smp_processor_id()); | |
614bea50 | 268 | return -EPERM; |
f435ab79 | 269 | } |
f81ef4a9 WD |
270 | |
271 | out: | |
614bea50 | 272 | return 0; |
f81ef4a9 WD |
273 | } |
274 | ||
8fbf397c WD |
275 | int hw_breakpoint_slots(int type) |
276 | { | |
66e1cfe6 WD |
277 | if (!debug_arch_supported()) |
278 | return 0; | |
279 | ||
8fbf397c WD |
280 | /* |
281 | * We can be called early, so don't rely on | |
282 | * our static variables being initialised. | |
283 | */ | |
284 | switch (type) { | |
285 | case TYPE_INST: | |
286 | return get_num_brps(); | |
287 | case TYPE_DATA: | |
288 | return get_num_wrps(); | |
289 | default: | |
290 | pr_warning("unknown slot type: %d\n", type); | |
291 | return 0; | |
292 | } | |
293 | } | |
294 | ||
f81ef4a9 WD |
295 | /* |
296 | * Check if 8-bit byte-address select is available. | |
297 | * This clobbers WRP 0. | |
298 | */ | |
299 | static u8 get_max_wp_len(void) | |
300 | { | |
301 | u32 ctrl_reg; | |
302 | struct arch_hw_breakpoint_ctrl ctrl; | |
303 | u8 size = 4; | |
304 | ||
305 | if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14) | |
306 | goto out; | |
307 | ||
f81ef4a9 WD |
308 | memset(&ctrl, 0, sizeof(ctrl)); |
309 | ctrl.len = ARM_BREAKPOINT_LEN_8; | |
310 | ctrl_reg = encode_ctrl_reg(ctrl); | |
311 | ||
312 | write_wb_reg(ARM_BASE_WVR, 0); | |
313 | write_wb_reg(ARM_BASE_WCR, ctrl_reg); | |
314 | if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg) | |
315 | size = 8; | |
316 | ||
317 | out: | |
318 | return size; | |
319 | } | |
320 | ||
321 | u8 arch_get_max_wp_len(void) | |
322 | { | |
323 | return max_watchpoint_len; | |
324 | } | |
325 | ||
f81ef4a9 WD |
326 | /* |
327 | * Install a perf counter breakpoint. | |
328 | */ | |
329 | int arch_install_hw_breakpoint(struct perf_event *bp) | |
330 | { | |
331 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
332 | struct perf_event **slot, **slots; | |
0daa034e | 333 | int i, max_slots, ctrl_base, val_base; |
93a04a34 | 334 | u32 addr, ctrl; |
f81ef4a9 | 335 | |
93a04a34 WD |
336 | addr = info->address; |
337 | ctrl = encode_ctrl_reg(info->ctrl) | 0x1; | |
338 | ||
f81ef4a9 WD |
339 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { |
340 | /* Breakpoint */ | |
341 | ctrl_base = ARM_BASE_BCR; | |
342 | val_base = ARM_BASE_BVR; | |
4a55c18e | 343 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); |
0017ff42 | 344 | max_slots = core_num_brps; |
f81ef4a9 WD |
345 | } else { |
346 | /* Watchpoint */ | |
6f26aa05 WD |
347 | ctrl_base = ARM_BASE_WCR; |
348 | val_base = ARM_BASE_WVR; | |
4a55c18e | 349 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
f81ef4a9 WD |
350 | max_slots = core_num_wrps; |
351 | } | |
352 | ||
353 | for (i = 0; i < max_slots; ++i) { | |
354 | slot = &slots[i]; | |
355 | ||
356 | if (!*slot) { | |
357 | *slot = bp; | |
358 | break; | |
359 | } | |
360 | } | |
361 | ||
f435ab79 WD |
362 | if (i == max_slots) { |
363 | pr_warning("Can't find any breakpoint slot\n"); | |
0daa034e | 364 | return -EBUSY; |
f435ab79 | 365 | } |
f81ef4a9 | 366 | |
6f26aa05 WD |
367 | /* Override the breakpoint data with the step data. */ |
368 | if (info->step_ctrl.enabled) { | |
369 | addr = info->trigger & ~0x3; | |
370 | ctrl = encode_ctrl_reg(info->step_ctrl); | |
371 | if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) { | |
372 | i = 0; | |
373 | ctrl_base = ARM_BASE_BCR + core_num_brps; | |
374 | val_base = ARM_BASE_BVR + core_num_brps; | |
375 | } | |
376 | } | |
377 | ||
f81ef4a9 | 378 | /* Setup the address register. */ |
93a04a34 | 379 | write_wb_reg(val_base + i, addr); |
f81ef4a9 WD |
380 | |
381 | /* Setup the control register. */ | |
93a04a34 | 382 | write_wb_reg(ctrl_base + i, ctrl); |
0daa034e | 383 | return 0; |
f81ef4a9 WD |
384 | } |
385 | ||
386 | void arch_uninstall_hw_breakpoint(struct perf_event *bp) | |
387 | { | |
388 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
389 | struct perf_event **slot, **slots; | |
390 | int i, max_slots, base; | |
391 | ||
392 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { | |
393 | /* Breakpoint */ | |
394 | base = ARM_BASE_BCR; | |
4a55c18e | 395 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); |
0017ff42 | 396 | max_slots = core_num_brps; |
f81ef4a9 WD |
397 | } else { |
398 | /* Watchpoint */ | |
6f26aa05 | 399 | base = ARM_BASE_WCR; |
4a55c18e | 400 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
f81ef4a9 WD |
401 | max_slots = core_num_wrps; |
402 | } | |
403 | ||
404 | /* Remove the breakpoint. */ | |
405 | for (i = 0; i < max_slots; ++i) { | |
406 | slot = &slots[i]; | |
407 | ||
408 | if (*slot == bp) { | |
409 | *slot = NULL; | |
410 | break; | |
411 | } | |
412 | } | |
413 | ||
f435ab79 WD |
414 | if (i == max_slots) { |
415 | pr_warning("Can't find any breakpoint slot\n"); | |
f81ef4a9 | 416 | return; |
f435ab79 | 417 | } |
f81ef4a9 | 418 | |
6f26aa05 WD |
419 | /* Ensure that we disable the mismatch breakpoint. */ |
420 | if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE && | |
421 | info->step_ctrl.enabled) { | |
422 | i = 0; | |
423 | base = ARM_BASE_BCR + core_num_brps; | |
424 | } | |
425 | ||
f81ef4a9 WD |
426 | /* Reset the control register. */ |
427 | write_wb_reg(base + i, 0); | |
428 | } | |
429 | ||
430 | static int get_hbp_len(u8 hbp_len) | |
431 | { | |
432 | unsigned int len_in_bytes = 0; | |
433 | ||
434 | switch (hbp_len) { | |
435 | case ARM_BREAKPOINT_LEN_1: | |
436 | len_in_bytes = 1; | |
437 | break; | |
438 | case ARM_BREAKPOINT_LEN_2: | |
439 | len_in_bytes = 2; | |
440 | break; | |
441 | case ARM_BREAKPOINT_LEN_4: | |
442 | len_in_bytes = 4; | |
443 | break; | |
444 | case ARM_BREAKPOINT_LEN_8: | |
445 | len_in_bytes = 8; | |
446 | break; | |
447 | } | |
448 | ||
449 | return len_in_bytes; | |
450 | } | |
451 | ||
452 | /* | |
453 | * Check whether bp virtual address is in kernel space. | |
454 | */ | |
455 | int arch_check_bp_in_kernelspace(struct perf_event *bp) | |
456 | { | |
457 | unsigned int len; | |
458 | unsigned long va; | |
459 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
460 | ||
461 | va = info->address; | |
462 | len = get_hbp_len(info->ctrl.len); | |
463 | ||
464 | return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE); | |
465 | } | |
466 | ||
467 | /* | |
468 | * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl. | |
469 | * Hopefully this will disappear when ptrace can bypass the conversion | |
470 | * to generic breakpoint descriptions. | |
471 | */ | |
472 | int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, | |
473 | int *gen_len, int *gen_type) | |
474 | { | |
475 | /* Type */ | |
476 | switch (ctrl.type) { | |
477 | case ARM_BREAKPOINT_EXECUTE: | |
478 | *gen_type = HW_BREAKPOINT_X; | |
479 | break; | |
480 | case ARM_BREAKPOINT_LOAD: | |
481 | *gen_type = HW_BREAKPOINT_R; | |
482 | break; | |
483 | case ARM_BREAKPOINT_STORE: | |
484 | *gen_type = HW_BREAKPOINT_W; | |
485 | break; | |
486 | case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE: | |
487 | *gen_type = HW_BREAKPOINT_RW; | |
488 | break; | |
489 | default: | |
490 | return -EINVAL; | |
491 | } | |
492 | ||
493 | /* Len */ | |
494 | switch (ctrl.len) { | |
495 | case ARM_BREAKPOINT_LEN_1: | |
496 | *gen_len = HW_BREAKPOINT_LEN_1; | |
497 | break; | |
498 | case ARM_BREAKPOINT_LEN_2: | |
499 | *gen_len = HW_BREAKPOINT_LEN_2; | |
500 | break; | |
501 | case ARM_BREAKPOINT_LEN_4: | |
502 | *gen_len = HW_BREAKPOINT_LEN_4; | |
503 | break; | |
504 | case ARM_BREAKPOINT_LEN_8: | |
505 | *gen_len = HW_BREAKPOINT_LEN_8; | |
506 | break; | |
507 | default: | |
508 | return -EINVAL; | |
509 | } | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
514 | /* | |
515 | * Construct an arch_hw_breakpoint from a perf_event. | |
516 | */ | |
517 | static int arch_build_bp_info(struct perf_event *bp) | |
518 | { | |
519 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
520 | ||
521 | /* Type */ | |
522 | switch (bp->attr.bp_type) { | |
523 | case HW_BREAKPOINT_X: | |
524 | info->ctrl.type = ARM_BREAKPOINT_EXECUTE; | |
525 | break; | |
526 | case HW_BREAKPOINT_R: | |
527 | info->ctrl.type = ARM_BREAKPOINT_LOAD; | |
528 | break; | |
529 | case HW_BREAKPOINT_W: | |
530 | info->ctrl.type = ARM_BREAKPOINT_STORE; | |
531 | break; | |
532 | case HW_BREAKPOINT_RW: | |
533 | info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; | |
534 | break; | |
535 | default: | |
536 | return -EINVAL; | |
537 | } | |
538 | ||
539 | /* Len */ | |
540 | switch (bp->attr.bp_len) { | |
541 | case HW_BREAKPOINT_LEN_1: | |
542 | info->ctrl.len = ARM_BREAKPOINT_LEN_1; | |
543 | break; | |
544 | case HW_BREAKPOINT_LEN_2: | |
545 | info->ctrl.len = ARM_BREAKPOINT_LEN_2; | |
546 | break; | |
547 | case HW_BREAKPOINT_LEN_4: | |
548 | info->ctrl.len = ARM_BREAKPOINT_LEN_4; | |
549 | break; | |
550 | case HW_BREAKPOINT_LEN_8: | |
551 | info->ctrl.len = ARM_BREAKPOINT_LEN_8; | |
552 | if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE) | |
553 | && max_watchpoint_len >= 8) | |
554 | break; | |
555 | default: | |
556 | return -EINVAL; | |
557 | } | |
558 | ||
6ee33c27 WD |
559 | /* |
560 | * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes. | |
561 | * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported | |
562 | * by the hardware and must be aligned to the appropriate number of | |
563 | * bytes. | |
564 | */ | |
565 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE && | |
566 | info->ctrl.len != ARM_BREAKPOINT_LEN_2 && | |
567 | info->ctrl.len != ARM_BREAKPOINT_LEN_4) | |
568 | return -EINVAL; | |
569 | ||
f81ef4a9 WD |
570 | /* Address */ |
571 | info->address = bp->attr.bp_addr; | |
572 | ||
573 | /* Privilege */ | |
574 | info->ctrl.privilege = ARM_BREAKPOINT_USER; | |
93a04a34 | 575 | if (arch_check_bp_in_kernelspace(bp)) |
f81ef4a9 WD |
576 | info->ctrl.privilege |= ARM_BREAKPOINT_PRIV; |
577 | ||
578 | /* Enabled? */ | |
579 | info->ctrl.enabled = !bp->attr.disabled; | |
580 | ||
581 | /* Mismatch */ | |
582 | info->ctrl.mismatch = 0; | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
587 | /* | |
588 | * Validate the arch-specific HW Breakpoint register settings. | |
589 | */ | |
590 | int arch_validate_hwbkpt_settings(struct perf_event *bp) | |
591 | { | |
592 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
593 | int ret = 0; | |
6ee33c27 | 594 | u32 offset, alignment_mask = 0x3; |
f81ef4a9 | 595 | |
0daa034e WD |
596 | /* Ensure that we are in monitor debug mode. */ |
597 | if (!monitor_mode_enabled()) | |
598 | return -ENODEV; | |
599 | ||
f81ef4a9 WD |
600 | /* Build the arch_hw_breakpoint. */ |
601 | ret = arch_build_bp_info(bp); | |
602 | if (ret) | |
603 | goto out; | |
604 | ||
605 | /* Check address alignment. */ | |
606 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) | |
607 | alignment_mask = 0x7; | |
6ee33c27 WD |
608 | offset = info->address & alignment_mask; |
609 | switch (offset) { | |
610 | case 0: | |
611 | /* Aligned */ | |
612 | break; | |
613 | case 1: | |
6ee33c27 WD |
614 | case 2: |
615 | /* Allow halfword watchpoints and breakpoints. */ | |
616 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) | |
617 | break; | |
d968d2b8 WD |
618 | case 3: |
619 | /* Allow single byte watchpoint. */ | |
620 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) | |
621 | break; | |
6ee33c27 WD |
622 | default: |
623 | ret = -EINVAL; | |
624 | goto out; | |
f81ef4a9 WD |
625 | } |
626 | ||
6ee33c27 WD |
627 | info->address &= ~alignment_mask; |
628 | info->ctrl.len <<= offset; | |
629 | ||
bf880114 WD |
630 | if (!bp->overflow_handler) { |
631 | /* | |
632 | * Mismatch breakpoints are required for single-stepping | |
633 | * breakpoints. | |
634 | */ | |
635 | if (!core_has_mismatch_brps()) | |
636 | return -EINVAL; | |
637 | ||
638 | /* We don't allow mismatch breakpoints in kernel space. */ | |
639 | if (arch_check_bp_in_kernelspace(bp)) | |
640 | return -EPERM; | |
641 | ||
642 | /* | |
643 | * Per-cpu breakpoints are not supported by our stepping | |
644 | * mechanism. | |
645 | */ | |
646 | if (!bp->hw.bp_target) | |
647 | return -EINVAL; | |
648 | ||
649 | /* | |
650 | * We only support specific access types if the fsr | |
651 | * reports them. | |
652 | */ | |
653 | if (!debug_exception_updates_fsr() && | |
654 | (info->ctrl.type == ARM_BREAKPOINT_LOAD || | |
655 | info->ctrl.type == ARM_BREAKPOINT_STORE)) | |
656 | return -EINVAL; | |
f81ef4a9 | 657 | } |
bf880114 | 658 | |
f81ef4a9 WD |
659 | out: |
660 | return ret; | |
661 | } | |
662 | ||
9ebb3cbc WD |
663 | /* |
664 | * Enable/disable single-stepping over the breakpoint bp at address addr. | |
665 | */ | |
666 | static void enable_single_step(struct perf_event *bp, u32 addr) | |
f81ef4a9 | 667 | { |
9ebb3cbc | 668 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); |
f81ef4a9 | 669 | |
9ebb3cbc WD |
670 | arch_uninstall_hw_breakpoint(bp); |
671 | info->step_ctrl.mismatch = 1; | |
672 | info->step_ctrl.len = ARM_BREAKPOINT_LEN_4; | |
673 | info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE; | |
674 | info->step_ctrl.privilege = info->ctrl.privilege; | |
675 | info->step_ctrl.enabled = 1; | |
676 | info->trigger = addr; | |
677 | arch_install_hw_breakpoint(bp); | |
678 | } | |
f81ef4a9 | 679 | |
9ebb3cbc WD |
680 | static void disable_single_step(struct perf_event *bp) |
681 | { | |
682 | arch_uninstall_hw_breakpoint(bp); | |
683 | counter_arch_bp(bp)->step_ctrl.enabled = 0; | |
684 | arch_install_hw_breakpoint(bp); | |
f81ef4a9 WD |
685 | } |
686 | ||
6f26aa05 WD |
687 | static void watchpoint_handler(unsigned long addr, unsigned int fsr, |
688 | struct pt_regs *regs) | |
f81ef4a9 | 689 | { |
6f26aa05 WD |
690 | int i, access; |
691 | u32 val, ctrl_reg, alignment_mask; | |
4a55c18e | 692 | struct perf_event *wp, **slots; |
f81ef4a9 | 693 | struct arch_hw_breakpoint *info; |
6f26aa05 | 694 | struct arch_hw_breakpoint_ctrl ctrl; |
f81ef4a9 | 695 | |
4a55c18e WD |
696 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
697 | ||
f81ef4a9 WD |
698 | for (i = 0; i < core_num_wrps; ++i) { |
699 | rcu_read_lock(); | |
700 | ||
93a04a34 WD |
701 | wp = slots[i]; |
702 | ||
6f26aa05 WD |
703 | if (wp == NULL) |
704 | goto unlock; | |
f81ef4a9 | 705 | |
6f26aa05 | 706 | info = counter_arch_bp(wp); |
f81ef4a9 | 707 | /* |
6f26aa05 WD |
708 | * The DFAR is an unknown value on debug architectures prior |
709 | * to 7.1. Since we only allow a single watchpoint on these | |
710 | * older CPUs, we can set the trigger to the lowest possible | |
711 | * faulting address. | |
f81ef4a9 | 712 | */ |
6f26aa05 WD |
713 | if (debug_arch < ARM_DEBUG_ARCH_V7_1) { |
714 | BUG_ON(i > 0); | |
715 | info->trigger = wp->attr.bp_addr; | |
716 | } else { | |
717 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) | |
718 | alignment_mask = 0x7; | |
719 | else | |
720 | alignment_mask = 0x3; | |
721 | ||
722 | /* Check if the watchpoint value matches. */ | |
723 | val = read_wb_reg(ARM_BASE_WVR + i); | |
724 | if (val != (addr & ~alignment_mask)) | |
725 | goto unlock; | |
726 | ||
727 | /* Possible match, check the byte address select. */ | |
728 | ctrl_reg = read_wb_reg(ARM_BASE_WCR + i); | |
729 | decode_ctrl_reg(ctrl_reg, &ctrl); | |
730 | if (!((1 << (addr & alignment_mask)) & ctrl.len)) | |
731 | goto unlock; | |
732 | ||
733 | /* Check that the access type matches. */ | |
bf880114 WD |
734 | if (debug_exception_updates_fsr()) { |
735 | access = (fsr & ARM_FSR_ACCESS_MASK) ? | |
736 | HW_BREAKPOINT_W : HW_BREAKPOINT_R; | |
737 | if (!(access & hw_breakpoint_type(wp))) | |
738 | goto unlock; | |
739 | } | |
6f26aa05 WD |
740 | |
741 | /* We have a winner. */ | |
742 | info->trigger = addr; | |
743 | } | |
744 | ||
f81ef4a9 | 745 | pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); |
93a04a34 | 746 | perf_bp_event(wp, regs); |
f81ef4a9 WD |
747 | |
748 | /* | |
749 | * If no overflow handler is present, insert a temporary | |
750 | * mismatch breakpoint so we can single-step over the | |
751 | * watchpoint trigger. | |
752 | */ | |
9ebb3cbc WD |
753 | if (!wp->overflow_handler) |
754 | enable_single_step(wp, instruction_pointer(regs)); | |
f81ef4a9 | 755 | |
6f26aa05 | 756 | unlock: |
f81ef4a9 WD |
757 | rcu_read_unlock(); |
758 | } | |
759 | } | |
760 | ||
93a04a34 WD |
761 | static void watchpoint_single_step_handler(unsigned long pc) |
762 | { | |
763 | int i; | |
4a55c18e | 764 | struct perf_event *wp, **slots; |
93a04a34 WD |
765 | struct arch_hw_breakpoint *info; |
766 | ||
4a55c18e WD |
767 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
768 | ||
c512de95 | 769 | for (i = 0; i < core_num_wrps; ++i) { |
93a04a34 WD |
770 | rcu_read_lock(); |
771 | ||
772 | wp = slots[i]; | |
773 | ||
774 | if (wp == NULL) | |
775 | goto unlock; | |
776 | ||
777 | info = counter_arch_bp(wp); | |
778 | if (!info->step_ctrl.enabled) | |
779 | goto unlock; | |
780 | ||
781 | /* | |
782 | * Restore the original watchpoint if we've completed the | |
783 | * single-step. | |
784 | */ | |
9ebb3cbc WD |
785 | if (info->trigger != pc) |
786 | disable_single_step(wp); | |
93a04a34 WD |
787 | |
788 | unlock: | |
789 | rcu_read_unlock(); | |
790 | } | |
791 | } | |
792 | ||
f81ef4a9 WD |
793 | static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) |
794 | { | |
795 | int i; | |
f81ef4a9 | 796 | u32 ctrl_reg, val, addr; |
4a55c18e | 797 | struct perf_event *bp, **slots; |
f81ef4a9 WD |
798 | struct arch_hw_breakpoint *info; |
799 | struct arch_hw_breakpoint_ctrl ctrl; | |
800 | ||
4a55c18e WD |
801 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); |
802 | ||
f81ef4a9 WD |
803 | /* The exception entry code places the amended lr in the PC. */ |
804 | addr = regs->ARM_pc; | |
805 | ||
93a04a34 WD |
806 | /* Check the currently installed breakpoints first. */ |
807 | for (i = 0; i < core_num_brps; ++i) { | |
f81ef4a9 WD |
808 | rcu_read_lock(); |
809 | ||
810 | bp = slots[i]; | |
811 | ||
9ebb3cbc WD |
812 | if (bp == NULL) |
813 | goto unlock; | |
f81ef4a9 | 814 | |
9ebb3cbc | 815 | info = counter_arch_bp(bp); |
f81ef4a9 WD |
816 | |
817 | /* Check if the breakpoint value matches. */ | |
818 | val = read_wb_reg(ARM_BASE_BVR + i); | |
819 | if (val != (addr & ~0x3)) | |
9ebb3cbc | 820 | goto mismatch; |
f81ef4a9 WD |
821 | |
822 | /* Possible match, check the byte address select to confirm. */ | |
823 | ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); | |
824 | decode_ctrl_reg(ctrl_reg, &ctrl); | |
825 | if ((1 << (addr & 0x3)) & ctrl.len) { | |
f81ef4a9 | 826 | info->trigger = addr; |
f81ef4a9 WD |
827 | pr_debug("breakpoint fired: address = 0x%x\n", addr); |
828 | perf_bp_event(bp, regs); | |
9ebb3cbc WD |
829 | if (!bp->overflow_handler) |
830 | enable_single_step(bp, addr); | |
831 | goto unlock; | |
f81ef4a9 WD |
832 | } |
833 | ||
9ebb3cbc WD |
834 | mismatch: |
835 | /* If we're stepping a breakpoint, it can now be restored. */ | |
836 | if (info->step_ctrl.enabled) | |
837 | disable_single_step(bp); | |
838 | unlock: | |
f81ef4a9 WD |
839 | rcu_read_unlock(); |
840 | } | |
93a04a34 WD |
841 | |
842 | /* Handle any pending watchpoint single-step breakpoints. */ | |
843 | watchpoint_single_step_handler(addr); | |
f81ef4a9 WD |
844 | } |
845 | ||
846 | /* | |
847 | * Called from either the Data Abort Handler [watchpoint] or the | |
02fe2845 | 848 | * Prefetch Abort Handler [breakpoint] with interrupts disabled. |
f81ef4a9 WD |
849 | */ |
850 | static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, | |
851 | struct pt_regs *regs) | |
852 | { | |
7e202696 | 853 | int ret = 0; |
f81ef4a9 WD |
854 | u32 dscr; |
855 | ||
02fe2845 RK |
856 | preempt_disable(); |
857 | ||
858 | if (interrupts_enabled(regs)) | |
859 | local_irq_enable(); | |
7e202696 | 860 | |
f81ef4a9 | 861 | /* We only handle watchpoints and hardware breakpoints. */ |
9e962f76 | 862 | ARM_DBG_READ(c0, c1, 0, dscr); |
f81ef4a9 WD |
863 | |
864 | /* Perform perf callbacks. */ | |
865 | switch (ARM_DSCR_MOE(dscr)) { | |
866 | case ARM_ENTRY_BREAKPOINT: | |
867 | breakpoint_handler(addr, regs); | |
868 | break; | |
869 | case ARM_ENTRY_ASYNC_WATCHPOINT: | |
235584b6 | 870 | WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n"); |
f81ef4a9 | 871 | case ARM_ENTRY_SYNC_WATCHPOINT: |
6f26aa05 | 872 | watchpoint_handler(addr, fsr, regs); |
f81ef4a9 WD |
873 | break; |
874 | default: | |
7e202696 | 875 | ret = 1; /* Unhandled fault. */ |
f81ef4a9 WD |
876 | } |
877 | ||
7e202696 WD |
878 | preempt_enable(); |
879 | ||
f81ef4a9 WD |
880 | return ret; |
881 | } | |
882 | ||
883 | /* | |
884 | * One-time initialisation. | |
885 | */ | |
0d352e3d WD |
886 | static cpumask_t debug_err_mask; |
887 | ||
888 | static int debug_reg_trap(struct pt_regs *regs, unsigned int instr) | |
889 | { | |
890 | int cpu = smp_processor_id(); | |
891 | ||
892 | pr_warning("Debug register access (0x%x) caused undefined instruction on CPU %d\n", | |
893 | instr, cpu); | |
894 | ||
895 | /* Set the error flag for this CPU and skip the faulting instruction. */ | |
896 | cpumask_set_cpu(cpu, &debug_err_mask); | |
897 | instruction_pointer(regs) += 4; | |
898 | return 0; | |
899 | } | |
900 | ||
901 | static struct undef_hook debug_reg_hook = { | |
902 | .instr_mask = 0x0fe80f10, | |
903 | .instr_val = 0x0e000e10, | |
904 | .fn = debug_reg_trap, | |
905 | }; | |
906 | ||
907 | static void reset_ctrl_regs(void *unused) | |
f81ef4a9 | 908 | { |
c512de95 | 909 | int i, raw_num_brps, err = 0, cpu = smp_processor_id(); |
e64877dc | 910 | u32 val; |
f81ef4a9 | 911 | |
ac88e071 WD |
912 | /* |
913 | * v7 debug contains save and restore registers so that debug state | |
ed19b739 WD |
914 | * can be maintained across low-power modes without leaving the debug |
915 | * logic powered up. It is IMPLEMENTATION DEFINED whether we can access | |
916 | * the debug registers out of reset, so we must unlock the OS Lock | |
917 | * Access Register to avoid taking undefined instruction exceptions | |
918 | * later on. | |
ac88e071 | 919 | */ |
b5d5b8f9 | 920 | switch (debug_arch) { |
a26bce12 WD |
921 | case ARM_DEBUG_ARCH_V6: |
922 | case ARM_DEBUG_ARCH_V6_1: | |
7f4050a0 WD |
923 | /* ARMv6 cores clear the registers out of reset. */ |
924 | goto out_mdbgen; | |
b5d5b8f9 | 925 | case ARM_DEBUG_ARCH_V7_ECP14: |
c09bae70 WD |
926 | /* |
927 | * Ensure sticky power-down is clear (i.e. debug logic is | |
928 | * powered up). | |
929 | */ | |
9e962f76 | 930 | ARM_DBG_READ(c1, c5, 4, val); |
e64877dc | 931 | if ((val & 0x1) == 0) |
b5d5b8f9 | 932 | err = -EPERM; |
e64877dc WD |
933 | |
934 | /* | |
935 | * Check whether we implement OS save and restore. | |
936 | */ | |
9e962f76 | 937 | ARM_DBG_READ(c1, c1, 4, val); |
e64877dc WD |
938 | if ((val & 0x9) == 0) |
939 | goto clear_vcr; | |
b5d5b8f9 WD |
940 | break; |
941 | case ARM_DEBUG_ARCH_V7_1: | |
ac88e071 | 942 | /* |
b5d5b8f9 | 943 | * Ensure the OS double lock is clear. |
ac88e071 | 944 | */ |
9e962f76 | 945 | ARM_DBG_READ(c1, c3, 4, val); |
e64877dc | 946 | if ((val & 0x1) == 1) |
b5d5b8f9 WD |
947 | err = -EPERM; |
948 | break; | |
949 | } | |
e89c0d70 | 950 | |
b5d5b8f9 WD |
951 | if (err) { |
952 | pr_warning("CPU %d debug is powered down!\n", cpu); | |
0d352e3d | 953 | cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); |
b5d5b8f9 | 954 | return; |
ac88e071 WD |
955 | } |
956 | ||
b5d5b8f9 | 957 | /* |
e64877dc | 958 | * Unconditionally clear the OS lock by writing a value |
02051ead | 959 | * other than CS_LAR_KEY to the access register. |
b5d5b8f9 | 960 | */ |
02051ead | 961 | ARM_DBG_WRITE(c1, c0, 4, ~CS_LAR_KEY); |
b5d5b8f9 WD |
962 | isb(); |
963 | ||
964 | /* | |
965 | * Clear any configured vector-catch events before | |
966 | * enabling monitor mode. | |
967 | */ | |
e64877dc | 968 | clear_vcr: |
9e962f76 | 969 | ARM_DBG_WRITE(c0, c7, 0, 0); |
b5d5b8f9 WD |
970 | isb(); |
971 | ||
614bea50 WD |
972 | if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { |
973 | pr_warning("CPU %d failed to disable vector catch\n", cpu); | |
f81ef4a9 | 974 | return; |
614bea50 | 975 | } |
f81ef4a9 | 976 | |
614bea50 WD |
977 | /* |
978 | * The control/value register pairs are UNKNOWN out of reset so | |
979 | * clear them to avoid spurious debug events. | |
980 | */ | |
c512de95 WD |
981 | raw_num_brps = get_num_brp_resources(); |
982 | for (i = 0; i < raw_num_brps; ++i) { | |
f81ef4a9 WD |
983 | write_wb_reg(ARM_BASE_BCR + i, 0UL); |
984 | write_wb_reg(ARM_BASE_BVR + i, 0UL); | |
985 | } | |
986 | ||
987 | for (i = 0; i < core_num_wrps; ++i) { | |
988 | write_wb_reg(ARM_BASE_WCR + i, 0UL); | |
989 | write_wb_reg(ARM_BASE_WVR + i, 0UL); | |
990 | } | |
614bea50 WD |
991 | |
992 | if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { | |
993 | pr_warning("CPU %d failed to clear debug register pairs\n", cpu); | |
994 | return; | |
995 | } | |
996 | ||
997 | /* | |
998 | * Have a crack at enabling monitor mode. We don't actually need | |
999 | * it yet, but reporting an error early is useful if it fails. | |
1000 | */ | |
7f4050a0 | 1001 | out_mdbgen: |
614bea50 WD |
1002 | if (enable_monitor_mode()) |
1003 | cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); | |
f81ef4a9 WD |
1004 | } |
1005 | ||
7d99331e WD |
1006 | static int __cpuinit dbg_reset_notify(struct notifier_block *self, |
1007 | unsigned long action, void *cpu) | |
1008 | { | |
1009 | if (action == CPU_ONLINE) | |
1010 | smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1); | |
0d352e3d | 1011 | |
7d99331e WD |
1012 | return NOTIFY_OK; |
1013 | } | |
1014 | ||
1015 | static struct notifier_block __cpuinitdata dbg_reset_nb = { | |
1016 | .notifier_call = dbg_reset_notify, | |
1017 | }; | |
1018 | ||
f81ef4a9 WD |
1019 | static int __init arch_hw_breakpoint_init(void) |
1020 | { | |
f81ef4a9 WD |
1021 | debug_arch = get_debug_arch(); |
1022 | ||
66e1cfe6 | 1023 | if (!debug_arch_supported()) { |
f81ef4a9 | 1024 | pr_info("debug architecture 0x%x unsupported.\n", debug_arch); |
8fbf397c | 1025 | return 0; |
f81ef4a9 WD |
1026 | } |
1027 | ||
1028 | /* Determine how many BRPs/WRPs are available. */ | |
1029 | core_num_brps = get_num_brps(); | |
1030 | core_num_wrps = get_num_wrps(); | |
1031 | ||
0d352e3d WD |
1032 | /* |
1033 | * We need to tread carefully here because DBGSWENABLE may be | |
1034 | * driven low on this core and there isn't an architected way to | |
1035 | * determine that. | |
1036 | */ | |
1037 | register_undef_hook(&debug_reg_hook); | |
f81ef4a9 | 1038 | |
ed19b739 WD |
1039 | /* |
1040 | * Reset the breakpoint resources. We assume that a halting | |
1041 | * debugger will leave the world in a nice state for us. | |
1042 | */ | |
0d352e3d WD |
1043 | on_each_cpu(reset_ctrl_regs, NULL, 1); |
1044 | unregister_undef_hook(&debug_reg_hook); | |
1045 | if (!cpumask_empty(&debug_err_mask)) { | |
c09bae70 | 1046 | core_num_brps = 0; |
c09bae70 WD |
1047 | core_num_wrps = 0; |
1048 | return 0; | |
1049 | } | |
ed19b739 | 1050 | |
0d352e3d WD |
1051 | pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n", |
1052 | core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " : | |
1053 | "", core_num_wrps); | |
1054 | ||
b59a540c WD |
1055 | /* Work out the maximum supported watchpoint length. */ |
1056 | max_watchpoint_len = get_max_wp_len(); | |
1057 | pr_info("maximum watchpoint size is %u bytes.\n", | |
1058 | max_watchpoint_len); | |
f81ef4a9 WD |
1059 | |
1060 | /* Register debug fault handler. */ | |
f7b8156d CM |
1061 | hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP, |
1062 | TRAP_HWBKPT, "watchpoint debug exception"); | |
1063 | hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP, | |
1064 | TRAP_HWBKPT, "breakpoint debug exception"); | |
f81ef4a9 | 1065 | |
7d99331e WD |
1066 | /* Register hotplug notifier. */ |
1067 | register_cpu_notifier(&dbg_reset_nb); | |
8fbf397c | 1068 | return 0; |
f81ef4a9 WD |
1069 | } |
1070 | arch_initcall(arch_hw_breakpoint_init); | |
1071 | ||
1072 | void hw_breakpoint_pmu_read(struct perf_event *bp) | |
1073 | { | |
1074 | } | |
1075 | ||
1076 | /* | |
1077 | * Dummy function to register with die_notifier. | |
1078 | */ | |
1079 | int hw_breakpoint_exceptions_notify(struct notifier_block *unused, | |
1080 | unsigned long val, void *data) | |
1081 | { | |
1082 | return NOTIFY_DONE; | |
1083 | } |