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f81ef4a9 WD |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License version 2 as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public License | |
12 | * along with this program; if not, write to the Free Software | |
13 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
14 | * | |
15 | * Copyright (C) 2009, 2010 ARM Limited | |
16 | * | |
17 | * Author: Will Deacon <will.deacon@arm.com> | |
18 | */ | |
19 | ||
20 | /* | |
21 | * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, | |
22 | * using the CPU's debug registers. | |
23 | */ | |
24 | #define pr_fmt(fmt) "hw-breakpoint: " fmt | |
25 | ||
26 | #include <linux/errno.h> | |
7e202696 | 27 | #include <linux/hardirq.h> |
f81ef4a9 WD |
28 | #include <linux/perf_event.h> |
29 | #include <linux/hw_breakpoint.h> | |
30 | #include <linux/smp.h> | |
31 | ||
32 | #include <asm/cacheflush.h> | |
33 | #include <asm/cputype.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/hw_breakpoint.h> | |
36 | #include <asm/kdebug.h> | |
f81ef4a9 WD |
37 | #include <asm/traps.h> |
38 | ||
39 | /* Breakpoint currently in use for each BRP. */ | |
40 | static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); | |
41 | ||
42 | /* Watchpoint currently in use for each WRP. */ | |
43 | static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); | |
44 | ||
45 | /* Number of BRP/WRP registers on this CPU. */ | |
46 | static int core_num_brps; | |
47 | static int core_num_wrps; | |
48 | ||
49 | /* Debug architecture version. */ | |
50 | static u8 debug_arch; | |
51 | ||
52 | /* Maximum supported watchpoint length. */ | |
53 | static u8 max_watchpoint_len; | |
54 | ||
f81ef4a9 WD |
55 | #define READ_WB_REG_CASE(OP2, M, VAL) \ |
56 | case ((OP2 << 4) + M): \ | |
57 | ARM_DBG_READ(c ## M, OP2, VAL); \ | |
58 | break | |
59 | ||
60 | #define WRITE_WB_REG_CASE(OP2, M, VAL) \ | |
61 | case ((OP2 << 4) + M): \ | |
62 | ARM_DBG_WRITE(c ## M, OP2, VAL);\ | |
63 | break | |
64 | ||
65 | #define GEN_READ_WB_REG_CASES(OP2, VAL) \ | |
66 | READ_WB_REG_CASE(OP2, 0, VAL); \ | |
67 | READ_WB_REG_CASE(OP2, 1, VAL); \ | |
68 | READ_WB_REG_CASE(OP2, 2, VAL); \ | |
69 | READ_WB_REG_CASE(OP2, 3, VAL); \ | |
70 | READ_WB_REG_CASE(OP2, 4, VAL); \ | |
71 | READ_WB_REG_CASE(OP2, 5, VAL); \ | |
72 | READ_WB_REG_CASE(OP2, 6, VAL); \ | |
73 | READ_WB_REG_CASE(OP2, 7, VAL); \ | |
74 | READ_WB_REG_CASE(OP2, 8, VAL); \ | |
75 | READ_WB_REG_CASE(OP2, 9, VAL); \ | |
76 | READ_WB_REG_CASE(OP2, 10, VAL); \ | |
77 | READ_WB_REG_CASE(OP2, 11, VAL); \ | |
78 | READ_WB_REG_CASE(OP2, 12, VAL); \ | |
79 | READ_WB_REG_CASE(OP2, 13, VAL); \ | |
80 | READ_WB_REG_CASE(OP2, 14, VAL); \ | |
81 | READ_WB_REG_CASE(OP2, 15, VAL) | |
82 | ||
83 | #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \ | |
84 | WRITE_WB_REG_CASE(OP2, 0, VAL); \ | |
85 | WRITE_WB_REG_CASE(OP2, 1, VAL); \ | |
86 | WRITE_WB_REG_CASE(OP2, 2, VAL); \ | |
87 | WRITE_WB_REG_CASE(OP2, 3, VAL); \ | |
88 | WRITE_WB_REG_CASE(OP2, 4, VAL); \ | |
89 | WRITE_WB_REG_CASE(OP2, 5, VAL); \ | |
90 | WRITE_WB_REG_CASE(OP2, 6, VAL); \ | |
91 | WRITE_WB_REG_CASE(OP2, 7, VAL); \ | |
92 | WRITE_WB_REG_CASE(OP2, 8, VAL); \ | |
93 | WRITE_WB_REG_CASE(OP2, 9, VAL); \ | |
94 | WRITE_WB_REG_CASE(OP2, 10, VAL); \ | |
95 | WRITE_WB_REG_CASE(OP2, 11, VAL); \ | |
96 | WRITE_WB_REG_CASE(OP2, 12, VAL); \ | |
97 | WRITE_WB_REG_CASE(OP2, 13, VAL); \ | |
98 | WRITE_WB_REG_CASE(OP2, 14, VAL); \ | |
99 | WRITE_WB_REG_CASE(OP2, 15, VAL) | |
100 | ||
101 | static u32 read_wb_reg(int n) | |
102 | { | |
103 | u32 val = 0; | |
104 | ||
105 | switch (n) { | |
106 | GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val); | |
107 | GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val); | |
108 | GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val); | |
109 | GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val); | |
110 | default: | |
111 | pr_warning("attempt to read from unknown breakpoint " | |
112 | "register %d\n", n); | |
113 | } | |
114 | ||
115 | return val; | |
116 | } | |
117 | ||
118 | static void write_wb_reg(int n, u32 val) | |
119 | { | |
120 | switch (n) { | |
121 | GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val); | |
122 | GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val); | |
123 | GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val); | |
124 | GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val); | |
125 | default: | |
126 | pr_warning("attempt to write to unknown breakpoint " | |
127 | "register %d\n", n); | |
128 | } | |
129 | isb(); | |
130 | } | |
131 | ||
0017ff42 WD |
132 | /* Determine debug architecture. */ |
133 | static u8 get_debug_arch(void) | |
134 | { | |
135 | u32 didr; | |
136 | ||
137 | /* Do we implement the extended CPUID interface? */ | |
d1244336 WD |
138 | if (((read_cpuid_id() >> 16) & 0xf) != 0xf) { |
139 | pr_warning("CPUID feature registers not supported. " | |
140 | "Assuming v6 debug is present.\n"); | |
0017ff42 | 141 | return ARM_DEBUG_ARCH_V6; |
d1244336 | 142 | } |
0017ff42 WD |
143 | |
144 | ARM_DBG_READ(c0, 0, didr); | |
145 | return (didr >> 16) & 0xf; | |
146 | } | |
147 | ||
148 | u8 arch_get_debug_arch(void) | |
149 | { | |
150 | return debug_arch; | |
151 | } | |
152 | ||
66e1cfe6 WD |
153 | static int debug_arch_supported(void) |
154 | { | |
155 | u8 arch = get_debug_arch(); | |
b5d5b8f9 WD |
156 | |
157 | /* We don't support the memory-mapped interface. */ | |
158 | return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) || | |
159 | arch >= ARM_DEBUG_ARCH_V7_1; | |
66e1cfe6 WD |
160 | } |
161 | ||
bf880114 WD |
162 | /* Can we determine the watchpoint access type from the fsr? */ |
163 | static int debug_exception_updates_fsr(void) | |
164 | { | |
165 | return 0; | |
166 | } | |
167 | ||
c512de95 WD |
168 | /* Determine number of WRP registers available. */ |
169 | static int get_num_wrp_resources(void) | |
170 | { | |
171 | u32 didr; | |
172 | ARM_DBG_READ(c0, 0, didr); | |
173 | return ((didr >> 28) & 0xf) + 1; | |
174 | } | |
175 | ||
176 | /* Determine number of BRP registers available. */ | |
0017ff42 WD |
177 | static int get_num_brp_resources(void) |
178 | { | |
179 | u32 didr; | |
180 | ARM_DBG_READ(c0, 0, didr); | |
181 | return ((didr >> 24) & 0xf) + 1; | |
182 | } | |
183 | ||
184 | /* Does this core support mismatch breakpoints? */ | |
185 | static int core_has_mismatch_brps(void) | |
186 | { | |
187 | return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 && | |
188 | get_num_brp_resources() > 1); | |
189 | } | |
190 | ||
191 | /* Determine number of usable WRPs available. */ | |
192 | static int get_num_wrps(void) | |
193 | { | |
194 | /* | |
c512de95 WD |
195 | * On debug architectures prior to 7.1, when a watchpoint fires, the |
196 | * only way to work out which watchpoint it was is by disassembling | |
197 | * the faulting instruction and working out the address of the memory | |
198 | * access. | |
0017ff42 WD |
199 | * |
200 | * Furthermore, we can only do this if the watchpoint was precise | |
201 | * since imprecise watchpoints prevent us from calculating register | |
202 | * based addresses. | |
203 | * | |
204 | * Providing we have more than 1 breakpoint register, we only report | |
205 | * a single watchpoint register for the time being. This way, we always | |
206 | * know which watchpoint fired. In the future we can either add a | |
207 | * disassembler and address generation emulator, or we can insert a | |
208 | * check to see if the DFAR is set on watchpoint exception entry | |
209 | * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows | |
210 | * that it is set on some implementations]. | |
211 | */ | |
c512de95 WD |
212 | if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1) |
213 | return 1; | |
0017ff42 | 214 | |
c512de95 | 215 | return get_num_wrp_resources(); |
0017ff42 WD |
216 | } |
217 | ||
218 | /* Determine number of usable BRPs available. */ | |
219 | static int get_num_brps(void) | |
220 | { | |
221 | int brps = get_num_brp_resources(); | |
c512de95 | 222 | return core_has_mismatch_brps() ? brps - 1 : brps; |
0017ff42 WD |
223 | } |
224 | ||
f81ef4a9 WD |
225 | /* |
226 | * In order to access the breakpoint/watchpoint control registers, | |
227 | * we must be running in debug monitor mode. Unfortunately, we can | |
228 | * be put into halting debug mode at any time by an external debugger | |
229 | * but there is nothing we can do to prevent that. | |
230 | */ | |
231 | static int enable_monitor_mode(void) | |
232 | { | |
233 | u32 dscr; | |
234 | int ret = 0; | |
235 | ||
236 | ARM_DBG_READ(c1, 0, dscr); | |
237 | ||
8fbf397c WD |
238 | /* If monitor mode is already enabled, just return. */ |
239 | if (dscr & ARM_DSCR_MDBGEN) | |
240 | goto out; | |
241 | ||
f81ef4a9 | 242 | /* Write to the corresponding DSCR. */ |
8fbf397c | 243 | switch (get_debug_arch()) { |
f81ef4a9 WD |
244 | case ARM_DEBUG_ARCH_V6: |
245 | case ARM_DEBUG_ARCH_V6_1: | |
246 | ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN)); | |
247 | break; | |
248 | case ARM_DEBUG_ARCH_V7_ECP14: | |
b5d5b8f9 | 249 | case ARM_DEBUG_ARCH_V7_1: |
f81ef4a9 | 250 | ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN)); |
b59a540c | 251 | isb(); |
f81ef4a9 WD |
252 | break; |
253 | default: | |
254 | ret = -ENODEV; | |
255 | goto out; | |
256 | } | |
257 | ||
258 | /* Check that the write made it through. */ | |
259 | ARM_DBG_READ(c1, 0, dscr); | |
8fbf397c | 260 | if (!(dscr & ARM_DSCR_MDBGEN)) |
f81ef4a9 | 261 | ret = -EPERM; |
f81ef4a9 WD |
262 | |
263 | out: | |
264 | return ret; | |
265 | } | |
266 | ||
8fbf397c WD |
267 | int hw_breakpoint_slots(int type) |
268 | { | |
66e1cfe6 WD |
269 | if (!debug_arch_supported()) |
270 | return 0; | |
271 | ||
8fbf397c WD |
272 | /* |
273 | * We can be called early, so don't rely on | |
274 | * our static variables being initialised. | |
275 | */ | |
276 | switch (type) { | |
277 | case TYPE_INST: | |
278 | return get_num_brps(); | |
279 | case TYPE_DATA: | |
280 | return get_num_wrps(); | |
281 | default: | |
282 | pr_warning("unknown slot type: %d\n", type); | |
283 | return 0; | |
284 | } | |
285 | } | |
286 | ||
f81ef4a9 WD |
287 | /* |
288 | * Check if 8-bit byte-address select is available. | |
289 | * This clobbers WRP 0. | |
290 | */ | |
291 | static u8 get_max_wp_len(void) | |
292 | { | |
293 | u32 ctrl_reg; | |
294 | struct arch_hw_breakpoint_ctrl ctrl; | |
295 | u8 size = 4; | |
296 | ||
297 | if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14) | |
298 | goto out; | |
299 | ||
f81ef4a9 WD |
300 | memset(&ctrl, 0, sizeof(ctrl)); |
301 | ctrl.len = ARM_BREAKPOINT_LEN_8; | |
302 | ctrl_reg = encode_ctrl_reg(ctrl); | |
303 | ||
304 | write_wb_reg(ARM_BASE_WVR, 0); | |
305 | write_wb_reg(ARM_BASE_WCR, ctrl_reg); | |
306 | if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg) | |
307 | size = 8; | |
308 | ||
309 | out: | |
310 | return size; | |
311 | } | |
312 | ||
313 | u8 arch_get_max_wp_len(void) | |
314 | { | |
315 | return max_watchpoint_len; | |
316 | } | |
317 | ||
f81ef4a9 WD |
318 | /* |
319 | * Install a perf counter breakpoint. | |
320 | */ | |
321 | int arch_install_hw_breakpoint(struct perf_event *bp) | |
322 | { | |
323 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
324 | struct perf_event **slot, **slots; | |
325 | int i, max_slots, ctrl_base, val_base, ret = 0; | |
93a04a34 | 326 | u32 addr, ctrl; |
f81ef4a9 WD |
327 | |
328 | /* Ensure that we are in monitor mode and halting mode is disabled. */ | |
329 | ret = enable_monitor_mode(); | |
330 | if (ret) | |
331 | goto out; | |
332 | ||
93a04a34 WD |
333 | addr = info->address; |
334 | ctrl = encode_ctrl_reg(info->ctrl) | 0x1; | |
335 | ||
f81ef4a9 WD |
336 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { |
337 | /* Breakpoint */ | |
338 | ctrl_base = ARM_BASE_BCR; | |
339 | val_base = ARM_BASE_BVR; | |
4a55c18e | 340 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); |
0017ff42 | 341 | max_slots = core_num_brps; |
f81ef4a9 WD |
342 | } else { |
343 | /* Watchpoint */ | |
6f26aa05 WD |
344 | ctrl_base = ARM_BASE_WCR; |
345 | val_base = ARM_BASE_WVR; | |
4a55c18e | 346 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
f81ef4a9 WD |
347 | max_slots = core_num_wrps; |
348 | } | |
349 | ||
350 | for (i = 0; i < max_slots; ++i) { | |
351 | slot = &slots[i]; | |
352 | ||
353 | if (!*slot) { | |
354 | *slot = bp; | |
355 | break; | |
356 | } | |
357 | } | |
358 | ||
7d85d61f | 359 | if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n")) { |
f81ef4a9 WD |
360 | ret = -EBUSY; |
361 | goto out; | |
362 | } | |
363 | ||
6f26aa05 WD |
364 | /* Override the breakpoint data with the step data. */ |
365 | if (info->step_ctrl.enabled) { | |
366 | addr = info->trigger & ~0x3; | |
367 | ctrl = encode_ctrl_reg(info->step_ctrl); | |
368 | if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) { | |
369 | i = 0; | |
370 | ctrl_base = ARM_BASE_BCR + core_num_brps; | |
371 | val_base = ARM_BASE_BVR + core_num_brps; | |
372 | } | |
373 | } | |
374 | ||
f81ef4a9 | 375 | /* Setup the address register. */ |
93a04a34 | 376 | write_wb_reg(val_base + i, addr); |
f81ef4a9 WD |
377 | |
378 | /* Setup the control register. */ | |
93a04a34 | 379 | write_wb_reg(ctrl_base + i, ctrl); |
f81ef4a9 WD |
380 | |
381 | out: | |
382 | return ret; | |
383 | } | |
384 | ||
385 | void arch_uninstall_hw_breakpoint(struct perf_event *bp) | |
386 | { | |
387 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
388 | struct perf_event **slot, **slots; | |
389 | int i, max_slots, base; | |
390 | ||
391 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { | |
392 | /* Breakpoint */ | |
393 | base = ARM_BASE_BCR; | |
4a55c18e | 394 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); |
0017ff42 | 395 | max_slots = core_num_brps; |
f81ef4a9 WD |
396 | } else { |
397 | /* Watchpoint */ | |
6f26aa05 | 398 | base = ARM_BASE_WCR; |
4a55c18e | 399 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
f81ef4a9 WD |
400 | max_slots = core_num_wrps; |
401 | } | |
402 | ||
403 | /* Remove the breakpoint. */ | |
404 | for (i = 0; i < max_slots; ++i) { | |
405 | slot = &slots[i]; | |
406 | ||
407 | if (*slot == bp) { | |
408 | *slot = NULL; | |
409 | break; | |
410 | } | |
411 | } | |
412 | ||
7d85d61f | 413 | if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n")) |
f81ef4a9 WD |
414 | return; |
415 | ||
6f26aa05 WD |
416 | /* Ensure that we disable the mismatch breakpoint. */ |
417 | if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE && | |
418 | info->step_ctrl.enabled) { | |
419 | i = 0; | |
420 | base = ARM_BASE_BCR + core_num_brps; | |
421 | } | |
422 | ||
f81ef4a9 WD |
423 | /* Reset the control register. */ |
424 | write_wb_reg(base + i, 0); | |
425 | } | |
426 | ||
427 | static int get_hbp_len(u8 hbp_len) | |
428 | { | |
429 | unsigned int len_in_bytes = 0; | |
430 | ||
431 | switch (hbp_len) { | |
432 | case ARM_BREAKPOINT_LEN_1: | |
433 | len_in_bytes = 1; | |
434 | break; | |
435 | case ARM_BREAKPOINT_LEN_2: | |
436 | len_in_bytes = 2; | |
437 | break; | |
438 | case ARM_BREAKPOINT_LEN_4: | |
439 | len_in_bytes = 4; | |
440 | break; | |
441 | case ARM_BREAKPOINT_LEN_8: | |
442 | len_in_bytes = 8; | |
443 | break; | |
444 | } | |
445 | ||
446 | return len_in_bytes; | |
447 | } | |
448 | ||
449 | /* | |
450 | * Check whether bp virtual address is in kernel space. | |
451 | */ | |
452 | int arch_check_bp_in_kernelspace(struct perf_event *bp) | |
453 | { | |
454 | unsigned int len; | |
455 | unsigned long va; | |
456 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
457 | ||
458 | va = info->address; | |
459 | len = get_hbp_len(info->ctrl.len); | |
460 | ||
461 | return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE); | |
462 | } | |
463 | ||
464 | /* | |
465 | * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl. | |
466 | * Hopefully this will disappear when ptrace can bypass the conversion | |
467 | * to generic breakpoint descriptions. | |
468 | */ | |
469 | int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, | |
470 | int *gen_len, int *gen_type) | |
471 | { | |
472 | /* Type */ | |
473 | switch (ctrl.type) { | |
474 | case ARM_BREAKPOINT_EXECUTE: | |
475 | *gen_type = HW_BREAKPOINT_X; | |
476 | break; | |
477 | case ARM_BREAKPOINT_LOAD: | |
478 | *gen_type = HW_BREAKPOINT_R; | |
479 | break; | |
480 | case ARM_BREAKPOINT_STORE: | |
481 | *gen_type = HW_BREAKPOINT_W; | |
482 | break; | |
483 | case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE: | |
484 | *gen_type = HW_BREAKPOINT_RW; | |
485 | break; | |
486 | default: | |
487 | return -EINVAL; | |
488 | } | |
489 | ||
490 | /* Len */ | |
491 | switch (ctrl.len) { | |
492 | case ARM_BREAKPOINT_LEN_1: | |
493 | *gen_len = HW_BREAKPOINT_LEN_1; | |
494 | break; | |
495 | case ARM_BREAKPOINT_LEN_2: | |
496 | *gen_len = HW_BREAKPOINT_LEN_2; | |
497 | break; | |
498 | case ARM_BREAKPOINT_LEN_4: | |
499 | *gen_len = HW_BREAKPOINT_LEN_4; | |
500 | break; | |
501 | case ARM_BREAKPOINT_LEN_8: | |
502 | *gen_len = HW_BREAKPOINT_LEN_8; | |
503 | break; | |
504 | default: | |
505 | return -EINVAL; | |
506 | } | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
511 | /* | |
512 | * Construct an arch_hw_breakpoint from a perf_event. | |
513 | */ | |
514 | static int arch_build_bp_info(struct perf_event *bp) | |
515 | { | |
516 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
517 | ||
518 | /* Type */ | |
519 | switch (bp->attr.bp_type) { | |
520 | case HW_BREAKPOINT_X: | |
521 | info->ctrl.type = ARM_BREAKPOINT_EXECUTE; | |
522 | break; | |
523 | case HW_BREAKPOINT_R: | |
524 | info->ctrl.type = ARM_BREAKPOINT_LOAD; | |
525 | break; | |
526 | case HW_BREAKPOINT_W: | |
527 | info->ctrl.type = ARM_BREAKPOINT_STORE; | |
528 | break; | |
529 | case HW_BREAKPOINT_RW: | |
530 | info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; | |
531 | break; | |
532 | default: | |
533 | return -EINVAL; | |
534 | } | |
535 | ||
536 | /* Len */ | |
537 | switch (bp->attr.bp_len) { | |
538 | case HW_BREAKPOINT_LEN_1: | |
539 | info->ctrl.len = ARM_BREAKPOINT_LEN_1; | |
540 | break; | |
541 | case HW_BREAKPOINT_LEN_2: | |
542 | info->ctrl.len = ARM_BREAKPOINT_LEN_2; | |
543 | break; | |
544 | case HW_BREAKPOINT_LEN_4: | |
545 | info->ctrl.len = ARM_BREAKPOINT_LEN_4; | |
546 | break; | |
547 | case HW_BREAKPOINT_LEN_8: | |
548 | info->ctrl.len = ARM_BREAKPOINT_LEN_8; | |
549 | if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE) | |
550 | && max_watchpoint_len >= 8) | |
551 | break; | |
552 | default: | |
553 | return -EINVAL; | |
554 | } | |
555 | ||
6ee33c27 WD |
556 | /* |
557 | * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes. | |
558 | * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported | |
559 | * by the hardware and must be aligned to the appropriate number of | |
560 | * bytes. | |
561 | */ | |
562 | if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE && | |
563 | info->ctrl.len != ARM_BREAKPOINT_LEN_2 && | |
564 | info->ctrl.len != ARM_BREAKPOINT_LEN_4) | |
565 | return -EINVAL; | |
566 | ||
f81ef4a9 WD |
567 | /* Address */ |
568 | info->address = bp->attr.bp_addr; | |
569 | ||
570 | /* Privilege */ | |
571 | info->ctrl.privilege = ARM_BREAKPOINT_USER; | |
93a04a34 | 572 | if (arch_check_bp_in_kernelspace(bp)) |
f81ef4a9 WD |
573 | info->ctrl.privilege |= ARM_BREAKPOINT_PRIV; |
574 | ||
575 | /* Enabled? */ | |
576 | info->ctrl.enabled = !bp->attr.disabled; | |
577 | ||
578 | /* Mismatch */ | |
579 | info->ctrl.mismatch = 0; | |
580 | ||
581 | return 0; | |
582 | } | |
583 | ||
584 | /* | |
585 | * Validate the arch-specific HW Breakpoint register settings. | |
586 | */ | |
587 | int arch_validate_hwbkpt_settings(struct perf_event *bp) | |
588 | { | |
589 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); | |
590 | int ret = 0; | |
6ee33c27 | 591 | u32 offset, alignment_mask = 0x3; |
f81ef4a9 WD |
592 | |
593 | /* Build the arch_hw_breakpoint. */ | |
594 | ret = arch_build_bp_info(bp); | |
595 | if (ret) | |
596 | goto out; | |
597 | ||
598 | /* Check address alignment. */ | |
599 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) | |
600 | alignment_mask = 0x7; | |
6ee33c27 WD |
601 | offset = info->address & alignment_mask; |
602 | switch (offset) { | |
603 | case 0: | |
604 | /* Aligned */ | |
605 | break; | |
606 | case 1: | |
6ee33c27 WD |
607 | case 2: |
608 | /* Allow halfword watchpoints and breakpoints. */ | |
609 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) | |
610 | break; | |
d968d2b8 WD |
611 | case 3: |
612 | /* Allow single byte watchpoint. */ | |
613 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) | |
614 | break; | |
6ee33c27 WD |
615 | default: |
616 | ret = -EINVAL; | |
617 | goto out; | |
f81ef4a9 WD |
618 | } |
619 | ||
6ee33c27 WD |
620 | info->address &= ~alignment_mask; |
621 | info->ctrl.len <<= offset; | |
622 | ||
bf880114 WD |
623 | if (!bp->overflow_handler) { |
624 | /* | |
625 | * Mismatch breakpoints are required for single-stepping | |
626 | * breakpoints. | |
627 | */ | |
628 | if (!core_has_mismatch_brps()) | |
629 | return -EINVAL; | |
630 | ||
631 | /* We don't allow mismatch breakpoints in kernel space. */ | |
632 | if (arch_check_bp_in_kernelspace(bp)) | |
633 | return -EPERM; | |
634 | ||
635 | /* | |
636 | * Per-cpu breakpoints are not supported by our stepping | |
637 | * mechanism. | |
638 | */ | |
639 | if (!bp->hw.bp_target) | |
640 | return -EINVAL; | |
641 | ||
642 | /* | |
643 | * We only support specific access types if the fsr | |
644 | * reports them. | |
645 | */ | |
646 | if (!debug_exception_updates_fsr() && | |
647 | (info->ctrl.type == ARM_BREAKPOINT_LOAD || | |
648 | info->ctrl.type == ARM_BREAKPOINT_STORE)) | |
649 | return -EINVAL; | |
f81ef4a9 | 650 | } |
bf880114 | 651 | |
f81ef4a9 WD |
652 | out: |
653 | return ret; | |
654 | } | |
655 | ||
9ebb3cbc WD |
656 | /* |
657 | * Enable/disable single-stepping over the breakpoint bp at address addr. | |
658 | */ | |
659 | static void enable_single_step(struct perf_event *bp, u32 addr) | |
f81ef4a9 | 660 | { |
9ebb3cbc | 661 | struct arch_hw_breakpoint *info = counter_arch_bp(bp); |
f81ef4a9 | 662 | |
9ebb3cbc WD |
663 | arch_uninstall_hw_breakpoint(bp); |
664 | info->step_ctrl.mismatch = 1; | |
665 | info->step_ctrl.len = ARM_BREAKPOINT_LEN_4; | |
666 | info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE; | |
667 | info->step_ctrl.privilege = info->ctrl.privilege; | |
668 | info->step_ctrl.enabled = 1; | |
669 | info->trigger = addr; | |
670 | arch_install_hw_breakpoint(bp); | |
671 | } | |
f81ef4a9 | 672 | |
9ebb3cbc WD |
673 | static void disable_single_step(struct perf_event *bp) |
674 | { | |
675 | arch_uninstall_hw_breakpoint(bp); | |
676 | counter_arch_bp(bp)->step_ctrl.enabled = 0; | |
677 | arch_install_hw_breakpoint(bp); | |
f81ef4a9 WD |
678 | } |
679 | ||
6f26aa05 WD |
680 | static void watchpoint_handler(unsigned long addr, unsigned int fsr, |
681 | struct pt_regs *regs) | |
f81ef4a9 | 682 | { |
6f26aa05 WD |
683 | int i, access; |
684 | u32 val, ctrl_reg, alignment_mask; | |
4a55c18e | 685 | struct perf_event *wp, **slots; |
f81ef4a9 | 686 | struct arch_hw_breakpoint *info; |
6f26aa05 | 687 | struct arch_hw_breakpoint_ctrl ctrl; |
f81ef4a9 | 688 | |
4a55c18e WD |
689 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
690 | ||
f81ef4a9 WD |
691 | for (i = 0; i < core_num_wrps; ++i) { |
692 | rcu_read_lock(); | |
693 | ||
93a04a34 WD |
694 | wp = slots[i]; |
695 | ||
6f26aa05 WD |
696 | if (wp == NULL) |
697 | goto unlock; | |
f81ef4a9 | 698 | |
6f26aa05 | 699 | info = counter_arch_bp(wp); |
f81ef4a9 | 700 | /* |
6f26aa05 WD |
701 | * The DFAR is an unknown value on debug architectures prior |
702 | * to 7.1. Since we only allow a single watchpoint on these | |
703 | * older CPUs, we can set the trigger to the lowest possible | |
704 | * faulting address. | |
f81ef4a9 | 705 | */ |
6f26aa05 WD |
706 | if (debug_arch < ARM_DEBUG_ARCH_V7_1) { |
707 | BUG_ON(i > 0); | |
708 | info->trigger = wp->attr.bp_addr; | |
709 | } else { | |
710 | if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) | |
711 | alignment_mask = 0x7; | |
712 | else | |
713 | alignment_mask = 0x3; | |
714 | ||
715 | /* Check if the watchpoint value matches. */ | |
716 | val = read_wb_reg(ARM_BASE_WVR + i); | |
717 | if (val != (addr & ~alignment_mask)) | |
718 | goto unlock; | |
719 | ||
720 | /* Possible match, check the byte address select. */ | |
721 | ctrl_reg = read_wb_reg(ARM_BASE_WCR + i); | |
722 | decode_ctrl_reg(ctrl_reg, &ctrl); | |
723 | if (!((1 << (addr & alignment_mask)) & ctrl.len)) | |
724 | goto unlock; | |
725 | ||
726 | /* Check that the access type matches. */ | |
bf880114 WD |
727 | if (debug_exception_updates_fsr()) { |
728 | access = (fsr & ARM_FSR_ACCESS_MASK) ? | |
729 | HW_BREAKPOINT_W : HW_BREAKPOINT_R; | |
730 | if (!(access & hw_breakpoint_type(wp))) | |
731 | goto unlock; | |
732 | } | |
6f26aa05 WD |
733 | |
734 | /* We have a winner. */ | |
735 | info->trigger = addr; | |
736 | } | |
737 | ||
f81ef4a9 | 738 | pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); |
93a04a34 | 739 | perf_bp_event(wp, regs); |
f81ef4a9 WD |
740 | |
741 | /* | |
742 | * If no overflow handler is present, insert a temporary | |
743 | * mismatch breakpoint so we can single-step over the | |
744 | * watchpoint trigger. | |
745 | */ | |
9ebb3cbc WD |
746 | if (!wp->overflow_handler) |
747 | enable_single_step(wp, instruction_pointer(regs)); | |
f81ef4a9 | 748 | |
6f26aa05 | 749 | unlock: |
f81ef4a9 WD |
750 | rcu_read_unlock(); |
751 | } | |
752 | } | |
753 | ||
93a04a34 WD |
754 | static void watchpoint_single_step_handler(unsigned long pc) |
755 | { | |
756 | int i; | |
4a55c18e | 757 | struct perf_event *wp, **slots; |
93a04a34 WD |
758 | struct arch_hw_breakpoint *info; |
759 | ||
4a55c18e WD |
760 | slots = (struct perf_event **)__get_cpu_var(wp_on_reg); |
761 | ||
c512de95 | 762 | for (i = 0; i < core_num_wrps; ++i) { |
93a04a34 WD |
763 | rcu_read_lock(); |
764 | ||
765 | wp = slots[i]; | |
766 | ||
767 | if (wp == NULL) | |
768 | goto unlock; | |
769 | ||
770 | info = counter_arch_bp(wp); | |
771 | if (!info->step_ctrl.enabled) | |
772 | goto unlock; | |
773 | ||
774 | /* | |
775 | * Restore the original watchpoint if we've completed the | |
776 | * single-step. | |
777 | */ | |
9ebb3cbc WD |
778 | if (info->trigger != pc) |
779 | disable_single_step(wp); | |
93a04a34 WD |
780 | |
781 | unlock: | |
782 | rcu_read_unlock(); | |
783 | } | |
784 | } | |
785 | ||
f81ef4a9 WD |
786 | static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) |
787 | { | |
788 | int i; | |
f81ef4a9 | 789 | u32 ctrl_reg, val, addr; |
4a55c18e | 790 | struct perf_event *bp, **slots; |
f81ef4a9 WD |
791 | struct arch_hw_breakpoint *info; |
792 | struct arch_hw_breakpoint_ctrl ctrl; | |
793 | ||
4a55c18e WD |
794 | slots = (struct perf_event **)__get_cpu_var(bp_on_reg); |
795 | ||
f81ef4a9 WD |
796 | /* The exception entry code places the amended lr in the PC. */ |
797 | addr = regs->ARM_pc; | |
798 | ||
93a04a34 WD |
799 | /* Check the currently installed breakpoints first. */ |
800 | for (i = 0; i < core_num_brps; ++i) { | |
f81ef4a9 WD |
801 | rcu_read_lock(); |
802 | ||
803 | bp = slots[i]; | |
804 | ||
9ebb3cbc WD |
805 | if (bp == NULL) |
806 | goto unlock; | |
f81ef4a9 | 807 | |
9ebb3cbc | 808 | info = counter_arch_bp(bp); |
f81ef4a9 WD |
809 | |
810 | /* Check if the breakpoint value matches. */ | |
811 | val = read_wb_reg(ARM_BASE_BVR + i); | |
812 | if (val != (addr & ~0x3)) | |
9ebb3cbc | 813 | goto mismatch; |
f81ef4a9 WD |
814 | |
815 | /* Possible match, check the byte address select to confirm. */ | |
816 | ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); | |
817 | decode_ctrl_reg(ctrl_reg, &ctrl); | |
818 | if ((1 << (addr & 0x3)) & ctrl.len) { | |
f81ef4a9 | 819 | info->trigger = addr; |
f81ef4a9 WD |
820 | pr_debug("breakpoint fired: address = 0x%x\n", addr); |
821 | perf_bp_event(bp, regs); | |
9ebb3cbc WD |
822 | if (!bp->overflow_handler) |
823 | enable_single_step(bp, addr); | |
824 | goto unlock; | |
f81ef4a9 WD |
825 | } |
826 | ||
9ebb3cbc WD |
827 | mismatch: |
828 | /* If we're stepping a breakpoint, it can now be restored. */ | |
829 | if (info->step_ctrl.enabled) | |
830 | disable_single_step(bp); | |
831 | unlock: | |
f81ef4a9 WD |
832 | rcu_read_unlock(); |
833 | } | |
93a04a34 WD |
834 | |
835 | /* Handle any pending watchpoint single-step breakpoints. */ | |
836 | watchpoint_single_step_handler(addr); | |
f81ef4a9 WD |
837 | } |
838 | ||
839 | /* | |
840 | * Called from either the Data Abort Handler [watchpoint] or the | |
02fe2845 | 841 | * Prefetch Abort Handler [breakpoint] with interrupts disabled. |
f81ef4a9 WD |
842 | */ |
843 | static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, | |
844 | struct pt_regs *regs) | |
845 | { | |
7e202696 | 846 | int ret = 0; |
f81ef4a9 WD |
847 | u32 dscr; |
848 | ||
02fe2845 RK |
849 | preempt_disable(); |
850 | ||
851 | if (interrupts_enabled(regs)) | |
852 | local_irq_enable(); | |
7e202696 | 853 | |
f81ef4a9 WD |
854 | /* We only handle watchpoints and hardware breakpoints. */ |
855 | ARM_DBG_READ(c1, 0, dscr); | |
856 | ||
857 | /* Perform perf callbacks. */ | |
858 | switch (ARM_DSCR_MOE(dscr)) { | |
859 | case ARM_ENTRY_BREAKPOINT: | |
860 | breakpoint_handler(addr, regs); | |
861 | break; | |
862 | case ARM_ENTRY_ASYNC_WATCHPOINT: | |
235584b6 | 863 | WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n"); |
f81ef4a9 | 864 | case ARM_ENTRY_SYNC_WATCHPOINT: |
6f26aa05 | 865 | watchpoint_handler(addr, fsr, regs); |
f81ef4a9 WD |
866 | break; |
867 | default: | |
7e202696 | 868 | ret = 1; /* Unhandled fault. */ |
f81ef4a9 WD |
869 | } |
870 | ||
7e202696 WD |
871 | preempt_enable(); |
872 | ||
f81ef4a9 WD |
873 | return ret; |
874 | } | |
875 | ||
876 | /* | |
877 | * One-time initialisation. | |
878 | */ | |
0d352e3d WD |
879 | static cpumask_t debug_err_mask; |
880 | ||
881 | static int debug_reg_trap(struct pt_regs *regs, unsigned int instr) | |
882 | { | |
883 | int cpu = smp_processor_id(); | |
884 | ||
885 | pr_warning("Debug register access (0x%x) caused undefined instruction on CPU %d\n", | |
886 | instr, cpu); | |
887 | ||
888 | /* Set the error flag for this CPU and skip the faulting instruction. */ | |
889 | cpumask_set_cpu(cpu, &debug_err_mask); | |
890 | instruction_pointer(regs) += 4; | |
891 | return 0; | |
892 | } | |
893 | ||
894 | static struct undef_hook debug_reg_hook = { | |
895 | .instr_mask = 0x0fe80f10, | |
896 | .instr_val = 0x0e000e10, | |
897 | .fn = debug_reg_trap, | |
898 | }; | |
899 | ||
900 | static void reset_ctrl_regs(void *unused) | |
f81ef4a9 | 901 | { |
c512de95 | 902 | int i, raw_num_brps, err = 0, cpu = smp_processor_id(); |
e64877dc | 903 | u32 val; |
f81ef4a9 | 904 | |
ac88e071 WD |
905 | /* |
906 | * v7 debug contains save and restore registers so that debug state | |
ed19b739 WD |
907 | * can be maintained across low-power modes without leaving the debug |
908 | * logic powered up. It is IMPLEMENTATION DEFINED whether we can access | |
909 | * the debug registers out of reset, so we must unlock the OS Lock | |
910 | * Access Register to avoid taking undefined instruction exceptions | |
911 | * later on. | |
ac88e071 | 912 | */ |
b5d5b8f9 | 913 | switch (debug_arch) { |
a26bce12 WD |
914 | case ARM_DEBUG_ARCH_V6: |
915 | case ARM_DEBUG_ARCH_V6_1: | |
916 | /* ARMv6 cores just need to reset the registers. */ | |
917 | goto reset_regs; | |
b5d5b8f9 | 918 | case ARM_DEBUG_ARCH_V7_ECP14: |
c09bae70 WD |
919 | /* |
920 | * Ensure sticky power-down is clear (i.e. debug logic is | |
921 | * powered up). | |
922 | */ | |
e64877dc WD |
923 | asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (val)); |
924 | if ((val & 0x1) == 0) | |
b5d5b8f9 | 925 | err = -EPERM; |
e64877dc WD |
926 | |
927 | /* | |
928 | * Check whether we implement OS save and restore. | |
929 | */ | |
930 | asm volatile("mrc p14, 0, %0, c1, c1, 4" : "=r" (val)); | |
931 | if ((val & 0x9) == 0) | |
932 | goto clear_vcr; | |
b5d5b8f9 WD |
933 | break; |
934 | case ARM_DEBUG_ARCH_V7_1: | |
ac88e071 | 935 | /* |
b5d5b8f9 | 936 | * Ensure the OS double lock is clear. |
ac88e071 | 937 | */ |
e64877dc WD |
938 | asm volatile("mrc p14, 0, %0, c1, c3, 4" : "=r" (val)); |
939 | if ((val & 0x1) == 1) | |
b5d5b8f9 WD |
940 | err = -EPERM; |
941 | break; | |
942 | } | |
e89c0d70 | 943 | |
b5d5b8f9 WD |
944 | if (err) { |
945 | pr_warning("CPU %d debug is powered down!\n", cpu); | |
0d352e3d | 946 | cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); |
b5d5b8f9 | 947 | return; |
ac88e071 WD |
948 | } |
949 | ||
b5d5b8f9 | 950 | /* |
e64877dc | 951 | * Unconditionally clear the OS lock by writing a value |
b5d5b8f9 WD |
952 | * other than 0xC5ACCE55 to the access register. |
953 | */ | |
954 | asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0)); | |
955 | isb(); | |
956 | ||
957 | /* | |
958 | * Clear any configured vector-catch events before | |
959 | * enabling monitor mode. | |
960 | */ | |
e64877dc | 961 | clear_vcr: |
b5d5b8f9 WD |
962 | asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0)); |
963 | isb(); | |
964 | ||
a26bce12 | 965 | reset_regs: |
f81ef4a9 WD |
966 | if (enable_monitor_mode()) |
967 | return; | |
968 | ||
0017ff42 | 969 | /* We must also reset any reserved registers. */ |
c512de95 WD |
970 | raw_num_brps = get_num_brp_resources(); |
971 | for (i = 0; i < raw_num_brps; ++i) { | |
f81ef4a9 WD |
972 | write_wb_reg(ARM_BASE_BCR + i, 0UL); |
973 | write_wb_reg(ARM_BASE_BVR + i, 0UL); | |
974 | } | |
975 | ||
976 | for (i = 0; i < core_num_wrps; ++i) { | |
977 | write_wb_reg(ARM_BASE_WCR + i, 0UL); | |
978 | write_wb_reg(ARM_BASE_WVR + i, 0UL); | |
979 | } | |
980 | } | |
981 | ||
7d99331e WD |
982 | static int __cpuinit dbg_reset_notify(struct notifier_block *self, |
983 | unsigned long action, void *cpu) | |
984 | { | |
985 | if (action == CPU_ONLINE) | |
986 | smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1); | |
0d352e3d | 987 | |
7d99331e WD |
988 | return NOTIFY_OK; |
989 | } | |
990 | ||
991 | static struct notifier_block __cpuinitdata dbg_reset_nb = { | |
992 | .notifier_call = dbg_reset_notify, | |
993 | }; | |
994 | ||
f81ef4a9 WD |
995 | static int __init arch_hw_breakpoint_init(void) |
996 | { | |
f81ef4a9 WD |
997 | debug_arch = get_debug_arch(); |
998 | ||
66e1cfe6 | 999 | if (!debug_arch_supported()) { |
f81ef4a9 | 1000 | pr_info("debug architecture 0x%x unsupported.\n", debug_arch); |
8fbf397c | 1001 | return 0; |
f81ef4a9 WD |
1002 | } |
1003 | ||
1004 | /* Determine how many BRPs/WRPs are available. */ | |
1005 | core_num_brps = get_num_brps(); | |
1006 | core_num_wrps = get_num_wrps(); | |
1007 | ||
0d352e3d WD |
1008 | /* |
1009 | * We need to tread carefully here because DBGSWENABLE may be | |
1010 | * driven low on this core and there isn't an architected way to | |
1011 | * determine that. | |
1012 | */ | |
1013 | register_undef_hook(&debug_reg_hook); | |
f81ef4a9 | 1014 | |
ed19b739 WD |
1015 | /* |
1016 | * Reset the breakpoint resources. We assume that a halting | |
1017 | * debugger will leave the world in a nice state for us. | |
1018 | */ | |
0d352e3d WD |
1019 | on_each_cpu(reset_ctrl_regs, NULL, 1); |
1020 | unregister_undef_hook(&debug_reg_hook); | |
1021 | if (!cpumask_empty(&debug_err_mask)) { | |
c09bae70 | 1022 | core_num_brps = 0; |
c09bae70 WD |
1023 | core_num_wrps = 0; |
1024 | return 0; | |
1025 | } | |
ed19b739 | 1026 | |
0d352e3d WD |
1027 | pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n", |
1028 | core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " : | |
1029 | "", core_num_wrps); | |
1030 | ||
b59a540c WD |
1031 | /* Work out the maximum supported watchpoint length. */ |
1032 | max_watchpoint_len = get_max_wp_len(); | |
1033 | pr_info("maximum watchpoint size is %u bytes.\n", | |
1034 | max_watchpoint_len); | |
f81ef4a9 WD |
1035 | |
1036 | /* Register debug fault handler. */ | |
f7b8156d CM |
1037 | hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP, |
1038 | TRAP_HWBKPT, "watchpoint debug exception"); | |
1039 | hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP, | |
1040 | TRAP_HWBKPT, "breakpoint debug exception"); | |
f81ef4a9 | 1041 | |
7d99331e WD |
1042 | /* Register hotplug notifier. */ |
1043 | register_cpu_notifier(&dbg_reset_nb); | |
8fbf397c | 1044 | return 0; |
f81ef4a9 WD |
1045 | } |
1046 | arch_initcall(arch_hw_breakpoint_init); | |
1047 | ||
1048 | void hw_breakpoint_pmu_read(struct perf_event *bp) | |
1049 | { | |
1050 | } | |
1051 | ||
1052 | /* | |
1053 | * Dummy function to register with die_notifier. | |
1054 | */ | |
1055 | int hw_breakpoint_exceptions_notify(struct notifier_block *unused, | |
1056 | unsigned long val, void *data) | |
1057 | { | |
1058 | return NOTIFY_DONE; | |
1059 | } |