[people/ms/u-boot.git] / arch / arm / mach-at91 / arm926ejs / at91sam9260_devices.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/gpio.h>

/*
 * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
 * peripheral pins. Good to have if hardware is soldered optionally
 * or in case of SPI no slave is selected. Avoid lines to float
 * needlessly. Use a short local PUP define.
 *
 * Due to errata "TXD floats when CTS is inactive" pullups are always
 * on for TXD pins.
 */
#ifdef CONFIG_AT91_GPIO_PULLUP
# define PUP CONFIG_AT91_GPIO_PULLUP
#else
# define PUP 0
#endif

void at91_serial0_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD0 */
	at91_set_a_periph(AT91_PIO_PORTB, 5, PUP);		/* RXD0 */
	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
}

void at91_serial1_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 6, 1);		/* TXD1 */
	at91_set_a_periph(AT91_PIO_PORTB, 7, PUP);		/* RXD1 */
	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
}

void at91_serial2_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 8, 1);		/* TXD2 */
	at91_set_a_periph(AT91_PIO_PORTB, 9, PUP);		/* RXD2 */
	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
}

void at91_seriald_hw_init(void)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP);		/* DRXD */
	at91_set_a_periph(AT91_PIO_PORTB, 15, 1);		/* DTXD */
	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}

#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP);	/* SPI0_MISO */
	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP);	/* SPI0_MOSI */
	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP);	/* SPI0_SPCK */

	/* Enable clock */
	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);

	if (cs_mask & (1 << 0)) {
		at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
	}
}

void at91_spi1_hw_init(unsigned long cs_mask)
{
	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;

	at91_set_a_periph(AT91_PIO_PORTB, 0, PUP);	/* SPI1_MISO */
	at91_set_a_periph(AT91_PIO_PORTB, 1, PUP);	/* SPI1_MOSI */
	at91_set_a_periph(AT91_PIO_PORTB, 2, PUP);	/* SPI1_SPCK */

	/* Enable clock */
	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);

	if (cs_mask & (1 << 0)) {
		at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
	}
	if (cs_mask & (1 << 1)) {
		at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
	}
	if (cs_mask & (1 << 2)) {
		at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
	}
	if (cs_mask & (1 << 3)) {
		at91_set_b_periph(AT91_PIO_PORTC, 3, 1);
	}
	if (cs_mask & (1 << 4)) {
		at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
	}
	if (cs_mask & (1 << 5)) {
		at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
	}
	if (cs_mask & (1 << 6)) {
		at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
	}
	if (cs_mask & (1 << 7)) {
		at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
	}
}
#endif

#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
	/* Enable EMAC clock */
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);

	at91_set_a_periph(AT91_PIO_PORTA, 19, 0);	/* ETXCK_EREFCK */
	at91_set_a_periph(AT91_PIO_PORTA, 17, 0);	/* ERXDV */
	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* ERX0 */
	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* ERX1 */
	at91_set_a_periph(AT91_PIO_PORTA, 18, 0);	/* ERXER */
	at91_set_a_periph(AT91_PIO_PORTA, 16, 0);	/* ETXEN */
	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* ETX0 */
	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* ETX1 */
	at91_set_a_periph(AT91_PIO_PORTA, 21, 0);	/* EMDIO */
	at91_set_a_periph(AT91_PIO_PORTA, 20, 0);	/* EMDC */

#ifndef CONFIG_RMII
	at91_set_b_periph(AT91_PIO_PORTA, 28, 0);	/* ECRS */
	at91_set_b_periph(AT91_PIO_PORTA, 29, 0);	/* ECOL */
	at91_set_b_periph(AT91_PIO_PORTA, 25, 0);	/* ERX2 */
	at91_set_b_periph(AT91_PIO_PORTA, 26, 0);	/* ERX3 */
	at91_set_b_periph(AT91_PIO_PORTA, 27, 0);	/* ERXCK */
#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
	/*
	 * use PA10, PA11 for ETX2, ETX3.
	 * PA23 and PA24 are for TWI EEPROM
	 */
	at91_set_b_periph(AT91_PIO_PORTA, 10, 0);	/* ETX2 */
	at91_set_b_periph(AT91_PIO_PORTA, 11, 0);	/* ETX3 */
#else
	at91_set_b_periph(AT91_PIO_PORTA, 23, 0);	/* ETX2 */
	at91_set_b_periph(AT91_PIO_PORTA, 24, 0);	/* ETX3 */
#if defined(CONFIG_AT91SAM9G20)
	/* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
#endif
#endif
	at91_set_b_periph(AT91_PIO_PORTA, 22, 0);	/* ETXER */
#endif
}
#endif

#if defined(CONFIG_GENERIC_ATMEL_MCI)
void at91_mci_hw_init(void)
{
	/* Enable mci clock */
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	writel(1 << ATMEL_ID_MCI, &pmc->pcer);

	at91_set_a_periph(AT91_PIO_PORTA, 8, 1);	/* MCCK */
#if defined(CONFIG_ATMEL_MCI_PORTB)
	at91_set_b_periph(AT91_PIO_PORTA, 1, 1);	/* MCCDB */
	at91_set_b_periph(AT91_PIO_PORTA, 0, 1);	/* MCDB0 */
	at91_set_b_periph(AT91_PIO_PORTA, 5, 1);	/* MCDB1 */
	at91_set_b_periph(AT91_PIO_PORTA, 4, 1);	/* MCDB2 */
	at91_set_b_periph(AT91_PIO_PORTA, 3, 1);	/* MCDB3 */
#else
	at91_set_a_periph(AT91_PIO_PORTA, 7, 1);	/* MCCDA */
	at91_set_a_periph(AT91_PIO_PORTA, 6, 1);	/* MCDA0 */
	at91_set_a_periph(AT91_PIO_PORTA, 9, 1);	/* MCDA1 */
	at91_set_a_periph(AT91_PIO_PORTA, 10, 1);	/* MCDA2 */
	at91_set_a_periph(AT91_PIO_PORTA, 11, 1);	/* MCDA3 */
#endif
}
#endif

void at91_sdram_hw_init(void)
{
	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 17, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 20, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 21, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 25, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 28, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 29, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);
	at91_set_a_periph(AT91_PIO_PORTC, 31, 0);
}

/* Platform data for the GPIOs */
static const struct at91_port_platdata at91sam9260_plat[] = {
	{ ATMEL_BASE_PIOA, "PA" },
	{ ATMEL_BASE_PIOB, "PB" },
	{ ATMEL_BASE_PIOC, "PC" },
};

U_BOOT_DEVICES(at91sam9260_gpios) = {
	{ "gpio_at91", &at91sam9260_plat[0] },
	{ "gpio_at91", &at91sam9260_plat[1] },
	{ "gpio_at91", &at91sam9260_plat[2] },
};
Commit	Line	Data
7ebafb7e JCPV	1	/*
7ebafb7e JCPV	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
7ebafb7e JCPV	4	* Lead Tech Design <www.leadtechdesign.com>
7ebafb7e JCPV	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
7ebafb7e JCPV	7	*/
	8
	9	#include <common.h>
12fe7f7c	10	#include <dm.h>
86592f60	11	#include <asm/io.h>
5abc00d0	12	#include <asm/arch/at91sam9260_matrix.h>
7ebafb7e JCPV	13	#include <asm/arch/at91_common.h>
7ebafb7e JCPV	14	#include <asm/arch/at91_pmc.h>
5abc00d0	15	#include <asm/arch/at91sam9_sdramc.h>
7ebafb7e	16	#include <asm/arch/gpio.h>
7ebafb7e	17
7588ad12 RM	18	/*
	19	* if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
	20	* peripheral pins. Good to have if hardware is soldered optionally
	21	* or in case of SPI no slave is selected. Avoid lines to float
	22	* needlessly. Use a short local PUP define.
	23	*
	24	* Due to errata "TXD floats when CTS is inactive" pullups are always
	25	* on for TXD pins.
	26	*/
	27	#ifdef CONFIG_AT91_GPIO_PULLUP
	28	# define PUP CONFIG_AT91_GPIO_PULLUP
	29	#else
	30	# define PUP 0
	31	#endif
	32
1699da62 JCPV	33	void at91_serial0_hw_init(void)
1699da62 JCPV	34	{
9f3fe90f	35	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	36
7f9e8633	37	at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
7588ad12	38	at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */
9f3fe90f	39	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
1699da62 JCPV	40	}
	41
	42	void at91_serial1_hw_init(void)
	43	{
9f3fe90f	44	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	45
7f9e8633	46	at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
7588ad12	47	at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */
9f3fe90f	48	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
1699da62 JCPV	49	}
	50
	51	void at91_serial2_hw_init(void)
	52	{
9f3fe90f	53	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	54
7f9e8633	55	at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
7588ad12	56	at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */
9f3fe90f	57	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
1699da62 JCPV	58	}
1699da62 JCPV	59
9f3fe90f	60	void at91_seriald_hw_init(void)
1699da62	61	{
9f3fe90f	62	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	63
7588ad12	64	at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */
7f9e8633	65	at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
9f3fe90f	66	writel(1 << ATMEL_ID_SYS, &pmc->pcer);
1699da62 JCPV	67	}
1699da62 JCPV	68
9453967e	69	#if defined(CONFIG_HAS_DATAFLASH) \|\| defined(CONFIG_ATMEL_SPI)
7ebafb7e JCPV	70	void at91_spi0_hw_init(unsigned long cs_mask)
7ebafb7e JCPV	71	{
9f3fe90f	72	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	73
7588ad12 RM	74	at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
	75	at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
	76	at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
7ebafb7e JCPV	77
7ebafb7e JCPV	78	/* Enable clock */
9f3fe90f	79	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
7ebafb7e JCPV	80
7ebafb7e JCPV	81	if (cs_mask & (1 << 0)) {
7f9e8633	82	at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
7ebafb7e JCPV	83	}
7ebafb7e JCPV	84	if (cs_mask & (1 << 1)) {
7f9e8633	85	at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
7ebafb7e JCPV	86	}
7ebafb7e JCPV	87	if (cs_mask & (1 << 2)) {
7f9e8633	88	at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
7ebafb7e JCPV	89	}
7ebafb7e JCPV	90	if (cs_mask & (1 << 3)) {
7f9e8633	91	at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
a47492ac JCPV	92	}
a47492ac JCPV	93	if (cs_mask & (1 << 4)) {
7f9e8633	94	at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
a47492ac JCPV	95	}
a47492ac JCPV	96	if (cs_mask & (1 << 5)) {
7f9e8633	97	at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
a47492ac JCPV	98	}
a47492ac JCPV	99	if (cs_mask & (1 << 6)) {
7f9e8633	100	at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
a47492ac JCPV	101	}
a47492ac JCPV	102	if (cs_mask & (1 << 7)) {
7f9e8633	103	at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
7ebafb7e JCPV	104	}
	105	}
	106
	107	void at91_spi1_hw_init(unsigned long cs_mask)
	108	{
9f3fe90f	109	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
0cf0b931	110
7588ad12 RM	111	at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */
	112	at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */
	113	at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */
7ebafb7e JCPV	114
7ebafb7e JCPV	115	/* Enable clock */
9f3fe90f	116	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
7ebafb7e JCPV	117
7ebafb7e JCPV	118	if (cs_mask & (1 << 0)) {
7f9e8633	119	at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
7ebafb7e JCPV	120	}
7ebafb7e JCPV	121	if (cs_mask & (1 << 1)) {
7f9e8633	122	at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
7ebafb7e JCPV	123	}
7ebafb7e JCPV	124	if (cs_mask & (1 << 2)) {
7f9e8633	125	at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
7ebafb7e JCPV	126	}
7ebafb7e JCPV	127	if (cs_mask & (1 << 3)) {
b38d634b	128	at91_set_b_periph(AT91_PIO_PORTC, 3, 1);
7ebafb7e	129	}
a47492ac	130	if (cs_mask & (1 << 4)) {
7f9e8633	131	at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
a47492ac JCPV	132	}
a47492ac JCPV	133	if (cs_mask & (1 << 5)) {
7f9e8633	134	at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
a47492ac JCPV	135	}
a47492ac JCPV	136	if (cs_mask & (1 << 6)) {
7f9e8633	137	at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
a47492ac JCPV	138	}
a47492ac JCPV	139	if (cs_mask & (1 << 7)) {
7f9e8633	140	at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
a47492ac	141	}
7ebafb7e	142	}
1699da62 JCPV	143	#endif
	144
	145	#ifdef CONFIG_MACB
	146	void at91_macb_hw_init(void)
	147	{
a3dab5d1 MH	148	/* Enable EMAC clock */
	149	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	150	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
	151
7f9e8633 JS	152	at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */
	153	at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */
	154	at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */
	155	at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERX1 */
	156	at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* ERXER */
	157	at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ETXEN */
	158	at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ETX0 */
	159	at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ETX1 */
	160	at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* EMDIO */
	161	at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* EMDC */
1699da62 JCPV	162
1699da62 JCPV	163	#ifndef CONFIG_RMII
7f9e8633 JS	164	at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ECRS */
	165	at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECOL */
	166	at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */
	167	at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */
	168	at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */
9475c63c	169	#if defined(CONFIG_AT91SAM9260EK) \|\| defined(CONFIG_AFEB9260)
1699da62 JCPV	170	/*
	171	* use PA10, PA11 for ETX2, ETX3.
	172	* PA23 and PA24 are for TWI EEPROM
	173	*/
7f9e8633 JS	174	at91_set_b_periph(AT91_PIO_PORTA, 10, 0); /* ETX2 */
7f9e8633 JS	175	at91_set_b_periph(AT91_PIO_PORTA, 11, 0); /* ETX3 */
1699da62	176	#else
7f9e8633 JS	177	at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */
7f9e8633 JS	178	at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */
accef431 RM	179	#if defined(CONFIG_AT91SAM9G20)
	180	/* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
	181	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
	182	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
	183	#endif
1699da62	184	#endif
7f9e8633	185	at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */
1699da62 JCPV	186	#endif
	187	}
	188	#endif
1592ef85	189
c9abb426	190	#if defined(CONFIG_GENERIC_ATMEL_MCI)
1592ef85 RM	191	void at91_mci_hw_init(void)
1592ef85 RM	192	{
a73267a7 WJ	193	/* Enable mci clock */
	194	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	195	writel(1 << ATMEL_ID_MCI, &pmc->pcer);
	196
1592ef85 RM	197	at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */
	198	#if defined(CONFIG_ATMEL_MCI_PORTB)
	199	at91_set_b_periph(AT91_PIO_PORTA, 1, 1); /* MCCDB */
	200	at91_set_b_periph(AT91_PIO_PORTA, 0, 1); /* MCDB0 */
	201	at91_set_b_periph(AT91_PIO_PORTA, 5, 1); /* MCDB1 */
	202	at91_set_b_periph(AT91_PIO_PORTA, 4, 1); /* MCDB2 */
	203	at91_set_b_periph(AT91_PIO_PORTA, 3, 1); /* MCDB3 */
	204	#else
	205	at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* MCCDA */
	206	at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* MCDA0 */
	207	at91_set_a_periph(AT91_PIO_PORTA, 9, 1); /* MCDA1 */
	208	at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* MCDA2 */
	209	at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* MCDA3 */
	210	#endif
	211	}
	212	#endif
5abc00d0 HS	213
	214	void at91_sdram_hw_init(void)
	215	{
	216	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);
	217	at91_set_a_periph(AT91_PIO_PORTC, 17, 0);
	218	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);
	219	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);
	220	at91_set_a_periph(AT91_PIO_PORTC, 20, 0);
	221	at91_set_a_periph(AT91_PIO_PORTC, 21, 0);
	222	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);
	223	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);
	224	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);
	225	at91_set_a_periph(AT91_PIO_PORTC, 25, 0);
	226	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);
	227	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);
	228	at91_set_a_periph(AT91_PIO_PORTC, 28, 0);
	229	at91_set_a_periph(AT91_PIO_PORTC, 29, 0);
	230	at91_set_a_periph(AT91_PIO_PORTC, 30, 0);
	231	at91_set_a_periph(AT91_PIO_PORTC, 31, 0);
	232	}
12fe7f7c SG	233
	234	/* Platform data for the GPIOs */
	235	static const struct at91_port_platdata at91sam9260_plat[] = {
	236	{ ATMEL_BASE_PIOA, "PA" },
	237	{ ATMEL_BASE_PIOB, "PB" },
	238	{ ATMEL_BASE_PIOC, "PC" },
	239	};
	240
	241	U_BOOT_DEVICES(at91sam9260_gpios) = {
	242	{ "gpio_at91", &at91sam9260_plat[0] },
	243	{ "gpio_at91", &at91sam9260_plat[1] },
	244	{ "gpio_at91", &at91sam9260_plat[2] },
	245	};