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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
22ee6473 SG |
2 | /* |
3 | * (C) Copyright 2007-2008 | |
c9e798d3 | 4 | * Stelian Pop <stelian@popies.net> |
22ee6473 | 5 | * Lead Tech Design <www.leadtechdesign.com> |
22ee6473 SG |
6 | */ |
7 | ||
8 | #include <common.h> | |
b3ab0fc7 | 9 | #include <dm.h> |
22ee6473 | 10 | #include <asm/arch/at91_common.h> |
eced5a7e | 11 | #include <asm/arch/clk.h> |
22ee6473 | 12 | #include <asm/arch/gpio.h> |
58fb6020 TP |
13 | #include <asm/io.h> |
14 | ||
15 | /* | |
16 | * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all | |
17 | * peripheral pins. Good to have if hardware is soldered optionally | |
18 | * or in case of SPI no slave is selected. Avoid lines to float | |
19 | * needlessly. Use a short local PUP define. | |
20 | * | |
21 | * Due to errata "TXD floats when CTS is inactive" pullups are always | |
22 | * on for TXD pins. | |
23 | */ | |
24 | #ifdef CONFIG_AT91_GPIO_PULLUP | |
25 | # define PUP CONFIG_AT91_GPIO_PULLUP | |
26 | #else | |
27 | # define PUP 0 | |
28 | #endif | |
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29 | |
30 | void at91_serial0_hw_init(void) | |
31 | { | |
7f9e8633 | 32 | at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */ |
58fb6020 | 33 | at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */ |
eced5a7e | 34 | at91_periph_clk_enable(ATMEL_ID_USART0); |
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35 | } |
36 | ||
37 | void at91_serial1_hw_init(void) | |
38 | { | |
7f9e8633 | 39 | at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */ |
58fb6020 | 40 | at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */ |
eced5a7e | 41 | at91_periph_clk_enable(ATMEL_ID_USART1); |
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42 | } |
43 | ||
44 | void at91_serial2_hw_init(void) | |
45 | { | |
7f9e8633 | 46 | at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */ |
58fb6020 | 47 | at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */ |
eced5a7e | 48 | at91_periph_clk_enable(ATMEL_ID_USART2); |
22ee6473 SG |
49 | } |
50 | ||
58fb6020 | 51 | void at91_seriald_hw_init(void) |
22ee6473 | 52 | { |
7f9e8633 JS |
53 | at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */ |
54 | at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */ | |
eced5a7e | 55 | at91_periph_clk_enable(ATMEL_ID_SYS); |
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56 | } |
57 | ||
c68c03f5 | 58 | #ifdef CONFIG_ATMEL_SPI |
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59 | void at91_spi0_hw_init(unsigned long cs_mask) |
60 | { | |
58fb6020 TP |
61 | at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */ |
62 | at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */ | |
63 | at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */ | |
22ee6473 | 64 | |
eced5a7e | 65 | at91_periph_clk_enable(ATMEL_ID_SPI0); |
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66 | |
67 | if (cs_mask & (1 << 0)) { | |
58fb6020 | 68 | at91_set_a_periph(AT91_PIO_PORTB, 3, 1); |
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69 | } |
70 | if (cs_mask & (1 << 1)) { | |
58fb6020 | 71 | at91_set_b_periph(AT91_PIO_PORTB, 18, 1); |
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72 | } |
73 | if (cs_mask & (1 << 2)) { | |
58fb6020 | 74 | at91_set_b_periph(AT91_PIO_PORTB, 19, 1); |
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75 | } |
76 | if (cs_mask & (1 << 3)) { | |
58fb6020 | 77 | at91_set_b_periph(AT91_PIO_PORTD, 27, 1); |
22ee6473 SG |
78 | } |
79 | if (cs_mask & (1 << 4)) { | |
58fb6020 | 80 | at91_set_pio_output(AT91_PIO_PORTB, 3, 1); |
22ee6473 SG |
81 | } |
82 | if (cs_mask & (1 << 5)) { | |
58fb6020 | 83 | at91_set_pio_output(AT91_PIO_PORTB, 18, 1); |
22ee6473 SG |
84 | } |
85 | if (cs_mask & (1 << 6)) { | |
58fb6020 | 86 | at91_set_pio_output(AT91_PIO_PORTB, 19, 1); |
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87 | } |
88 | if (cs_mask & (1 << 7)) { | |
58fb6020 | 89 | at91_set_pio_output(AT91_PIO_PORTD, 27, 1); |
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90 | } |
91 | } | |
92 | ||
93 | void at91_spi1_hw_init(unsigned long cs_mask) | |
94 | { | |
58fb6020 TP |
95 | at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */ |
96 | at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */ | |
97 | at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */ | |
22ee6473 | 98 | |
eced5a7e | 99 | at91_periph_clk_enable(ATMEL_ID_SPI1); |
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100 | |
101 | if (cs_mask & (1 << 0)) { | |
58fb6020 | 102 | at91_set_a_periph(AT91_PIO_PORTB, 17, 1); |
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103 | } |
104 | if (cs_mask & (1 << 1)) { | |
58fb6020 | 105 | at91_set_b_periph(AT91_PIO_PORTD, 28, 1); |
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106 | } |
107 | if (cs_mask & (1 << 2)) { | |
58fb6020 | 108 | at91_set_a_periph(AT91_PIO_PORTD, 18, 1); |
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109 | } |
110 | if (cs_mask & (1 << 3)) { | |
58fb6020 | 111 | at91_set_a_periph(AT91_PIO_PORTD, 19, 1); |
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112 | } |
113 | if (cs_mask & (1 << 4)) { | |
58fb6020 | 114 | at91_set_pio_output(AT91_PIO_PORTB, 17, 1); |
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115 | } |
116 | if (cs_mask & (1 << 5)) { | |
58fb6020 | 117 | at91_set_pio_output(AT91_PIO_PORTD, 28, 1); |
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118 | } |
119 | if (cs_mask & (1 << 6)) { | |
58fb6020 | 120 | at91_set_pio_output(AT91_PIO_PORTD, 18, 1); |
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121 | } |
122 | if (cs_mask & (1 << 7)) { | |
58fb6020 | 123 | at91_set_pio_output(AT91_PIO_PORTD, 19, 1); |
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124 | } |
125 | ||
126 | } | |
127 | #endif | |
128 | ||
129 | #ifdef CONFIG_MACB | |
130 | void at91_macb_hw_init(void) | |
131 | { | |
7f9e8633 JS |
132 | at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */ |
133 | at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */ | |
134 | at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */ | |
135 | at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */ | |
136 | at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */ | |
137 | at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */ | |
138 | at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */ | |
139 | at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */ | |
140 | at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */ | |
141 | at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */ | |
22ee6473 | 142 | #ifndef CONFIG_RMII |
7f9e8633 JS |
143 | at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */ |
144 | at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */ | |
145 | at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */ | |
146 | at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */ | |
147 | at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */ | |
148 | at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */ | |
149 | at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */ | |
150 | at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */ | |
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151 | #endif |
152 | } | |
153 | #endif | |
cf874c19 WJ |
154 | |
155 | #ifdef CONFIG_GENERIC_ATMEL_MCI | |
156 | void at91_mci_hw_init(void) | |
157 | { | |
cf874c19 WJ |
158 | at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */ |
159 | at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */ | |
160 | at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */ | |
161 | at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */ | |
162 | at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */ | |
163 | at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */ | |
164 | ||
eced5a7e | 165 | at91_periph_clk_enable(ATMEL_ID_MCI0); |
cf874c19 WJ |
166 | } |
167 | #endif | |
b3ab0fc7 SG |
168 | |
169 | /* Platform data for the GPIOs */ | |
170 | static const struct at91_port_platdata at91sam9260_plat[] = { | |
171 | { ATMEL_BASE_PIOA, "PA" }, | |
172 | { ATMEL_BASE_PIOB, "PB" }, | |
173 | { ATMEL_BASE_PIOC, "PC" }, | |
174 | { ATMEL_BASE_PIOD, "PD" }, | |
175 | { ATMEL_BASE_PIOE, "PE" }, | |
176 | }; | |
177 | ||
178 | U_BOOT_DEVICES(at91sam9260_gpios) = { | |
179 | { "gpio_at91", &at91sam9260_plat[0] }, | |
180 | { "gpio_at91", &at91sam9260_plat[1] }, | |
181 | { "gpio_at91", &at91sam9260_plat[2] }, | |
182 | { "gpio_at91", &at91sam9260_plat[3] }, | |
183 | { "gpio_at91", &at91sam9260_plat[4] }, | |
184 | }; |