projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 8e429b3e SP |
2 | /* |
| 3 | * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h] | |
| 4 | * | |
| 5 | * Copyright (C) 2006 Atmel Corporation. | |
| 6 | * | |
| 7 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | |
| 8 | * Based on AT91SAM9263 datasheet revision B (Preliminary). | |
| 8e429b3e SP |
9 | */ |
| 10 | ||
| 11 | #ifndef AT91SAM9263_MATRIX_H | |
| 12 | #define AT91SAM9263_MATRIX_H | |
| 13 | ||
| ffa280fa | 14 | #ifndef __ASSEMBLY__ |
| 8e429b3e | 15 | |
| ffa280fa XH |
16 | /* |
| 17 | * This struct defines access to the matrix' maximum of | |
| 18 | * 16 masters and 16 slaves. | |
| 19 | * Note: not all masters/slaves are available | |
| 20 | */ | |
| 21 | struct at91_matrix { | |
| 22 | u32 mcfg[16]; /* Master Configuration Registers */ | |
| 23 | u32 scfg[16]; /* Slave Configuration Registers */ | |
| 24 | u32 pras[16][2]; /* Priority Assignment Slave Registers */ | |
| 25 | u32 mrcr; /* Master Remap Control Register */ | |
| 26 | u32 filler[0x06]; | |
| 27 | u32 ebicsa; /* EBI Chip Select Assignment Register */ | |
| 28 | }; | |
| 29 | ||
| 30 | #endif /* __ASSEMBLY__ */ | |
| 8e429b3e | 31 | |
| ffa280fa XH |
32 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) |
| 33 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | |
| 34 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | |
| 35 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | |
| 36 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | |
| 8e429b3e | 37 | |
| ffa280fa XH |
38 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
| 39 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | |
| 40 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | |
| 41 | #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 | |
| 42 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | |
| 43 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | |
| 8e429b3e | 44 | |
| ffa280fa XH |
45 | #define AT91_MATRIX_M0PR_SHIFT 0 |
| 46 | #define AT91_MATRIX_M1PR_SHIFT 4 | |
| 47 | #define AT91_MATRIX_M2PR_SHIFT 8 | |
| 48 | #define AT91_MATRIX_M3PR_SHIFT 12 | |
| 49 | #define AT91_MATRIX_M4PR_SHIFT 16 | |
| 50 | #define AT91_MATRIX_M5PR_SHIFT 20 | |
| 8e429b3e | 51 | |
| ffa280fa XH |
52 | #define AT91_MATRIX_RCB0 (1 << 0) |
| 53 | #define AT91_MATRIX_RCB1 (1 << 1) | |
| 8e429b3e | 54 | |
| ffa280fa XH |
55 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) |
| 56 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | |
| 57 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | |
| 58 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | |
| 59 | #define AT91_MATRIX_DBPUC (1 << 8) | |
| 60 | #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) | |
| 61 | #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) | |
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62 | |
| 63 | #endif |