projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 75238f23 WY |
2 | /* |
| 3 | * Chip-specific header file for the SAMA5D2 SoC | |
| 4 | * | |
| 5 | * Copyright (C) 2015 Atmel | |
| 6 | * Wenyou Yang <wenyou.yang@atmel.com> | |
| 75238f23 WY |
7 | */ |
| 8 | ||
| 9 | #ifndef __SAMA5D2_H | |
| 10 | #define __SAMA5D2_H | |
| 11 | ||
| 75238f23 WY |
12 | /* |
| 13 | * Peripheral identifiers/interrupts. | |
| 14 | */ | |
| 15 | #define ATMEL_ID_FIQ 0 /* FIQ Interrupt ID */ | |
| 16 | /* 1 */ | |
| 17 | #define ATMEL_ID_ARM 2 /* Performance Monitor Unit */ | |
| 18 | #define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */ | |
| 19 | #define ATMEL_ID_WDT 4 /* Watchdog Timer Interrupt */ | |
| 20 | #define ATMEL_ID_GMAC 5 /* Ethernet MAC */ | |
| 21 | #define ATMEL_ID_XDMAC0 6 /* DMA Controller 0 */ | |
| 22 | #define ATMEL_ID_XDMAC1 7 /* DMA Controller 1 */ | |
| 23 | #define ATMEL_ID_ICM 8 /* Integrity Check Monitor */ | |
| 24 | #define ATMEL_ID_AES 9 /* Advanced Encryption Standard */ | |
| 25 | #define ATMEL_ID_AESB 10 /* AES bridge */ | |
| 26 | #define ATMEL_ID_TDES 11 /* Triple Data Encryption Standard */ | |
| 27 | #define ATMEL_ID_SHA 12 /* SHA Signature */ | |
| 28 | #define ATMEL_ID_MPDDRC 13 /* MPDDR Controller */ | |
| 29 | #define ATMEL_ID_MATRIX1 14 /* H32MX, 32-bit AHB Matrix */ | |
| 30 | #define ATMEL_ID_MATRIX0 15 /* H64MX, 64-bit AHB Matrix */ | |
| 31 | #define ATMEL_ID_SECUMOD 16 /* Secure Module */ | |
| 32 | #define ATMEL_ID_HSMC 17 /* Multi-bit ECC interrupt */ | |
| 33 | #define ATMEL_ID_PIOA 18 /* Parallel I/O Controller A */ | |
| 34 | #define ATMEL_ID_FLEXCOM0 19 /* FLEXCOM0 */ | |
| 35 | #define ATMEL_ID_FLEXCOM1 20 /* FLEXCOM1 */ | |
| 36 | #define ATMEL_ID_FLEXCOM2 21 /* FLEXCOM2 */ | |
| 37 | #define ATMEL_ID_FLEXCOM3 22 /* FLEXCOM3 */ | |
| 38 | #define ATMEL_ID_FLEXCOM4 23 /* FLEXCOM4 */ | |
| 39 | #define ATMEL_ID_UART0 24 /* UART0 */ | |
| 40 | #define ATMEL_ID_UART1 25 /* UART1 */ | |
| 41 | #define ATMEL_ID_UART2 26 /* UART2 */ | |
| 42 | #define ATMEL_ID_UART3 27 /* UART3 */ | |
| 43 | #define ATMEL_ID_UART4 28 /* UART4 */ | |
| 44 | #define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */ | |
| 45 | #define ATMEL_ID_TWIHS1 30 /* Two-wire Interface 1 */ | |
| 46 | #define ATMEL_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */ | |
| 47 | #define ATMEL_ID_SDMMC1 32 /* Secure Data Memory Card Controller 1 */ | |
| 48 | #define ATMEL_ID_SPI0 33 /* Serial Peripheral Interface 0 */ | |
| 49 | #define ATMEL_ID_SPI1 34 /* Serial Peripheral Interface 1 */ | |
| 50 | #define ATMEL_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */ | |
| 51 | #define ATMEL_ID_TC1 36 /* Timer Counter 1 (ch.3,4,5) */ | |
| 52 | /* 37 */ | |
| 53 | #define ATMEL_ID_PWM 38 /* PWMController0 (ch. 0,1,2,3) */ | |
| 54 | /* 39 */ | |
| 55 | #define ATMEL_ID_ADC 40 /* Touch Screen ADC Controller */ | |
| 56 | #define ATMEL_ID_UHPHS 41 /* USB Host High Speed */ | |
| 57 | #define ATMEL_ID_UDPHS 42 /* USB Device High Speed */ | |
| 58 | #define ATMEL_ID_SSC0 43 /* Serial Synchronous Controller 0 */ | |
| 59 | #define ATMEL_ID_SSC1 44 /* Serial Synchronous Controller 1 */ | |
| 60 | #define ATMEL_ID_LCDC 45 /* LCD Controller */ | |
| 61 | #define ATMEL_ID_ISI 46 /* Image Sensor Controller, for A5D2, named after ISC */ | |
| 62 | #define ATMEL_ID_TRNG 47 /* True Random Number Generator */ | |
| 63 | #define ATMEL_ID_PDMIC 48 /* PDM Interface Controller */ | |
| 64 | #define ATMEL_ID_AIC_IRQ 49 /* IRQ Interrupt ID */ | |
| 65 | #define ATMEL_ID_SFC 50 /* Fuse Controller */ | |
| 66 | #define ATMEL_ID_SECURAM 51 /* Secure RAM */ | |
| 67 | #define ATMEL_ID_QSPI0 52 /* QSPI0 */ | |
| 68 | #define ATMEL_ID_QSPI1 53 /* QSPI1 */ | |
| 69 | #define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */ | |
| 70 | #define ATMEL_ID_I2SC1 55 /* Inter-IC Sound Controller 1 */ | |
| 71 | #define ATMEL_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */ | |
| 72 | #define ATMEL_ID_CAN1_INT0 57 /* MCAN 1 Interrupt0 */ | |
| 73 | /* 58 */ | |
| 74 | #define ATMEL_ID_CLASSD 59 /* Audio Class D Amplifier */ | |
| 75 | #define ATMEL_ID_SFR 60 /* Special Function Register */ | |
| 76 | #define ATMEL_ID_SAIC 61 /* Secured AIC */ | |
| 77 | #define ATMEL_ID_AIC 62 /* Advanced Interrupt Controller */ | |
| 78 | #define ATMEL_ID_L2CC 63 /* L2 Cache Controller */ | |
| 79 | #define ATMEL_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */ | |
| 80 | #define ATMEL_ID_CAN1_INT1 65 /* MCAN 1 Interrupt1 */ | |
| 81 | #define ATMEL_ID_GMAC_Q1 66 /* GMAC Queue 1 Interrupt */ | |
| 82 | #define ATMEL_ID_GMAC_Q2 67 /* GMAC Queue 2 Interrupt */ | |
| 83 | #define ATMEL_ID_PIOB 68 /* Parallel I/O Controller B */ | |
| 84 | #define ATMEL_ID_PIOC 69 /* Parallel I/O Controller C */ | |
| 85 | #define ATMEL_ID_PIOD 70 /* Parallel I/O Controller D */ | |
| 86 | #define ATMEL_ID_SDMMC0_TIMER 71 /* Secure Data Memory Card Controller 0 (TIMER) */ | |
| 87 | #define ATMEL_ID_SDMMC1_TIMER 72 /* Secure Data Memory Card Controller 1 (TIMER) */ | |
| 88 | /* 73 */ | |
| 89 | #define ATMEL_ID_SYS 74 /* System Controller Interrupt */ | |
| 90 | #define ATMEL_ID_ACC 75 /* Analog Comparator */ | |
| 91 | #define ATMEL_ID_RXLP 76 /* UART Low-Power */ | |
| 92 | #define ATMEL_ID_SFRBU 77 /* Special Function Register BackUp */ | |
| 93 | #define ATMEL_ID_CHIPID 78 /* Chip ID */ | |
| 94 | ||
| 95 | /* | |
| 96 | * User Peripherals physical base addresses. | |
| 97 | */ | |
| 98 | #define ATMEL_BASE_LCDC 0xf0000000 | |
| 99 | #define ATMEL_BASE_XDMAC1 0xf0004000 | |
| 100 | #define ATMEL_BASE_MPDDRC 0xf000c000 | |
| 101 | #define ATMEL_BASE_XDMAC0 0xf0010000 | |
| 102 | #define ATMEL_BASE_PMC 0xf0014000 | |
| 37dadbca | 103 | #define ATMEL_BASE_MATRIX0 0xf0018000 |
| 75238f23 WY |
104 | #define ATMEL_BASE_QSPI0 0xf0020000 |
| 105 | #define ATMEL_BASE_QSPI1 0xf0024000 | |
| 106 | #define ATMEL_BASE_SPI0 0xf8000000 | |
| 107 | #define ATMEL_BASE_GMAC 0xf8008000 | |
| 108 | #define ATMEL_BASE_TC0 0xf800c000 | |
| 109 | #define ATMEL_BASE_TC1 0xf8010000 | |
| 110 | #define ATMEL_BASE_HSMC 0xf8014000 | |
| 111 | #define ATMEL_BASE_UART0 0xf801c000 | |
| 112 | #define ATMEL_BASE_UART1 0xf8020000 | |
| 113 | #define ATMEL_BASE_UART2 0xf8024000 | |
| 114 | #define ATMEL_BASE_TWI0 0xf8028000 | |
| 37dadbca | 115 | #define ATMEL_BASE_SFR 0xf8030000 |
| 75238f23 WY |
116 | #define ATMEL_BASE_SYSC 0xf8048000 |
| 117 | #define ATMEL_BASE_SPI1 0xfc000000 | |
| 118 | #define ATMEL_BASE_UART3 0xfc008000 | |
| 119 | #define ATMEL_BASE_UART4 0xfc00c000 | |
| 120 | #define ATMEL_BASE_TWI1 0xfc028000 | |
| 121 | #define ATMEL_BASE_UDPHS 0xfc02c000 | |
| 122 | ||
| 123 | #define ATMEL_BASE_PIOA 0xfc038000 | |
| 37dadbca | 124 | #define ATMEL_BASE_MATRIX1 0xfc03c000 |
| 75238f23 WY |
125 | |
| 126 | #define ATMEL_CHIPID_CIDR 0xfc069000 | |
| 127 | #define ATMEL_CHIPID_EXID 0xfc069004 | |
| 128 | ||
| 129 | /* | |
| 130 | * Address Memory Space | |
| 131 | */ | |
| cc434ad5 | 132 | #define ATMEL_BASE_CS0 0x10000000 |
| 75238f23 | 133 | #define ATMEL_BASE_DDRCS 0x20000000 |
| cc434ad5 WY |
134 | #define ATMEL_BASE_CS1 0x60000000 |
| 135 | #define ATMEL_BASE_CS2 0x70000000 | |
| 136 | #define ATMEL_BASE_CS3 0x80000000 | |
| 75238f23 WY |
137 | #define ATMEL_BASE_QSPI0_AES_MEM 0x90000000 |
| 138 | #define ATMEL_BASE_QSPI1_AES_MEM 0x98000000 | |
| 139 | #define ATMEL_BASE_SDMMC0 0xa0000000 | |
| 140 | #define ATMEL_BASE_SDMMC1 0xb0000000 | |
| 141 | #define ATMEL_BASE_QSPI0_MEM 0xd0000000 | |
| 142 | #define ATMEL_BASE_QSPI1_MEM 0xd8000000 | |
| 143 | ||
| 144 | /* | |
| 145 | * Internal Memories | |
| 146 | */ | |
| 147 | #define ATMEL_BASE_UDPHS_FIFO 0x00300000 /* USB Device HS controller */ | |
| 148 | #define ATMEL_BASE_OHCI 0x00400000 /* USB Host controller (OHCI) */ | |
| 149 | #define ATMEL_BASE_EHCI 0x00500000 /* USB Host controller (EHCI) */ | |
| 150 | ||
| 151 | /* | |
| 152 | * SYSC Spawns | |
| 153 | */ | |
| 154 | #define ATMEL_BASE_RSTC ATMEL_BASE_SYSC | |
| 155 | #define ATMEL_BASE_SHDWC (ATMEL_BASE_SYSC + 0x10) | |
| 156 | #define ATMEL_BASE_PIT (ATMEL_BASE_SYSC + 0x30) | |
| 157 | #define ATMEL_BASE_WDT (ATMEL_BASE_SYSC + 0x40) | |
| 158 | #define ATMEL_BASE_SCKC (ATMEL_BASE_SYSC + 0x50) | |
| 159 | #define ATMEL_BASE_RTC (ATMEL_BASE_SYSC + 0xb0) | |
| 160 | ||
| 161 | /* | |
| 162 | * Other misc definitions | |
| 163 | */ | |
| 164 | #define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70) | |
| 165 | #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500) | |
| cc434ad5 | 166 | #define ATMEL_BASE_SMC (ATMEL_BASE_HSMC + 0x700) |
| 75238f23 WY |
167 | |
| 168 | #define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) | |
| 169 | #define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) | |
| 170 | #define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40) | |
| 171 | ||
| 172 | #define ATMEL_PIO_PORTS 4 | |
| 173 | #define CPU_HAS_PCR | |
| 174 | #define CPU_HAS_H32MXDIV | |
| 175 | ||
| 37dadbca WY |
176 | /* AICREDIR Unlock Key */ |
| 177 | #define ATMEL_SFR_AICREDIR_KEY 0xB6D81C4D | |
| 178 | ||
| 179 | /* MATRIX0(H64MX) slave id definitions */ | |
| 180 | #define H64MX_SLAVE_AXIMX_BRIDGE 0 /* Bridge from H64MX to AXIMX */ | |
| 181 | #define H64MX_SLAVE_PERIPH_BRIDGE 1 /* H64MX Peripheral Bridge */ | |
| 182 | #define H64MX_SLAVE_DDRC_PORT0 2 /* DDR2 Port0-AESOTF */ | |
| 183 | #define H64MX_SLAVE_DDRC_PORT1 3 /* DDR2 Port1 */ | |
| 184 | #define H64MX_SLAVE_DDRC_PORT2 4 /* DDR2 Port2 */ | |
| 185 | #define H64MX_SLAVE_DDRC_PORT3 5 /* DDR2 Port3 */ | |
| 186 | #define H64MX_SLAVE_DDRC_PORT4 6 /* DDR2 Port4 */ | |
| 187 | #define H64MX_SLAVE_DDRC_PORT5 7 /* DDR2 Port5 */ | |
| 188 | #define H64MX_SLAVE_DDRC_PORT6 8 /* DDR2 Port6 */ | |
| 189 | #define H64MX_SLAVE_DDRC_PORT7 9 /* DDR2 Port7 */ | |
| 190 | #define H64MX_SLAVE_SRAM 10 /* Internal SRAM 128K */ | |
| 191 | #define H64MX_SLAVE_CACHE_L2 11 /* Internal SRAM 128K(L2) */ | |
| 192 | #define H64MX_SLAVE_QSPI0 12 /* QSPI0 */ | |
| 193 | #define H64MX_SLAVE_QSPI1 13 /* QSPI1 */ | |
| 194 | #define H64MX_SLAVE_AESB 14 /* AESB */ | |
| 195 | ||
| 196 | /* MATRIX1(H32MX) slave id definitions */ | |
| 197 | #define H32MX_SLAVE_H64MX_BRIDGE 0 /* Bridge from H32MX to H64MX */ | |
| 198 | #define H32MX_SLAVE_PERIPH_BRIDGE0 1 /* H32MX Peripheral Bridge 0 */ | |
| 199 | #define H32MX_SLAVE_PERIPH_BRIDGE1 2 /* H32MX Peripheral Bridge 1 */ | |
| 200 | #define H32MX_SLAVE_EBI 3 /* External Bus Interface */ | |
| 201 | #define H32MX_SLAVE_NFC_CMD 3 /* NFC command Register */ | |
| 202 | #define H32MX_SLAVE_NFC_SRAM 4 /* NFC SRAM */ | |
| 203 | #define H32MX_SLAVE_USB 5 /* USB Device & Host */ | |
| 204 | ||
| 75238f23 WY |
205 | /* SAMA5D2 series chip id definitions */ |
| 206 | #define ARCH_ID_SAMA5D2 0x8a5c08c0 | |
| 207 | #define ARCH_EXID_SAMA5D21CU 0x0000005a | |
| 208 | #define ARCH_EXID_SAMA5D22CU 0x00000059 | |
| 209 | #define ARCH_EXID_SAMA5D22CN 0x00000069 | |
| 210 | #define ARCH_EXID_SAMA5D23CU 0x00000058 | |
| 211 | #define ARCH_EXID_SAMA5D24CX 0x00000004 | |
| 212 | #define ARCH_EXID_SAMA5D24CU 0x00000014 | |
| 213 | #define ARCH_EXID_SAMA5D26CU 0x00000012 | |
| 214 | #define ARCH_EXID_SAMA5D27CU 0x00000011 | |
| 215 | #define ARCH_EXID_SAMA5D27CN 0x00000021 | |
| 216 | #define ARCH_EXID_SAMA5D28CU 0x00000010 | |
| 217 | #define ARCH_EXID_SAMA5D28CN 0x00000020 | |
| 218 | ||
| 245cbc58 WY |
219 | #define ARCH_ID_SAMA5D2_SIP 0x8a5c08c2 |
| 220 | #define ARCH_EXID_SAMA5D225C_D1M 0x00000053 | |
| 221 | #define ARCH_EXID_SAMA5D27C_D5M 0x00000032 | |
| 222 | #define ARCH_EXID_SAMA5D27C_D1G 0x00000033 | |
| 223 | #define ARCH_EXID_SAMA5D28C_D1G 0x00000013 | |
| 75238f23 WY |
224 | |
| 225 | /* PIT Timer(PIT_PIIR) */ | |
| 226 | #define CONFIG_SYS_TIMER_COUNTER 0xf804803c | |
| 227 | ||
| 228 | /* No PMECC Galois table in ROM */ | |
| 229 | #define NO_GALOIS_TABLE_IN_ROM | |
| 230 | ||
| 231 | #ifndef __ASSEMBLY__ | |
| 232 | unsigned int get_chip_id(void); | |
| 233 | unsigned int get_extension_chip_id(void); | |
| 245cbc58 | 234 | int cpu_is_sama5d2(void); |
| 75238f23 WY |
235 | unsigned int has_lcdc(void); |
| 236 | char *get_cpu_name(void); | |
| 237 | #endif | |
| 238 | ||
| 239 | #endif |