[people/ms/u-boot.git] / arch / arm / mach-bcm283x / reset.c

/*
 * (C) Copyright 2012 Stephen Warren
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/wdog.h>
#include <efi_loader.h>

#define RESET_TIMEOUT 10

/*
 * The Raspberry Pi firmware uses the RSTS register to know which partiton
 * to boot from. The partiton value is spread into bits 0, 2, 4, 6, 8, 10.
 * Partiton 63 is a special partition used by the firmware to indicate halt.
 */
#define BCM2835_WDOG_RSTS_RASPBERRYPI_HALT	0x555

__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
	(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;

void __efi_runtime reset_cpu(ulong addr)
{
	uint32_t rstc;

	rstc = readl(&wdog_regs->rstc);
	rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK;
	rstc |= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET;

	writel(BCM2835_WDOG_PASSWORD | RESET_TIMEOUT, &wdog_regs->wdog);
	writel(BCM2835_WDOG_PASSWORD | rstc, &wdog_regs->rstc);
}

#ifdef CONFIG_EFI_LOADER

void __efi_runtime EFIAPI efi_reset_system(
			enum efi_reset_type reset_type,
			efi_status_t reset_status,
			unsigned long data_size, void *reset_data)
{
	u32 val;

	switch (reset_type) {
	case EFI_RESET_COLD:
	case EFI_RESET_WARM:
		reset_cpu(0);
		break;
	case EFI_RESET_SHUTDOWN:
		/*
		 * We set the watchdog hard reset bit here to distinguish this reset
		 * from the normal (full) reset. bootcode.bin will not reboot after a
		 * hard reset.
		 */
		val = readl(&wdog_regs->rsts);
		val |= BCM2835_WDOG_PASSWORD;
		val |= BCM2835_WDOG_RSTS_RASPBERRYPI_HALT;
		writel(val, &wdog_regs->rsts);
		reset_cpu(0);
		break;
	}

	while (1) { }
}

void efi_reset_system_init(void)
{
	efi_add_runtime_mmio(&wdog_regs, sizeof(*wdog_regs));
}

#endif
Commit	Line	Data
efad6cf8 SW	1	/*
	2	* (C) Copyright 2012 Stephen Warren
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
5b8031cc	7	* SPDX-License-Identifier: GPL-2.0
efad6cf8 SW	8	*/
	9
	10	#include <common.h>
	11	#include <asm/io.h>
	12	#include <asm/arch/wdog.h>
6b0ee506	13	#include <efi_loader.h>
efad6cf8 SW	14
	15	#define RESET_TIMEOUT 10
	16
6b0ee506 AG	17	/*
	18	* The Raspberry Pi firmware uses the RSTS register to know which partiton
	19	* to boot from. The partiton value is spread into bits 0, 2, 4, 6, 8, 10.
	20	* Partiton 63 is a special partition used by the firmware to indicate halt.
	21	*/
	22	#define BCM2835_WDOG_RSTS_RASPBERRYPI_HALT 0x555
	23
	24	__efi_runtime_data struct bcm2835_wdog_regs *wdog_regs =
	25	(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
	26
	27	void __efi_runtime reset_cpu(ulong addr)
efad6cf8	28	{
efad6cf8 SW	29	uint32_t rstc;
efad6cf8 SW	30
6b0ee506	31	rstc = readl(&wdog_regs->rstc);
efad6cf8 SW	32	rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK;
	33	rstc \|= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET;
	34
6b0ee506 AG	35	writel(BCM2835_WDOG_PASSWORD \| RESET_TIMEOUT, &wdog_regs->wdog);
	36	writel(BCM2835_WDOG_PASSWORD \| rstc, &wdog_regs->rstc);
	37	}
	38
	39	#ifdef CONFIG_EFI_LOADER
	40
	41	void __efi_runtime EFIAPI efi_reset_system(
	42	enum efi_reset_type reset_type,
	43	efi_status_t reset_status,
	44	unsigned long data_size, void *reset_data)
	45	{
	46	u32 val;
	47
	48	switch (reset_type) {
	49	case EFI_RESET_COLD:
	50	case EFI_RESET_WARM:
	51	reset_cpu(0);
	52	break;
	53	case EFI_RESET_SHUTDOWN:
	54	/*
	55	* We set the watchdog hard reset bit here to distinguish this reset
	56	* from the normal (full) reset. bootcode.bin will not reboot after a
	57	* hard reset.
	58	*/
	59	val = readl(&wdog_regs->rsts);
	60	val \|= BCM2835_WDOG_PASSWORD;
	61	val \|= BCM2835_WDOG_RSTS_RASPBERRYPI_HALT;
	62	writel(val, &wdog_regs->rsts);
	63	reset_cpu(0);
	64	break;
	65	}
	66
	67	while (1) { }
efad6cf8	68	}
6b0ee506 AG	69
	70	void efi_reset_system_init(void)
	71	{
	72	efi_add_runtime_mmio(&wdog_regs, sizeof(*wdog_regs));
	73	}
	74
	75	#endif