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643be9c0 RS |
1 | /* |
2 | * Clock Initialization for board based on EXYNOS4210 | |
3 | * | |
4 | * Copyright (C) 2013 Samsung Electronics | |
5 | * Rajeshwari Shinde <rajeshwari.s@samsung.com> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <config.h> | |
643be9c0 RS |
28 | #include <asm/io.h> |
29 | #include <asm/arch/cpu.h> | |
30 | #include <asm/arch/clk.h> | |
31 | #include <asm/arch/clock.h> | |
32 | #include "common_setup.h" | |
33 | #include "exynos4_setup.h" | |
34 | ||
35 | /* | |
36 | * system_clock_init: Initialize core clock and bus clock. | |
37 | * void system_clock_init(void) | |
38 | */ | |
39 | void system_clock_init(void) | |
40 | { | |
41 | struct exynos4_clock *clk = | |
42 | (struct exynos4_clock *)samsung_get_base_clock(); | |
43 | ||
44 | writel(CLK_SRC_CPU_VAL, &clk->src_cpu); | |
45 | ||
46 | sdelay(0x10000); | |
47 | ||
48 | writel(CLK_SRC_TOP0_VAL, &clk->src_top0); | |
49 | writel(CLK_SRC_TOP1_VAL, &clk->src_top1); | |
50 | writel(CLK_SRC_DMC_VAL, &clk->src_dmc); | |
51 | writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus); | |
52 | writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus); | |
53 | writel(CLK_SRC_FSYS_VAL, &clk->src_fsys); | |
54 | writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0); | |
55 | writel(CLK_SRC_CAM_VAL, &clk->src_cam); | |
56 | writel(CLK_SRC_MFC_VAL, &clk->src_mfc); | |
57 | writel(CLK_SRC_G3D_VAL, &clk->src_g3d); | |
58 | writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0); | |
59 | ||
60 | sdelay(0x10000); | |
61 | ||
62 | writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); | |
63 | writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); | |
64 | writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0); | |
65 | writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1); | |
66 | writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus); | |
67 | writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus); | |
68 | writel(CLK_DIV_TOP_VAL, &clk->div_top); | |
69 | writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); | |
70 | writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); | |
71 | writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3); | |
72 | writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0); | |
73 | writel(CLK_DIV_CAM_VAL, &clk->div_cam); | |
74 | writel(CLK_DIV_MFC_VAL, &clk->div_mfc); | |
75 | writel(CLK_DIV_G3D_VAL, &clk->div_g3d); | |
76 | writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0); | |
77 | ||
78 | /* Set PLL locktime */ | |
79 | writel(PLL_LOCKTIME, &clk->apll_lock); | |
80 | writel(PLL_LOCKTIME, &clk->mpll_lock); | |
81 | writel(PLL_LOCKTIME, &clk->epll_lock); | |
82 | writel(PLL_LOCKTIME, &clk->vpll_lock); | |
83 | ||
84 | writel(APLL_CON1_VAL, &clk->apll_con1); | |
85 | writel(APLL_CON0_VAL, &clk->apll_con0); | |
86 | writel(MPLL_CON1_VAL, &clk->mpll_con1); | |
87 | writel(MPLL_CON0_VAL, &clk->mpll_con0); | |
88 | writel(EPLL_CON1_VAL, &clk->epll_con1); | |
89 | writel(EPLL_CON0_VAL, &clk->epll_con0); | |
90 | writel(VPLL_CON1_VAL, &clk->vpll_con1); | |
91 | writel(VPLL_CON0_VAL, &clk->vpll_con0); | |
92 | ||
93 | sdelay(0x30000); | |
94 | } |