[people/ms/u-boot.git] / arch / arm / mach-exynos / exynos4_setup.h

/*
 * Machine Specific Values for EXYNOS4012 based board
 *
 * Copyright (C) 2011 Samsung Electronics
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _ORIGEN_SETUP_H
#define _ORIGEN_SETUP_H

#include <config.h>
#include <asm/arch/cpu.h>

#ifdef CONFIG_CLK_800_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_200_200
#define DRAM_CLK_200
#endif
#ifdef CONFIG_CLK_1000_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_400_200
#define DRAM_CLK_400
#endif

/* Bus Configuration Register Address */
#define ASYNC_CONFIG		0x10010350

/* CLK_SRC_CPU */
#define MUX_HPM_SEL_MOUTAPLL		0x0
#define MUX_HPM_SEL_SCLKMPLL		0x1
#define MUX_CORE_SEL_MOUTAPLL		0x0
#define MUX_CORE_SEL_SCLKMPLL		0x1
#define MUX_MPLL_SEL_FILPLL		0x0
#define MUX_MPLL_SEL_MOUTMPLLFOUT	0x1
#define MUX_APLL_SEL_FILPLL		0x0
#define MUX_APLL_SEL_MOUTMPLLFOUT	0x1
#define CLK_SRC_CPU_VAL			((MUX_HPM_SEL_MOUTAPLL << 20) \
					| (MUX_CORE_SEL_MOUTAPLL << 16) \
					| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
					| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))

/* CLK_DIV_CPU0 */
#define APLL_RATIO		0x0
#define PCLK_DBG_RATIO		0x1
#define ATB_RATIO		0x3
#define PERIPH_RATIO		0x3
#define COREM1_RATIO		0x7
#define COREM0_RATIO		0x3
#define CORE_RATIO		0x0
#define CLK_DIV_CPU0_VAL	((APLL_RATIO << 24) \
				| (PCLK_DBG_RATIO << 20) \
				| (ATB_RATIO << 16) \
				| (PERIPH_RATIO << 12) \
				| (COREM1_RATIO << 8) \
				| (COREM0_RATIO << 4) \
				| (CORE_RATIO << 0))

/* CLK_DIV_CPU1 */
#define HPM_RATIO		0x0
#define COPY_RATIO		0x3
#define CLK_DIV_CPU1_VAL	((HPM_RATIO << 4) | (COPY_RATIO))

/* CLK_SRC_DMC */
#define MUX_PWI_SEL_XXTI		0x0
#define MUX_PWI_SEL_XUSBXTI		0x1
#define MUX_PWI_SEL_SCLK_HDMI24M	0x2
#define MUX_PWI_SEL_SCLK_USBPHY0	0x3
#define MUX_PWI_SEL_SCLK_USBPHY1	0x4
#define MUX_PWI_SEL_SCLK_HDMIPHY	0x5
#define MUX_PWI_SEL_SCLKMPLL		0x6
#define MUX_PWI_SEL_SCLKEPLL		0x7
#define MUX_PWI_SEL_SCLKVPLL		0x8
#define MUX_DPHY_SEL_SCLKMPLL		0x0
#define MUX_DPHY_SEL_SCLKAPLL		0x1
#define MUX_DMC_BUS_SEL_SCLKMPLL	0x0
#define MUX_DMC_BUS_SEL_SCLKAPLL	0x1
#define CLK_SRC_DMC_VAL			((MUX_PWI_SEL_XUSBXTI << 16) \
					| (MUX_DPHY_SEL_SCLKMPLL << 8) \
					| (MUX_DMC_BUS_SEL_SCLKMPLL << 4))

/* CLK_DIV_DMC0 */
#define CORE_TIMERS_RATIO	0x1
#define COPY2_RATIO		0x3
#define DMCP_RATIO		0x1
#define DMCD_RATIO		0x1
#define DMC_RATIO		0x1
#define DPHY_RATIO		0x1
#define ACP_PCLK_RATIO		0x1
#define ACP_RATIO		0x3
#define CLK_DIV_DMC0_VAL	((CORE_TIMERS_RATIO << 28) \
				| (COPY2_RATIO << 24) \
				| (DMCP_RATIO << 20) \
				| (DMCD_RATIO << 16) \
				| (DMC_RATIO << 12) \
				| (DPHY_RATIO << 8) \
				| (ACP_PCLK_RATIO << 4)	\
				| (ACP_RATIO << 0))

/* CLK_DIV_DMC1 */
#define DPM_RATIO		0x1
#define DVSEM_RATIO		0x1
#define PWI_RATIO		0x1
#define CLK_DIV_DMC1_VAL	((DPM_RATIO << 24) \
				| (DVSEM_RATIO << 16) \
				| (PWI_RATIO << 8))

/* CLK_SRC_TOP0 */
#define MUX_ONENAND_SEL_ACLK_133	0x0
#define MUX_ONENAND_SEL_ACLK_160	0x1
#define MUX_ACLK_133_SEL_SCLKMPLL	0x0
#define MUX_ACLK_133_SEL_SCLKAPLL	0x1
#define MUX_ACLK_160_SEL_SCLKMPLL	0x0
#define MUX_ACLK_160_SEL_SCLKAPLL	0x1
#define MUX_ACLK_100_SEL_SCLKMPLL	0x0
#define MUX_ACLK_100_SEL_SCLKAPLL	0x1
#define MUX_ACLK_200_SEL_SCLKMPLL	0x0
#define MUX_ACLK_200_SEL_SCLKAPLL	0x1
#define MUX_VPLL_SEL_FINPLL		0x0
#define MUX_VPLL_SEL_FOUTVPLL		0x1
#define MUX_EPLL_SEL_FINPLL		0x0
#define MUX_EPLL_SEL_FOUTEPLL		0x1
#define MUX_ONENAND_1_SEL_MOUTONENAND	0x0
#define MUX_ONENAND_1_SEL_SCLKVPLL	0x1
#define CLK_SRC_TOP0_VAL		((MUX_ONENAND_SEL_ACLK_133 << 28) \
					| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
					| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
					| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
					| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
					| (MUX_VPLL_SEL_FINPLL << 8) \
					| (MUX_EPLL_SEL_FINPLL << 4)\
					| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))

/* CLK_SRC_TOP1 */
#define VPLLSRC_SEL_FINPLL	0x0
#define VPLLSRC_SEL_SCLKHDMI24M	0x1
#define CLK_SRC_TOP1_VAL	(VPLLSRC_SEL_FINPLL)

/* CLK_DIV_TOP */
#define ONENAND_RATIO		0x0
#define ACLK_133_RATIO		0x5
#define ACLK_160_RATIO		0x4
#define ACLK_100_RATIO		0x7
#define ACLK_200_RATIO		0x3
#define CLK_DIV_TOP_VAL		((ONENAND_RATIO << 16)	\
				| (ACLK_133_RATIO << 12)\
				| (ACLK_160_RATIO << 8)	\
				| (ACLK_100_RATIO << 4)	\
				| (ACLK_200_RATIO << 0))

/* CLK_SRC_LEFTBUS */
#define MUX_GDL_SEL_SCLKMPLL	0x0
#define MUX_GDL_SEL_SCLKAPLL	0x1
#define CLK_SRC_LEFTBUS_VAL	(MUX_GDL_SEL_SCLKMPLL)

/* CLK_DIV_LEFTBUS */
#define GPL_RATIO		0x1
#define GDL_RATIO		0x3
#define CLK_DIV_LEFTBUS_VAL	((GPL_RATIO << 4) | (GDL_RATIO))

/* CLK_SRC_RIGHTBUS */
#define MUX_GDR_SEL_SCLKMPLL	0x0
#define MUX_GDR_SEL_SCLKAPLL	0x1
#define CLK_SRC_RIGHTBUS_VAL	(MUX_GDR_SEL_SCLKMPLL)

/* CLK_DIV_RIGHTBUS */
#define GPR_RATIO		0x1
#define GDR_RATIO		0x3
#define CLK_DIV_RIGHTBUS_VAL	((GPR_RATIO << 4) | (GDR_RATIO))

/* CLK_SRS_FSYS: 6 = SCLKMPLL */
#define SATA_SEL_SCLKMPLL	0
#define SATA_SEL_SCLKAPLL	1

#define MMC_SEL_XXTI		0
#define MMC_SEL_XUSBXTI		1
#define MMC_SEL_SCLK_HDMI24M	2
#define MMC_SEL_SCLK_USBPHY0	3
#define MMC_SEL_SCLK_USBPHY1	4
#define MMC_SEL_SCLK_HDMIPHY	5
#define MMC_SEL_SCLKMPLL	6
#define MMC_SEL_SCLKEPLL	7
#define MMC_SEL_SCLKVPLL	8

#define MMCC0_SEL		MMC_SEL_SCLKMPLL
#define MMCC1_SEL		MMC_SEL_SCLKMPLL
#define MMCC2_SEL		MMC_SEL_SCLKMPLL
#define MMCC3_SEL		MMC_SEL_SCLKMPLL
#define MMCC4_SEL		MMC_SEL_SCLKMPLL
#define CLK_SRC_FSYS_VAL	((SATA_SEL_SCLKMPLL << 24) \
				| (MMCC4_SEL << 16) \
				| (MMCC3_SEL << 12) \
				| (MMCC2_SEL << 8) \
				| (MMCC1_SEL << 4) \
				| (MMCC0_SEL << 0))

/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
/* CLK_DIV_FSYS1 */
#define MMC0_RATIO		0xF
#define MMC0_PRE_RATIO		0x0
#define MMC1_RATIO		0xF
#define MMC1_PRE_RATIO		0x0
#define CLK_DIV_FSYS1_VAL	((MMC1_PRE_RATIO << 24) \
				| (MMC1_RATIO << 16) \
				| (MMC0_PRE_RATIO << 8) \
				| (MMC0_RATIO << 0))

/* CLK_DIV_FSYS2 */
#define MMC2_RATIO		0xF
#define MMC2_PRE_RATIO		0x0
#define MMC3_RATIO		0xF
#define MMC3_PRE_RATIO		0x0
#define CLK_DIV_FSYS2_VAL	((MMC3_PRE_RATIO << 24) \
				| (MMC3_RATIO << 16) \
				| (MMC2_PRE_RATIO << 8) \
				| (MMC2_RATIO << 0))

/* CLK_DIV_FSYS3 */
#define MMC4_RATIO		0xF
#define MMC4_PRE_RATIO		0x0
#define CLK_DIV_FSYS3_VAL	((MMC4_PRE_RATIO << 8) \
				| (MMC4_RATIO << 0))

/* CLK_SRC_PERIL0 */
#define UART_SEL_XXTI		0
#define UART_SEL_XUSBXTI	1
#define UART_SEL_SCLK_HDMI24M	2
#define UART_SEL_SCLK_USBPHY0	3
#define UART_SEL_SCLK_USBPHY1	4
#define UART_SEL_SCLK_HDMIPHY	5
#define UART_SEL_SCLKMPLL	6
#define UART_SEL_SCLKEPLL	7
#define UART_SEL_SCLKVPLL	8

#define UART0_SEL		UART_SEL_SCLKMPLL
#define UART1_SEL		UART_SEL_SCLKMPLL
#define UART2_SEL		UART_SEL_SCLKMPLL
#define UART3_SEL		UART_SEL_SCLKMPLL
#define UART4_SEL		UART_SEL_SCLKMPLL
#define CLK_SRC_PERIL0_VAL	((UART4_SEL << 16) \
				| (UART3_SEL << 12) \
				| (UART2_SEL << 8) \
				| (UART1_SEL << 4) \
				| (UART0_SEL << 0))

/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
/* CLK_DIV_PERIL0 */
#define UART0_RATIO		7
#define UART1_RATIO		7
#define UART2_RATIO		7
#define UART3_RATIO		7
#define UART4_RATIO		7
#define CLK_DIV_PERIL0_VAL	((UART4_RATIO << 16) \
				| (UART3_RATIO << 12) \
				| (UART2_RATIO << 8) \
				| (UART1_RATIO << 4) \
				| (UART0_RATIO << 0))

/* Clock Source CAM/FIMC */
/* CLK_SRC_CAM */
#define CAM0_SEL_XUSBXTI	1
#define CAM1_SEL_XUSBXTI	1
#define CSIS0_SEL_XUSBXTI	1
#define CSIS1_SEL_XUSBXTI	1

#define FIMC_SEL_SCLKMPLL	6
#define FIMC0_LCLK_SEL		FIMC_SEL_SCLKMPLL
#define FIMC1_LCLK_SEL		FIMC_SEL_SCLKMPLL
#define FIMC2_LCLK_SEL		FIMC_SEL_SCLKMPLL
#define FIMC3_LCLK_SEL		FIMC_SEL_SCLKMPLL

#define CLK_SRC_CAM_VAL		((CSIS1_SEL_XUSBXTI << 28) \
				| (CSIS0_SEL_XUSBXTI << 24) \
				| (CAM1_SEL_XUSBXTI << 20) \
				| (CAM0_SEL_XUSBXTI << 16) \
				| (FIMC3_LCLK_SEL << 12) \
				| (FIMC2_LCLK_SEL << 8) \
				| (FIMC1_LCLK_SEL << 4) \
				| (FIMC0_LCLK_SEL << 0))

/* SCLK CAM */
/* CLK_DIV_CAM */
#define FIMC0_LCLK_RATIO	4
#define FIMC1_LCLK_RATIO	4
#define FIMC2_LCLK_RATIO	4
#define FIMC3_LCLK_RATIO	4
#define CLK_DIV_CAM_VAL		((FIMC3_LCLK_RATIO << 12) \
				| (FIMC2_LCLK_RATIO << 8) \
				| (FIMC1_LCLK_RATIO << 4) \
				| (FIMC0_LCLK_RATIO << 0))

/* SCLK MFC */
/* CLK_SRC_MFC */
#define MFC_SEL_MPLL		0
#define MOUTMFC_0		0
#define MFC_SEL			MOUTMFC_0
#define MFC_0_SEL		MFC_SEL_MPLL
#define CLK_SRC_MFC_VAL		((MFC_SEL << 8) | (MFC_0_SEL))


/* CLK_DIV_MFC */
#define MFC_RATIO		3
#define CLK_DIV_MFC_VAL		(MFC_RATIO)

/* SCLK G3D */
/* CLK_SRC_G3D */
#define G3D_SEL_MPLL		0
#define MOUTG3D_0		0
#define G3D_SEL			MOUTG3D_0
#define G3D_0_SEL		G3D_SEL_MPLL
#define CLK_SRC_G3D_VAL		((G3D_SEL << 8) | (G3D_0_SEL))

/* CLK_DIV_G3D */
#define G3D_RATIO		1
#define CLK_DIV_G3D_VAL		(G3D_RATIO)

/* SCLK LCD0 */
/* CLK_SRC_LCD0 */
#define FIMD_SEL_SCLKMPLL	6
#define MDNIE0_SEL_XUSBXTI	1
#define MDNIE_PWM0_SEL_XUSBXTI	1
#define MIPI0_SEL_XUSBXTI	1
#define CLK_SRC_LCD0_VAL	((MIPI0_SEL_XUSBXTI << 12) \
				| (MDNIE_PWM0_SEL_XUSBXTI << 8) \
				| (MDNIE0_SEL_XUSBXTI << 4) \
				| (FIMD_SEL_SCLKMPLL << 0))

/* CLK_DIV_LCD0 */
#define FIMD0_RATIO		4
#define CLK_DIV_LCD0_VAL	(FIMD0_RATIO)

/* Required period to generate a stable clock output */
/* PLL_LOCK_TIME */
#define PLL_LOCKTIME		0x1C20

/* PLL Values */
#define DISABLE			0
#define ENABLE			1
#define SET_PLL(mdiv, pdiv, sdiv)	((ENABLE << 31)\
					| (mdiv << 16) \
					| (pdiv << 8) \
					| (sdiv << 0))

/* APLL_CON0 */
#define APLL_MDIV		0xFA
#define APLL_PDIV		0x6
#define APLL_SDIV		0x1
#define APLL_CON0_VAL		SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)

/* APLL_CON1 */
#define APLL_AFC_ENB		0x1
#define APLL_AFC		0xC
#define APLL_CON1_VAL		((APLL_AFC_ENB << 31) | (APLL_AFC << 0))

/* MPLL_CON0 */
#define MPLL_MDIV		0xC8
#define MPLL_PDIV		0x6
#define MPLL_SDIV		0x1
#define MPLL_CON0_VAL		SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)

/* MPLL_CON1 */
#define MPLL_AFC_ENB		0x0
#define MPLL_AFC		0x1C
#define MPLL_CON1_VAL		((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))

/* EPLL_CON0 */
#define EPLL_MDIV		0x30
#define EPLL_PDIV		0x3
#define EPLL_SDIV		0x2
#define EPLL_CON0_VAL		SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)

/* EPLL_CON1 */
#define EPLL_K			0x0
#define EPLL_CON1_VAL		(EPLL_K >> 0)

/* VPLL_CON0 */
#define VPLL_MDIV		0x35
#define VPLL_PDIV		0x3
#define VPLL_SDIV		0x2
#define VPLL_CON0_VAL		SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)

/* VPLL_CON1 */
#define VPLL_SSCG_EN		DISABLE
#define VPLL_SEL_PF_DN_SPREAD	0x0
#define VPLL_MRR		0x11
#define VPLL_MFR		0x0
#define VPLL_K			0x400
#define VPLL_CON1_VAL		((VPLL_SSCG_EN << 31)\
				| (VPLL_SEL_PF_DN_SPREAD << 29) \
				| (VPLL_MRR << 24) \
				| (VPLL_MFR << 16) \
				| (VPLL_K << 0))

/* DMC */
#define DIRECT_CMD_NOP	0x07000000
#define DIRECT_CMD_ZQ	0x0a000000
#define DIRECT_CMD_CHIP1_SHIFT	(1 << 20)
#define MEM_TIMINGS_MSR_COUNT	4
#define CTRL_START	(1 << 0)
#define CTRL_DLL_ON	(1 << 1)
#define AREF_EN		(1 << 5)
#define DRV_TYPE	(1 << 6)

struct mem_timings {
	unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
	unsigned timingref;
	unsigned timingrow;
	unsigned timingdata;
	unsigned timingpower;
	unsigned zqcontrol;
	unsigned control0;
	unsigned control1;
	unsigned control2;
	unsigned concontrol;
	unsigned prechconfig;
	unsigned memcontrol;
	unsigned memconfig0;
	unsigned memconfig1;
	unsigned dll_resync;
	unsigned dll_on;
};

/* MIU */
/* MIU Config Register Offsets*/
#define APB_SFR_INTERLEAVE_CONF_OFFSET	0x400
#define APB_SFR_ARBRITATION_CONF_OFFSET	0xC00
#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET	0x800
#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET	0x808
#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET	0x810
#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET	0x818
#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET	0x820
#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET	0x828
#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET	0x830

#ifdef CONFIG_ORIGEN
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
#define APB_SFR_INTERLEAVE_CONF_VAL	0x20001507
#define APB_SFR_ARBRITATION_CONF_VAL	0x00000001
#endif

#define INTERLEAVE_ADDR_MAP_START_ADDR	0x40000000
#define INTERLEAVE_ADDR_MAP_END_ADDR	0xbfffffff
#define INTERLEAVE_ADDR_MAP_EN		0x00000001

#ifdef CONFIG_MIU_1BIT_INTERLEAVED
/* Interleave_bit0: 0xC*/
#define APB_SFR_INTERLEAVE_CONF_VAL	0x0000000c
#endif
#ifdef CONFIG_MIU_2BIT_INTERLEAVED
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
#define APB_SFR_INTERLEAVE_CONF_VAL	0x2000150c
#endif
#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR	0x40000000
#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR		0x7fffffff
#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR	0x80000000
#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR		0xbfffffff
/* Enable SME0 and SME1*/
#define APB_SFR_SLV_ADDR_MAP_CONF_VAL		0x00000006

#define FORCE_DLL_RESYNC	3
#define DLL_CONTROL_ON		1

#define DIRECT_CMD1	0x00020000
#define DIRECT_CMD2	0x00030000
#define DIRECT_CMD3	0x00010002
#define DIRECT_CMD4	0x00000328

#define CTRL_ZQ_MODE_NOTERM	(0x1 << 0)
#define CTRL_ZQ_START		(0x1 << 1)
#define CTRL_ZQ_DIV		(0 << 4)
#define CTRL_ZQ_MODE_DDS	(0x7 << 8)
#define CTRL_ZQ_MODE_TERM	(0x2 << 11)
#define CTRL_ZQ_FORCE_IMPN	(0x5 << 14)
#define CTRL_ZQ_FORCE_IMPP	(0x6 << 17)
#define CTRL_DCC		(0xE38 << 20)
#define ZQ_CONTROL_VAL		(CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
				| CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
				| CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
				| CTRL_ZQ_FORCE_IMPP | CTRL_DCC)

#define ASYNC			(0 << 0)
#define CLK_RATIO		(1 << 1)
#define DIV_PIPE		(1 << 3)
#define AWR_ON			(1 << 4)
#define AREF_DISABLE		(0 << 5)
#define DRV_TYPE_DISABLE	(0 << 6)
#define CHIP0_NOT_EMPTY		(0 << 8)
#define CHIP1_NOT_EMPTY		(0 << 9)
#define DQ_SWAP_DISABLE		(0 << 10)
#define QOS_FAST_DISABLE	(0 << 11)
#define RD_FETCH		(0x3 << 12)
#define TIMEOUT_LEVEL0		(0xFFF << 16)
#define CONCONTROL_VAL		(ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
				| AREF_DISABLE | DRV_TYPE_DISABLE\
				| CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
				| DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
				| RD_FETCH | TIMEOUT_LEVEL0)

#define CLK_STOP_DISABLE	(0 << 1)
#define DPWRDN_DISABLE		(0 << 2)
#define DPWRDN_TYPE		(0 << 3)
#define TP_DISABLE		(0 << 4)
#define DSREF_DIABLE		(0 << 5)
#define ADD_LAT_PALL		(1 << 6)
#define MEM_TYPE_DDR3		(0x6 << 8)
#define MEM_WIDTH_32		(0x2 << 12)
#define NUM_CHIP_2		(1 << 16)
#define BL_8			(0x3 << 20)
#define MEMCONTROL_VAL		(CLK_STOP_DISABLE | DPWRDN_DISABLE\
				| DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
				| ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
				| NUM_CHIP_2 | BL_8)


#define CHIP_BANK_8		(0x3 << 0)
#define CHIP_ROW_14		(0x2 << 4)
#define CHIP_COL_10		(0x3 << 8)
#define CHIP_MAP_INTERLEAVED	(1 << 12)
#define CHIP_MASK		(0xe0 << 16)
#ifdef CONFIG_MIU_LINEAR
#define CHIP0_BASE		(0x40 << 24)
#define CHIP1_BASE		(0x60 << 24)
#else
#define CHIP0_BASE		(0x20 << 24)
#define CHIP1_BASE		(0x40 << 24)
#endif
#define MEMCONFIG0_VAL		(CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
				| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
#define MEMCONFIG1_VAL		(CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
				| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)

#define TP_CNT			(0xff << 24)
#define PRECHCONFIG		TP_CNT

#define CTRL_OFF		(0 << 0)
#define CTRL_DLL_OFF		(0 << 1)
#define CTRL_HALF		(0 << 2)
#define CTRL_DFDQS		(1 << 3)
#define DQS_DELAY		(0 << 4)
#define CTRL_START_POINT	(0x10 << 8)
#define CTRL_INC		(0x10 << 16)
#define CTRL_FORCE		(0x71 << 24)
#define CONTROL0_VAL		(CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
				| CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
				| CTRL_INC | CTRL_FORCE)

#define CTRL_SHIFTC		(0x6 << 0)
#define CTRL_REF		(8 << 4)
#define CTRL_SHGATE		(1 << 29)
#define TERM_READ_EN		(1 << 30)
#define TERM_WRITE_EN		(1 << 31)
#define CONTROL1_VAL		(CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
				| TERM_READ_EN | TERM_WRITE_EN)

#define CONTROL2_VAL		0x00000000

#ifdef CONFIG_ORIGEN
#define TIMINGREF_VAL		0x000000BB
#define TIMINGROW_VAL		0x4046654f
#define	TIMINGDATA_VAL		0x46400506
#define	TIMINGPOWER_VAL		0x52000A3C
#else
#define TIMINGREF_VAL		0x000000BC
#ifdef DRAM_CLK_330
#define TIMINGROW_VAL		0x3545548d
#define	TIMINGDATA_VAL		0x45430506
#define	TIMINGPOWER_VAL		0x4439033c
#endif
#ifdef DRAM_CLK_400
#define TIMINGROW_VAL		0x45430506
#define	TIMINGDATA_VAL		0x56500506
#define	TIMINGPOWER_VAL		0x5444033d
#endif
#endif
#endif
Commit	Line	Data
b9a1ef21	1	/*
643be9c0	2	* Machine Specific Values for EXYNOS4012 based board
b9a1ef21 CK	3	*
	4	* Copyright (C) 2011 Samsung Electronics
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
b9a1ef21 CK	7	*/
	8
	9	#ifndef _ORIGEN_SETUP_H
	10	#define _ORIGEN_SETUP_H
	11
	12	#include <config.h>
b9a1ef21 CK	13	#include <asm/arch/cpu.h>
b9a1ef21 CK	14
643be9c0 RS	15	#ifdef CONFIG_CLK_800_330_165
	16	#define DRAM_CLK_330
	17	#endif
	18	#ifdef CONFIG_CLK_1000_200_200
	19	#define DRAM_CLK_200
	20	#endif
	21	#ifdef CONFIG_CLK_1000_330_165
	22	#define DRAM_CLK_330
	23	#endif
	24	#ifdef CONFIG_CLK_1000_400_200
	25	#define DRAM_CLK_400
	26	#endif
b9a1ef21 CK	27
	28	/* Bus Configuration Register Address */
	29	#define ASYNC_CONFIG 0x10010350
	30
b9a1ef21 CK	31	/* CLK_SRC_CPU */
	32	#define MUX_HPM_SEL_MOUTAPLL 0x0
	33	#define MUX_HPM_SEL_SCLKMPLL 0x1
	34	#define MUX_CORE_SEL_MOUTAPLL 0x0
	35	#define MUX_CORE_SEL_SCLKMPLL 0x1
	36	#define MUX_MPLL_SEL_FILPLL 0x0
	37	#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1
	38	#define MUX_APLL_SEL_FILPLL 0x0
	39	#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1
	40	#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \
	41	\| (MUX_CORE_SEL_MOUTAPLL << 16) \
	42	\| (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
	43	\| (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
	44
	45	/* CLK_DIV_CPU0 */
	46	#define APLL_RATIO 0x0
	47	#define PCLK_DBG_RATIO 0x1
	48	#define ATB_RATIO 0x3
	49	#define PERIPH_RATIO 0x3
	50	#define COREM1_RATIO 0x7
	51	#define COREM0_RATIO 0x3
	52	#define CORE_RATIO 0x0
	53	#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \
	54	\| (PCLK_DBG_RATIO << 20) \
	55	\| (ATB_RATIO << 16) \
	56	\| (PERIPH_RATIO << 12) \
	57	\| (COREM1_RATIO << 8) \
	58	\| (COREM0_RATIO << 4) \
	59	\| (CORE_RATIO << 0))
	60
	61	/* CLK_DIV_CPU1 */
	62	#define HPM_RATIO 0x0
	63	#define COPY_RATIO 0x3
	64	#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \| (COPY_RATIO))
	65
	66	/* CLK_SRC_DMC */
	67	#define MUX_PWI_SEL_XXTI 0x0
	68	#define MUX_PWI_SEL_XUSBXTI 0x1
	69	#define MUX_PWI_SEL_SCLK_HDMI24M 0x2
	70	#define MUX_PWI_SEL_SCLK_USBPHY0 0x3
	71	#define MUX_PWI_SEL_SCLK_USBPHY1 0x4
	72	#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5
	73	#define MUX_PWI_SEL_SCLKMPLL 0x6
	74	#define MUX_PWI_SEL_SCLKEPLL 0x7
	75	#define MUX_PWI_SEL_SCLKVPLL 0x8
	76	#define MUX_DPHY_SEL_SCLKMPLL 0x0
	77	#define MUX_DPHY_SEL_SCLKAPLL 0x1
	78	#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0
	79	#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1
	80	#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \
	81	\| (MUX_DPHY_SEL_SCLKMPLL << 8) \
	82	\| (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
	83
	84	/* CLK_DIV_DMC0 */
	85	#define CORE_TIMERS_RATIO 0x1
	86	#define COPY2_RATIO 0x3
	87	#define DMCP_RATIO 0x1
	88	#define DMCD_RATIO 0x1
	89	#define DMC_RATIO 0x1
	90	#define DPHY_RATIO 0x1
	91	#define ACP_PCLK_RATIO 0x1
	92	#define ACP_RATIO 0x3
	93	#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \
	94	\| (COPY2_RATIO << 24) \
95	\| (DMCP_RATIO << 20) \
96	\| (DMCD_RATIO << 16) \
97	\| (DMC_RATIO << 12) \
98	\| (DPHY_RATIO << 8) \
99	\| (ACP_PCLK_RATIO << 4) \
100	\| (ACP_RATIO << 0))
101
102	/* CLK_DIV_DMC1 */
103	#define DPM_RATIO 0x1
104	#define DVSEM_RATIO 0x1
105	#define PWI_RATIO 0x1
106	#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \
107	\| (DVSEM_RATIO << 16) \
108	\| (PWI_RATIO << 8))
109
110	/* CLK_SRC_TOP0 */
111	#define MUX_ONENAND_SEL_ACLK_133 0x0
112	#define MUX_ONENAND_SEL_ACLK_160 0x1
113	#define MUX_ACLK_133_SEL_SCLKMPLL 0x0
114	#define MUX_ACLK_133_SEL_SCLKAPLL 0x1
115	#define MUX_ACLK_160_SEL_SCLKMPLL 0x0
116	#define MUX_ACLK_160_SEL_SCLKAPLL 0x1
117	#define MUX_ACLK_100_SEL_SCLKMPLL 0x0
118	#define MUX_ACLK_100_SEL_SCLKAPLL 0x1
119	#define MUX_ACLK_200_SEL_SCLKMPLL 0x0
120	#define MUX_ACLK_200_SEL_SCLKAPLL 0x1
121	#define MUX_VPLL_SEL_FINPLL 0x0
122	#define MUX_VPLL_SEL_FOUTVPLL 0x1
123	#define MUX_EPLL_SEL_FINPLL 0x0
124	#define MUX_EPLL_SEL_FOUTEPLL 0x1
125	#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0
126	#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1
127	#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \
128	\| (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
129	\| (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
130	\| (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
131	\| (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
132	\| (MUX_VPLL_SEL_FINPLL << 8) \
133	\| (MUX_EPLL_SEL_FINPLL << 4)\
134	\| (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
135
136	/* CLK_SRC_TOP1 */
137	#define VPLLSRC_SEL_FINPLL 0x0
138	#define VPLLSRC_SEL_SCLKHDMI24M 0x1
139	#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL)
140
141	/* CLK_DIV_TOP */
142	#define ONENAND_RATIO 0x0
143	#define ACLK_133_RATIO 0x5
144	#define ACLK_160_RATIO 0x4
145	#define ACLK_100_RATIO 0x7
146	#define ACLK_200_RATIO 0x3
147	#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \
148	\| (ACLK_133_RATIO << 12)\
149	\| (ACLK_160_RATIO << 8) \
150	\| (ACLK_100_RATIO << 4) \
151	\| (ACLK_200_RATIO << 0))
152
153	/* CLK_SRC_LEFTBUS */
154	#define MUX_GDL_SEL_SCLKMPLL 0x0
155	#define MUX_GDL_SEL_SCLKAPLL 0x1
156	#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL)
157
158	/* CLK_DIV_LEFTBUS */
159	#define GPL_RATIO 0x1
160	#define GDL_RATIO 0x3
161	#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) \| (GDL_RATIO))
162
163	/* CLK_SRC_RIGHTBUS */
164	#define MUX_GDR_SEL_SCLKMPLL 0x0
165	#define MUX_GDR_SEL_SCLKAPLL 0x1
166	#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL)
167
168	/* CLK_DIV_RIGHTBUS */
169	#define GPR_RATIO 0x1
170	#define GDR_RATIO 0x3
171	#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) \| (GDR_RATIO))
172
173	/* CLK_SRS_FSYS: 6 = SCLKMPLL */
174	#define SATA_SEL_SCLKMPLL 0
175	#define SATA_SEL_SCLKAPLL 1
176
177	#define MMC_SEL_XXTI 0
178	#define MMC_SEL_XUSBXTI 1
179	#define MMC_SEL_SCLK_HDMI24M 2
180	#define MMC_SEL_SCLK_USBPHY0 3
181	#define MMC_SEL_SCLK_USBPHY1 4
182	#define MMC_SEL_SCLK_HDMIPHY 5
183	#define MMC_SEL_SCLKMPLL 6
184	#define MMC_SEL_SCLKEPLL 7
185	#define MMC_SEL_SCLKVPLL 8
186
187	#define MMCC0_SEL MMC_SEL_SCLKMPLL
188	#define MMCC1_SEL MMC_SEL_SCLKMPLL
189	#define MMCC2_SEL MMC_SEL_SCLKMPLL
190	#define MMCC3_SEL MMC_SEL_SCLKMPLL
191	#define MMCC4_SEL MMC_SEL_SCLKMPLL
192	#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \
193	\| (MMCC4_SEL << 16) \
194	\| (MMCC3_SEL << 12) \
195	\| (MMCC2_SEL << 8) \
196	\| (MMCC1_SEL << 4) \
197	\| (MMCC0_SEL << 0))
198
199	/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
200	/* CLK_DIV_FSYS1 */
201	#define MMC0_RATIO 0xF
202	#define MMC0_PRE_RATIO 0x0
203	#define MMC1_RATIO 0xF
204	#define MMC1_PRE_RATIO 0x0
205	#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \
206	\| (MMC1_RATIO << 16) \
207	\| (MMC0_PRE_RATIO << 8) \
208	\| (MMC0_RATIO << 0))
209
210	/* CLK_DIV_FSYS2 */
211	#define MMC2_RATIO 0xF
212	#define MMC2_PRE_RATIO 0x0
213	#define MMC3_RATIO 0xF
214	#define MMC3_PRE_RATIO 0x0
215	#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \
216	\| (MMC3_RATIO << 16) \
217	\| (MMC2_PRE_RATIO << 8) \
218	\| (MMC2_RATIO << 0))
219
220	/* CLK_DIV_FSYS3 */
221	#define MMC4_RATIO 0xF
222	#define MMC4_PRE_RATIO 0x0
223	#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \
224	\| (MMC4_RATIO << 0))
225
226	/* CLK_SRC_PERIL0 */
227	#define UART_SEL_XXTI 0
228	#define UART_SEL_XUSBXTI 1
229	#define UART_SEL_SCLK_HDMI24M 2
230	#define UART_SEL_SCLK_USBPHY0 3
231	#define UART_SEL_SCLK_USBPHY1 4
232	#define UART_SEL_SCLK_HDMIPHY 5
233	#define UART_SEL_SCLKMPLL 6
234	#define UART_SEL_SCLKEPLL 7
235	#define UART_SEL_SCLKVPLL 8
236
237	#define UART0_SEL UART_SEL_SCLKMPLL
238	#define UART1_SEL UART_SEL_SCLKMPLL
239	#define UART2_SEL UART_SEL_SCLKMPLL
240	#define UART3_SEL UART_SEL_SCLKMPLL
241	#define UART4_SEL UART_SEL_SCLKMPLL
242	#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \
243	\| (UART3_SEL << 12) \
244	\| (UART2_SEL << 8) \
245	\| (UART1_SEL << 4) \
246	\| (UART0_SEL << 0))
247
248	/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
249	/* CLK_DIV_PERIL0 */
250	#define UART0_RATIO 7
251	#define UART1_RATIO 7
252	#define UART2_RATIO 7
253	#define UART3_RATIO 7
254	#define UART4_RATIO 7
255	#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \
256	\| (UART3_RATIO << 12) \
257	\| (UART2_RATIO << 8) \
258	\| (UART1_RATIO << 4) \
259	\| (UART0_RATIO << 0))
260
522de019 AL	261	/* Clock Source CAM/FIMC */
	262	/* CLK_SRC_CAM */
	263	#define CAM0_SEL_XUSBXTI 1
	264	#define CAM1_SEL_XUSBXTI 1
	265	#define CSIS0_SEL_XUSBXTI 1
	266	#define CSIS1_SEL_XUSBXTI 1
	267
	268	#define FIMC_SEL_SCLKMPLL 6
	269	#define FIMC0_LCLK_SEL FIMC_SEL_SCLKMPLL
	270	#define FIMC1_LCLK_SEL FIMC_SEL_SCLKMPLL
	271	#define FIMC2_LCLK_SEL FIMC_SEL_SCLKMPLL
	272	#define FIMC3_LCLK_SEL FIMC_SEL_SCLKMPLL
	273
	274	#define CLK_SRC_CAM_VAL ((CSIS1_SEL_XUSBXTI << 28) \
	275	\| (CSIS0_SEL_XUSBXTI << 24) \
	276	\| (CAM1_SEL_XUSBXTI << 20) \
	277	\| (CAM0_SEL_XUSBXTI << 16) \
	278	\| (FIMC3_LCLK_SEL << 12) \
	279	\| (FIMC2_LCLK_SEL << 8) \
	280	\| (FIMC1_LCLK_SEL << 4) \
	281	\| (FIMC0_LCLK_SEL << 0))
	282
	283	/* SCLK CAM */
	284	/* CLK_DIV_CAM */
	285	#define FIMC0_LCLK_RATIO 4
	286	#define FIMC1_LCLK_RATIO 4
	287	#define FIMC2_LCLK_RATIO 4
	288	#define FIMC3_LCLK_RATIO 4
	289	#define CLK_DIV_CAM_VAL ((FIMC3_LCLK_RATIO << 12) \
	290	\| (FIMC2_LCLK_RATIO << 8) \
	291	\| (FIMC1_LCLK_RATIO << 4) \
	292	\| (FIMC0_LCLK_RATIO << 0))
	293
	294	/* SCLK MFC */
	295	/* CLK_SRC_MFC */
	296	#define MFC_SEL_MPLL 0
	297	#define MOUTMFC_0 0
	298	#define MFC_SEL MOUTMFC_0
	299	#define MFC_0_SEL MFC_SEL_MPLL
	300	#define CLK_SRC_MFC_VAL ((MFC_SEL << 8) \| (MFC_0_SEL))
	301
	302
	303	/* CLK_DIV_MFC */
	304	#define MFC_RATIO 3
	305	#define CLK_DIV_MFC_VAL (MFC_RATIO)
	306
	307	/* SCLK G3D */
	308	/* CLK_SRC_G3D */
	309	#define G3D_SEL_MPLL 0
	310	#define MOUTG3D_0 0
	311	#define G3D_SEL MOUTG3D_0
	312	#define G3D_0_SEL G3D_SEL_MPLL
	313	#define CLK_SRC_G3D_VAL ((G3D_SEL << 8) \| (G3D_0_SEL))
	314
	315	/* CLK_DIV_G3D */
	316	#define G3D_RATIO 1
	317	#define CLK_DIV_G3D_VAL (G3D_RATIO)
	318
	319	/* SCLK LCD0 */
7336278e CK	320	/* CLK_SRC_LCD0 */
	321	#define FIMD_SEL_SCLKMPLL 6
	322	#define MDNIE0_SEL_XUSBXTI 1
	323	#define MDNIE_PWM0_SEL_XUSBXTI 1
	324	#define MIPI0_SEL_XUSBXTI 1
	325	#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \
	326	\| (MDNIE_PWM0_SEL_XUSBXTI << 8) \
	327	\| (MDNIE0_SEL_XUSBXTI << 4) \
	328	\| (FIMD_SEL_SCLKMPLL << 0))
	329
522de019 AL	330	/* CLK_DIV_LCD0 */
	331	#define FIMD0_RATIO 4
	332	#define CLK_DIV_LCD0_VAL (FIMD0_RATIO)
	333
b9a1ef21 CK	334	/* Required period to generate a stable clock output */
	335	/* PLL_LOCK_TIME */
	336	#define PLL_LOCKTIME 0x1C20
	337
	338	/* PLL Values */
	339	#define DISABLE 0
	340	#define ENABLE 1
	341	#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\
	342	\| (mdiv << 16) \
	343	\| (pdiv << 8) \
	344	\| (sdiv << 0))
	345
	346	/* APLL_CON0 */
	347	#define APLL_MDIV 0xFA
	348	#define APLL_PDIV 0x6
	349	#define APLL_SDIV 0x1
	350	#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
	351
	352	/* APLL_CON1 */
	353	#define APLL_AFC_ENB 0x1
	354	#define APLL_AFC 0xC
	355	#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) \| (APLL_AFC << 0))
	356
	357	/* MPLL_CON0 */
	358	#define MPLL_MDIV 0xC8
	359	#define MPLL_PDIV 0x6
	360	#define MPLL_SDIV 0x1
	361	#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
	362
	363	/* MPLL_CON1 */
	364	#define MPLL_AFC_ENB 0x0
	365	#define MPLL_AFC 0x1C
	366	#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) \| (MPLL_AFC << 0))
	367
	368	/* EPLL_CON0 */
	369	#define EPLL_MDIV 0x30
	370	#define EPLL_PDIV 0x3
	371	#define EPLL_SDIV 0x2
	372	#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
	373
	374	/* EPLL_CON1 */
	375	#define EPLL_K 0x0
	376	#define EPLL_CON1_VAL (EPLL_K >> 0)
	377
	378	/* VPLL_CON0 */
	379	#define VPLL_MDIV 0x35
	380	#define VPLL_PDIV 0x3
	381	#define VPLL_SDIV 0x2
	382	#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
	383
	384	/* VPLL_CON1 */
	385	#define VPLL_SSCG_EN DISABLE
	386	#define VPLL_SEL_PF_DN_SPREAD 0x0
	387	#define VPLL_MRR 0x11
	388	#define VPLL_MFR 0x0
	389	#define VPLL_K 0x400
	390	#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\
	391	\| (VPLL_SEL_PF_DN_SPREAD << 29) \
	392	\| (VPLL_MRR << 24) \
	393	\| (VPLL_MFR << 16) \
	394	\| (VPLL_K << 0))
b9a1ef21	395
643be9c0 RS	396	/* DMC */
	397	#define DIRECT_CMD_NOP 0x07000000
	398	#define DIRECT_CMD_ZQ 0x0a000000
	399	#define DIRECT_CMD_CHIP1_SHIFT (1 << 20)
	400	#define MEM_TIMINGS_MSR_COUNT 4
	401	#define CTRL_START (1 << 0)
	402	#define CTRL_DLL_ON (1 << 1)
	403	#define AREF_EN (1 << 5)
	404	#define DRV_TYPE (1 << 6)
	405
	406	struct mem_timings {
	407	unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
	408	unsigned timingref;
	409	unsigned timingrow;
	410	unsigned timingdata;
	411	unsigned timingpower;
	412	unsigned zqcontrol;
	413	unsigned control0;
	414	unsigned control1;
	415	unsigned control2;
	416	unsigned concontrol;
	417	unsigned prechconfig;
	418	unsigned memcontrol;
	419	unsigned memconfig0;
	420	unsigned memconfig1;
	421	unsigned dll_resync;
	422	unsigned dll_on;
	423	};
	424
	425	/* MIU */
	426	/* MIU Config Register Offsets*/
	427	#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400
	428	#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
	429	#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
	430	#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
	431	#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810
	432	#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818
	433	#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820
	434	#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828
	435	#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830
	436
	437	#ifdef CONFIG_ORIGEN
	438	/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
	439	#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
	440	#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
	441	#endif
b9a1ef21	442
643be9c0 RS	443	#define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000
	444	#define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff
	445	#define INTERLEAVE_ADDR_MAP_EN 0x00000001
b9a1ef21	446
643be9c0 RS	447	#ifdef CONFIG_MIU_1BIT_INTERLEAVED
	448	/* Interleave_bit0: 0xC*/
	449	#define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c
	450	#endif
	451	#ifdef CONFIG_MIU_2BIT_INTERLEAVED
	452	/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
	453	#define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c
	454	#endif
	455	#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000
	456	#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff
	457	#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000
	458	#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff
	459	/* Enable SME0 and SME1*/
	460	#define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006
	461
	462	#define FORCE_DLL_RESYNC 3
	463	#define DLL_CONTROL_ON 1
	464
	465	#define DIRECT_CMD1 0x00020000
	466	#define DIRECT_CMD2 0x00030000
	467	#define DIRECT_CMD3 0x00010002
	468	#define DIRECT_CMD4 0x00000328
	469
	470	#define CTRL_ZQ_MODE_NOTERM (0x1 << 0)
	471	#define CTRL_ZQ_START (0x1 << 1)
	472	#define CTRL_ZQ_DIV (0 << 4)
	473	#define CTRL_ZQ_MODE_DDS (0x7 << 8)
	474	#define CTRL_ZQ_MODE_TERM (0x2 << 11)
	475	#define CTRL_ZQ_FORCE_IMPN (0x5 << 14)
	476	#define CTRL_ZQ_FORCE_IMPP (0x6 << 17)
	477	#define CTRL_DCC (0xE38 << 20)
	478	#define ZQ_CONTROL_VAL (CTRL_ZQ_MODE_NOTERM \| CTRL_ZQ_START\
	479	\| CTRL_ZQ_DIV \| CTRL_ZQ_MODE_DDS\
	480	\| CTRL_ZQ_MODE_TERM \| CTRL_ZQ_FORCE_IMPN\
	481	\| CTRL_ZQ_FORCE_IMPP \| CTRL_DCC)
	482
	483	#define ASYNC (0 << 0)
	484	#define CLK_RATIO (1 << 1)
	485	#define DIV_PIPE (1 << 3)
	486	#define AWR_ON (1 << 4)
	487	#define AREF_DISABLE (0 << 5)
	488	#define DRV_TYPE_DISABLE (0 << 6)
	489	#define CHIP0_NOT_EMPTY (0 << 8)
	490	#define CHIP1_NOT_EMPTY (0 << 9)
	491	#define DQ_SWAP_DISABLE (0 << 10)
	492	#define QOS_FAST_DISABLE (0 << 11)
	493	#define RD_FETCH (0x3 << 12)
	494	#define TIMEOUT_LEVEL0 (0xFFF << 16)
	495	#define CONCONTROL_VAL (ASYNC \| CLK_RATIO \| DIV_PIPE \| AWR_ON\
	496	\| AREF_DISABLE \| DRV_TYPE_DISABLE\
	497	\| CHIP0_NOT_EMPTY \| CHIP1_NOT_EMPTY\
	498	\| DQ_SWAP_DISABLE \| QOS_FAST_DISABLE\
	499	\| RD_FETCH \| TIMEOUT_LEVEL0)
	500
	501	#define CLK_STOP_DISABLE (0 << 1)
	502	#define DPWRDN_DISABLE (0 << 2)
	503	#define DPWRDN_TYPE (0 << 3)
	504	#define TP_DISABLE (0 << 4)
	505	#define DSREF_DIABLE (0 << 5)
	506	#define ADD_LAT_PALL (1 << 6)
	507	#define MEM_TYPE_DDR3 (0x6 << 8)
	508	#define MEM_WIDTH_32 (0x2 << 12)
	509	#define NUM_CHIP_2 (1 << 16)
	510	#define BL_8 (0x3 << 20)
511	#define MEMCONTROL_VAL (CLK_STOP_DISABLE \| DPWRDN_DISABLE\
512	\| DPWRDN_TYPE \| TP_DISABLE \| DSREF_DIABLE\
513	\| ADD_LAT_PALL \| MEM_TYPE_DDR3 \| MEM_WIDTH_32\
514	\| NUM_CHIP_2 \| BL_8)
515
516
517	#define CHIP_BANK_8 (0x3 << 0)
518	#define CHIP_ROW_14 (0x2 << 4)
519	#define CHIP_COL_10 (0x3 << 8)
520	#define CHIP_MAP_INTERLEAVED (1 << 12)
521	#define CHIP_MASK (0xe0 << 16)
522	#ifdef CONFIG_MIU_LINEAR
523	#define CHIP0_BASE (0x40 << 24)
524	#define CHIP1_BASE (0x60 << 24)
525	#else
526	#define CHIP0_BASE (0x20 << 24)
527	#define CHIP1_BASE (0x40 << 24)
528	#endif
529	#define MEMCONFIG0_VAL (CHIP_BANK_8 \| CHIP_ROW_14 \| CHIP_COL_10\
530	\| CHIP_MAP_INTERLEAVED \| CHIP_MASK \| CHIP0_BASE)
531	#define MEMCONFIG1_VAL (CHIP_BANK_8 \| CHIP_ROW_14 \| CHIP_COL_10\
532	\| CHIP_MAP_INTERLEAVED \| CHIP_MASK \| CHIP1_BASE)
533
534	#define TP_CNT (0xff << 24)
535	#define PRECHCONFIG TP_CNT
536
537	#define CTRL_OFF (0 << 0)
538	#define CTRL_DLL_OFF (0 << 1)
539	#define CTRL_HALF (0 << 2)
540	#define CTRL_DFDQS (1 << 3)
541	#define DQS_DELAY (0 << 4)
542	#define CTRL_START_POINT (0x10 << 8)
543	#define CTRL_INC (0x10 << 16)
544	#define CTRL_FORCE (0x71 << 24)
545	#define CONTROL0_VAL (CTRL_OFF \| CTRL_DLL_OFF \| CTRL_HALF\
546	\| CTRL_DFDQS \| DQS_DELAY \| CTRL_START_POINT\
547	\| CTRL_INC \| CTRL_FORCE)
548
549	#define CTRL_SHIFTC (0x6 << 0)
550	#define CTRL_REF (8 << 4)
551	#define CTRL_SHGATE (1 << 29)
552	#define TERM_READ_EN (1 << 30)
553	#define TERM_WRITE_EN (1 << 31)
554	#define CONTROL1_VAL (CTRL_SHIFTC \| CTRL_REF \| CTRL_SHGATE\
555	\| TERM_READ_EN \| TERM_WRITE_EN)
556
557	#define CONTROL2_VAL 0x00000000
558
559	#ifdef CONFIG_ORIGEN
560	#define TIMINGREF_VAL 0x000000BB
561	#define TIMINGROW_VAL 0x4046654f
562	#define TIMINGDATA_VAL 0x46400506
563	#define TIMINGPOWER_VAL 0x52000A3C
564	#else
565	#define TIMINGREF_VAL 0x000000BC
566	#ifdef DRAM_CLK_330
567	#define TIMINGROW_VAL 0x3545548d
568	#define TIMINGDATA_VAL 0x45430506
569	#define TIMINGPOWER_VAL 0x4439033c
570	#endif
571	#ifdef DRAM_CLK_400
572	#define TIMINGROW_VAL 0x45430506
573	#define TIMINGDATA_VAL 0x56500506
574	#define TIMINGPOWER_VAL 0x5444033d
575	#endif
576	#endif
b9a1ef21	577	#endif