[thirdparty/u-boot.git] / arch / arm / mach-imx / imx8 / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018, 2021 NXP
 */

#include <common.h>
#include <clk.h>
#include <cpu.h>
#include <cpu_func.h>
#include <dm.h>
#include <event.h>
#include <init.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/uclass.h>
#include <errno.h>
#include <spl.h>
#include <thermal.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-imx/cpu.h>
#include <asm/armv8/cpu.h>
#include <asm/armv8/mmu.h>
#include <asm/setup.h>
#include <asm/mach-imx/boot_mode.h>
#include <spl.h>

DECLARE_GLOBAL_DATA_PTR;

#define BT_PASSOVER_TAG	0x504F
struct pass_over_info_t *get_pass_over_info(void)
{
	struct pass_over_info_t *p =
		(struct pass_over_info_t *)PASS_OVER_INFO_ADDR;

	if (p->barker != BT_PASSOVER_TAG ||
	    p->len != sizeof(struct pass_over_info_t))
		return NULL;

	return p;
}

int arch_cpu_init(void)
{
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
	spl_save_restore_data();
#endif

#ifdef CONFIG_SPL_BUILD
	struct pass_over_info_t *pass_over;

	if (is_soc_rev(CHIP_REV_A)) {
		pass_over = get_pass_over_info();
		if (pass_over && pass_over->g_ap_mu == 0) {
			/*
			 * When ap_mu is 0, means the U-Boot booted
			 * from first container
			 */
			sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
		}
	}
#endif

	return 0;
}

static int imx8_init_mu(void *ctx, struct event *event)
{
	struct udevice *devp;
	int node, ret;

	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");

	ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
	if (ret) {
		printf("could not get scu %d\n", ret);
		return ret;
	}

	if (is_imx8qm()) {
		ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
						    SC_PM_PW_MODE_ON);
		if (ret)
			return ret;
	}

	return 0;
}
EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu);

#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
		struct udevice *dev;
		int ret;

		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
		if (ret)
			printf("Failed to initialize caam_jr: %d\n", ret);
	}

	return 0;
}
#endif

int print_bootinfo(void)
{
	enum boot_device bt_dev = get_boot_device();

	puts("Boot:  ");
	switch (bt_dev) {
	case SD1_BOOT:
		puts("SD0\n");
		break;
	case SD2_BOOT:
		puts("SD1\n");
		break;
	case SD3_BOOT:
		puts("SD2\n");
		break;
	case MMC1_BOOT:
		puts("MMC0\n");
		break;
	case MMC2_BOOT:
		puts("MMC1\n");
		break;
	case MMC3_BOOT:
		puts("MMC2\n");
		break;
	case FLEXSPI_BOOT:
		puts("FLEXSPI\n");
		break;
	case SATA_BOOT:
		puts("SATA\n");
		break;
	case NAND_BOOT:
		puts("NAND\n");
		break;
	case USB_BOOT:
		puts("USB\n");
		break;
	default:
		printf("Unknown device %u\n", bt_dev);
		break;
	}

	return 0;
}

enum boot_device get_boot_device(void)
{
	enum boot_device boot_dev = SD1_BOOT;

	sc_rsrc_t dev_rsrc;

	sc_misc_get_boot_dev(-1, &dev_rsrc);

	switch (dev_rsrc) {
	case SC_R_SDHC_0:
		boot_dev = MMC1_BOOT;
		break;
	case SC_R_SDHC_1:
		boot_dev = SD2_BOOT;
		break;
	case SC_R_SDHC_2:
		boot_dev = SD3_BOOT;
		break;
	case SC_R_NAND:
		boot_dev = NAND_BOOT;
		break;
	case SC_R_FSPI_0:
		boot_dev = FLEXSPI_BOOT;
		break;
	case SC_R_SATA_0:
		boot_dev = SATA_BOOT;
		break;
	case SC_R_USB_0:
	case SC_R_USB_1:
	case SC_R_USB_2:
		boot_dev = USB_BOOT;
		break;
	default:
		break;
	}

	return boot_dev;
}

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define FUSE_UNIQUE_ID_WORD0 16
#define FUSE_UNIQUE_ID_WORD1 17
void get_board_serial(struct tag_serialnr *serialnr)
{
	sc_err_t err;
	u32 val1 = 0, val2 = 0;
	u32 word1, word2;

	if (!serialnr)
		return;

	word1 = FUSE_UNIQUE_ID_WORD0;
	word2 = FUSE_UNIQUE_ID_WORD1;

	err = sc_misc_otp_fuse_read(-1, word1, &val1);
	if (err != SC_ERR_NONE) {
		printf("%s fuse %d read error: %d\n", __func__, word1, err);
		return;
	}

	err = sc_misc_otp_fuse_read(-1, word2, &val2);
	if (err != SC_ERR_NONE) {
		printf("%s fuse %d read error: %d\n", __func__, word2, err);
		return;
	}
	serialnr->low = val1;
	serialnr->high = val2;
}
#endif /*CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG*/

#ifdef CONFIG_ENV_IS_IN_MMC
__weak int board_mmc_get_env_dev(int devno)
{
	return CONFIG_SYS_MMC_ENV_DEV;
}

int mmc_get_env_dev(void)
{
	sc_rsrc_t dev_rsrc;
	int devno;

	sc_misc_get_boot_dev(-1, &dev_rsrc);

	switch (dev_rsrc) {
	case SC_R_SDHC_0:
		devno = 0;
		break;
	case SC_R_SDHC_1:
		devno = 1;
		break;
	case SC_R_SDHC_2:
		devno = 2;
		break;
	default:
		/* If not boot from sd/mmc, use default value */
		return CONFIG_SYS_MMC_ENV_DEV;
	}

	return board_mmc_get_env_dev(devno);
}
#endif

#define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */

static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
			    sc_faddr_t *addr_end)
{
	sc_faddr_t start, end;
	int ret;
	bool owned;

	owned = sc_rm_is_memreg_owned(-1, mr);
	if (owned) {
		ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
		if (ret) {
			printf("Memreg get info failed, %d\n", ret);
			return -EINVAL;
		}
		debug("0x%llx -- 0x%llx\n", start, end);
		*addr_start = start;
		*addr_end = end;

		return 0;
	}

	return -EINVAL;
}

__weak void board_mem_get_layout(u64 *phys_sdram_1_start,
				 u64 *phys_sdram_1_size,
				 u64 *phys_sdram_2_start,
				 u64 *phys_sdram_2_size)
{
	*phys_sdram_1_start = PHYS_SDRAM_1;
	*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
	*phys_sdram_2_start = PHYS_SDRAM_2;
	*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
}

phys_size_t get_effective_memsize(void)
{
	sc_rm_mr_t mr;
	sc_faddr_t start, end, end1, start_aligned;
	u64 phys_sdram_1_start, phys_sdram_1_size;
	u64 phys_sdram_2_start, phys_sdram_2_size;
	int err;

	board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
			     &phys_sdram_2_start, &phys_sdram_2_size);


	end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
	for (mr = 0; mr < 64; mr++) {
		err = get_owned_memreg(mr, &start, &end);
		if (!err) {
			start_aligned = roundup(start, MEMSTART_ALIGNMENT);
			/* Too small memory region, not use it */
			if (start_aligned > end)
				continue;

			/* Find the memory region runs the U-Boot */
			if (start >= phys_sdram_1_start && start <= end1 &&
			    (start <= CONFIG_TEXT_BASE &&
			    end >= CONFIG_TEXT_BASE)) {
				if ((end + 1) <=
				    ((sc_faddr_t)phys_sdram_1_start +
				    phys_sdram_1_size))
					return (end - phys_sdram_1_start + 1);
				else
					return phys_sdram_1_size;
			}
		}
	}

	return phys_sdram_1_size;
}

int dram_init(void)
{
	sc_rm_mr_t mr;
	sc_faddr_t start, end, end1, end2;
	u64 phys_sdram_1_start, phys_sdram_1_size;
	u64 phys_sdram_2_start, phys_sdram_2_size;
	int err;

	board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
			     &phys_sdram_2_start, &phys_sdram_2_size);

	end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
	end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
	for (mr = 0; mr < 64; mr++) {
		err = get_owned_memreg(mr, &start, &end);
		if (!err) {
			start = roundup(start, MEMSTART_ALIGNMENT);
			/* Too small memory region, not use it */
			if (start > end)
				continue;

			if (start >= phys_sdram_1_start && start <= end1) {
				if ((end + 1) <= end1)
					gd->ram_size += end - start + 1;
				else
					gd->ram_size += end1 - start;
			} else if (start >= phys_sdram_2_start &&
				   start <= end2) {
				if ((end + 1) <= end2)
					gd->ram_size += end - start + 1;
				else
					gd->ram_size += end2 - start;
			}
		}
	}

	/* If error, set to the default value */
	if (!gd->ram_size) {
		gd->ram_size = phys_sdram_1_size;
		gd->ram_size += phys_sdram_2_size;
	}
	return 0;
}

static void dram_bank_sort(int current_bank)
{
	phys_addr_t start;
	phys_size_t size;

	while (current_bank > 0) {
		if (gd->bd->bi_dram[current_bank - 1].start >
		    gd->bd->bi_dram[current_bank].start) {
			start = gd->bd->bi_dram[current_bank - 1].start;
			size = gd->bd->bi_dram[current_bank - 1].size;

			gd->bd->bi_dram[current_bank - 1].start =
				gd->bd->bi_dram[current_bank].start;
			gd->bd->bi_dram[current_bank - 1].size =
				gd->bd->bi_dram[current_bank].size;

			gd->bd->bi_dram[current_bank].start = start;
			gd->bd->bi_dram[current_bank].size = size;
		}
		current_bank--;
	}
}

int dram_init_banksize(void)
{
	sc_rm_mr_t mr;
	sc_faddr_t start, end, end1, end2;
	int i = 0;
	u64 phys_sdram_1_start, phys_sdram_1_size;
	u64 phys_sdram_2_start, phys_sdram_2_size;
	int err;

	board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
			     &phys_sdram_2_start, &phys_sdram_2_size);

	end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
	end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
	for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
		err = get_owned_memreg(mr, &start, &end);
		if (!err) {
			start = roundup(start, MEMSTART_ALIGNMENT);
			if (start > end) /* Small memory region, no use it */
				continue;

			if (start >= phys_sdram_1_start && start <= end1) {
				gd->bd->bi_dram[i].start = start;

				if ((end + 1) <= end1)
					gd->bd->bi_dram[i].size =
						end - start + 1;
				else
					gd->bd->bi_dram[i].size = end1 - start;

				dram_bank_sort(i);
				i++;
			} else if (start >= phys_sdram_2_start && start <= end2) {
				gd->bd->bi_dram[i].start = start;

				if ((end + 1) <= end2)
					gd->bd->bi_dram[i].size =
						end - start + 1;
				else
					gd->bd->bi_dram[i].size = end2 - start;

				dram_bank_sort(i);
				i++;
			}
		}
	}

	/* If error, set to the default value */
	if (!i) {
		gd->bd->bi_dram[0].start = phys_sdram_1_start;
		gd->bd->bi_dram[0].size = phys_sdram_1_size;
		gd->bd->bi_dram[1].start = phys_sdram_2_start;
		gd->bd->bi_dram[1].size = phys_sdram_2_size;
	}

	return 0;
}

static u64 get_block_attrs(sc_faddr_t addr_start)
{
	u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
		PTE_BLOCK_PXN | PTE_BLOCK_UXN;
	u64 phys_sdram_1_start, phys_sdram_1_size;
	u64 phys_sdram_2_start, phys_sdram_2_size;

	board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
			     &phys_sdram_2_start, &phys_sdram_2_size);

	if ((addr_start >= phys_sdram_1_start &&
	     addr_start <= ((sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size)) ||
	    (addr_start >= phys_sdram_2_start &&
	     addr_start <= ((sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size)))
		return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);

	return attr;
}

static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
{
	sc_faddr_t end1, end2;
	u64 phys_sdram_1_start, phys_sdram_1_size;
	u64 phys_sdram_2_start, phys_sdram_2_size;

	board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
			     &phys_sdram_2_start, &phys_sdram_2_size);


	end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
	end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;

	if (addr_start >= phys_sdram_1_start && addr_start <= end1) {
		if ((addr_end + 1) > end1)
			return end1 - addr_start;
	} else if (addr_start >= phys_sdram_2_start && addr_start <= end2) {
		if ((addr_end + 1) > end2)
			return end2 - addr_start;
	}

	return (addr_end - addr_start + 1);
}

#define MAX_PTE_ENTRIES 512
#define MAX_MEM_MAP_REGIONS 16

static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
struct mm_region *mem_map = imx8_mem_map;

void enable_caches(void)
{
	sc_rm_mr_t mr;
	sc_faddr_t start, end;
	int err, i;

	/* Create map for registers access from 0x1c000000 to 0x80000000*/
	imx8_mem_map[0].virt = 0x1c000000UL;
	imx8_mem_map[0].phys = 0x1c000000UL;
	imx8_mem_map[0].size = 0x64000000UL;
	imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;

	i = 1;
	for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
		err = get_owned_memreg(mr, &start, &end);
		if (!err) {
			imx8_mem_map[i].virt = start;
			imx8_mem_map[i].phys = start;
			imx8_mem_map[i].size = get_block_size(start, end);
			imx8_mem_map[i].attrs = get_block_attrs(start);
			i++;
		}
	}

	if (i < MAX_MEM_MAP_REGIONS) {
		imx8_mem_map[i].size = 0;
		imx8_mem_map[i].attrs = 0;
	} else {
		puts("Error, need more MEM MAP REGIONS reserved\n");
		icache_enable();
		return;
	}

	for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
		debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
		      i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
		      imx8_mem_map[i].size, imx8_mem_map[i].attrs);
	}

	icache_enable();
	dcache_enable();
}

#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
u64 get_page_table_size(void)
{
	u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
	u64 size = 0;

	/*
	 * For each memory region, the max table size:
	 * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
	 */
	size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;

	/*
	 * We need to duplicate our page table once to have an emergency pt to
	 * resort to when splitting page tables later on
	 */
	size *= 2;

	/*
	 * We may need to split page tables later on if dcache settings change,
	 * so reserve up to 4 (random pick) page tables for that.
	 */
	size += one_pt * 4;

	return size;
}
#endif

#if defined(CONFIG_IMX8QM)
#define FUSE_MAC0_WORD0 452
#define FUSE_MAC0_WORD1 453
#define FUSE_MAC1_WORD0 454
#define FUSE_MAC1_WORD1 455
#elif defined(CONFIG_IMX8QXP)
#define FUSE_MAC0_WORD0 708
#define FUSE_MAC0_WORD1 709
#define FUSE_MAC1_WORD0 710
#define FUSE_MAC1_WORD1 711
#endif

void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	u32 word[2], val[2] = {};
	int i, ret;

	if (dev_id == 0) {
		word[0] = FUSE_MAC0_WORD0;
		word[1] = FUSE_MAC0_WORD1;
	} else {
		word[0] = FUSE_MAC1_WORD0;
		word[1] = FUSE_MAC1_WORD1;
	}

	for (i = 0; i < 2; i++) {
		ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
		if (ret < 0)
			goto err;
	}

	mac[0] = val[0];
	mac[1] = val[0] >> 8;
	mac[2] = val[0] >> 16;
	mac[3] = val[0] >> 24;
	mac[4] = val[1];
	mac[5] = val[1] >> 8;

	debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
	      __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
	return;
err:
	printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
}

u32 get_cpu_rev(void)
{
	u32 id = 0, rev = 0;
	int ret;

	ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
	if (ret)
		return 0;

	rev = (id >> 5)  & 0xf;
	id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */

	return (id << 12) | rev;
}

void board_boot_order(u32 *spl_boot_list)
{
	spl_boot_list[0] = spl_boot_device();

	if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
		/* Check whether we own the flexspi0, if not, use NOR boot */
		if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0))
			spl_boot_list[0] = BOOT_DEVICE_NOR;
	}
}

bool m4_parts_booted(void)
{
	sc_rm_pt_t m4_parts[2];
	int err;

	err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]);
	if (err) {
		printf("%s get resource [%d] owner error: %d\n", __func__,
		       SC_R_M4_0_PID0, err);
		return false;
	}

	if (sc_pm_is_partition_started(-1, m4_parts[0]))
		return true;

	if (is_imx8qm()) {
		err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]);
		if (err) {
			printf("%s get resource [%d] owner error: %d\n",
			       __func__, SC_R_M4_1_PID0, err);
			return false;
		}

		if (sc_pm_is_partition_started(-1, m4_parts[1]))
			return true;
	}

	return false;
}
Commit	Line	Data
60d33fcd PF	1	// SPDX-License-Identifier: GPL-2.0+
60d33fcd PF	2	/*
cb5d0419	3	* Copyright 2018, 2021 NXP
60d33fcd PF	4	*/
	5
	6	#include <common.h>
	7	#include <clk.h>
2fdb1a1d	8	#include <cpu.h>
9edefc27	9	#include <cpu_func.h>
60d33fcd	10	#include <dm.h>
7fe32b34	11	#include <event.h>
9b4a205f	12	#include <init.h>
f7ae49fc	13	#include <log.h>
90526e9f	14	#include <asm/cache.h>
401d1c4f	15	#include <asm/global_data.h>
60d33fcd PF	16	#include <dm/device-internal.h>
	17	#include <dm/lists.h>
	18	#include <dm/uclass.h>
	19	#include <errno.h>
6aead233	20	#include <spl.h>
1796e509	21	#include <thermal.h>
60d33fcd	22	#include <asm/arch/sci/sci.h>
8aa1505b	23	#include <asm/arch/sys_proto.h>
60d33fcd PF	24	#include <asm/arch-imx/cpu.h>
60d33fcd PF	25	#include <asm/armv8/cpu.h>
930b5952	26	#include <asm/armv8/mmu.h>
81037672	27	#include <asm/setup.h>
8aa1505b	28	#include <asm/mach-imx/boot_mode.h>
42b26ddc	29	#include <spl.h>
60d33fcd PF	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
1ef20a3d PF	33	#define BT_PASSOVER_TAG 0x504F
	34	struct pass_over_info_t *get_pass_over_info(void)
	35	{
	36	struct pass_over_info_t *p =
	37	(struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
	38
	39	if (p->barker != BT_PASSOVER_TAG \|\|
	40	p->len != sizeof(struct pass_over_info_t))
	41	return NULL;
	42
	43	return p;
	44	}
	45
	46	int arch_cpu_init(void)
	47	{
6aead233 PF	48	#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
	49	spl_save_restore_data();
	50	#endif
	51
9382f73b PF	52	#ifdef CONFIG_SPL_BUILD
	53	struct pass_over_info_t *pass_over;
	54
	55	if (is_soc_rev(CHIP_REV_A)) {
	56	pass_over = get_pass_over_info();
	57	if (pass_over && pass_over->g_ap_mu == 0) {
	58	/*
	59	* When ap_mu is 0, means the U-Boot booted
	60	* from first container
	61	*/
	62	sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
	63	}
1ef20a3d	64	}
9382f73b	65	#endif
1ef20a3d PF	66
	67	return 0;
	68	}
	69
7fe32b34	70	static int imx8_init_mu(void ctx, struct event event)
1ef20a3d PF	71	{
	72	struct udevice *devp;
	73	int node, ret;
	74
	75	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
1ef20a3d	76
bcf94abd	77	ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
1ef20a3d	78	if (ret) {
bcf94abd	79	printf("could not get scu %d\n", ret);
1ef20a3d PF	80	return ret;
	81	}
	82
8f99438b PF	83	if (is_imx8qm()) {
	84	ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
	85	SC_PM_PW_MODE_ON);
	86	if (ret)
	87	return ret;
	88	}
	89
1ef20a3d PF	90	return 0;
1ef20a3d PF	91	}
7fe32b34	92	EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu);
1ef20a3d	93
cb5d0419 GJ	94	#if defined(CONFIG_ARCH_MISC_INIT)
	95	int arch_misc_init(void)
	96	{
	97	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
	98	struct udevice *dev;
	99	int ret;
	100
	101	ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
	102	if (ret)
cda8f873	103	printf("Failed to initialize caam_jr: %d\n", ret);
cb5d0419 GJ	104	}
	105
	106	return 0;
	107	}
	108	#endif
	109
8aa1505b PF	110	int print_bootinfo(void)
	111	{
	112	enum boot_device bt_dev = get_boot_device();
	113
	114	puts("Boot: ");
	115	switch (bt_dev) {
	116	case SD1_BOOT:
	117	puts("SD0\n");
	118	break;
	119	case SD2_BOOT:
	120	puts("SD1\n");
	121	break;
	122	case SD3_BOOT:
	123	puts("SD2\n");
	124	break;
	125	case MMC1_BOOT:
	126	puts("MMC0\n");
	127	break;
	128	case MMC2_BOOT:
	129	puts("MMC1\n");
	130	break;
	131	case MMC3_BOOT:
	132	puts("MMC2\n");
	133	break;
	134	case FLEXSPI_BOOT:
	135	puts("FLEXSPI\n");
	136	break;
	137	case SATA_BOOT:
	138	puts("SATA\n");
	139	break;
	140	case NAND_BOOT:
	141	puts("NAND\n");
	142	break;
	143	case USB_BOOT:
	144	puts("USB\n");
	145	break;
	146	default:
	147	printf("Unknown device %u\n", bt_dev);
	148	break;
	149	}
	150
	151	return 0;
	152	}
	153
	154	enum boot_device get_boot_device(void)
	155	{
	156	enum boot_device boot_dev = SD1_BOOT;
	157
	158	sc_rsrc_t dev_rsrc;
	159
	160	sc_misc_get_boot_dev(-1, &dev_rsrc);
	161
	162	switch (dev_rsrc) {
	163	case SC_R_SDHC_0:
	164	boot_dev = MMC1_BOOT;
	165	break;
	166	case SC_R_SDHC_1:
	167	boot_dev = SD2_BOOT;
	168	break;
	169	case SC_R_SDHC_2:
	170	boot_dev = SD3_BOOT;
	171	break;
	172	case SC_R_NAND:
	173	boot_dev = NAND_BOOT;
174	break;
175	case SC_R_FSPI_0:
176	boot_dev = FLEXSPI_BOOT;
177	break;
178	case SC_R_SATA_0:
179	boot_dev = SATA_BOOT;
180	break;
181	case SC_R_USB_0:
182	case SC_R_USB_1:
183	case SC_R_USB_2:
184	boot_dev = USB_BOOT;
185	break;
186	default:
187	break;
188	}
189
190	return boot_dev;
191	}
c1aae21d	192
b9d66a06	193	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
81037672 PF	194	#define FUSE_UNIQUE_ID_WORD0 16
	195	#define FUSE_UNIQUE_ID_WORD1 17
	196	void get_board_serial(struct tag_serialnr *serialnr)
	197	{
	198	sc_err_t err;
	199	u32 val1 = 0, val2 = 0;
	200	u32 word1, word2;
	201
	202	if (!serialnr)
	203	return;
	204
	205	word1 = FUSE_UNIQUE_ID_WORD0;
	206	word2 = FUSE_UNIQUE_ID_WORD1;
	207
	208	err = sc_misc_otp_fuse_read(-1, word1, &val1);
	209	if (err != SC_ERR_NONE) {
	210	printf("%s fuse %d read error: %d\n", __func__, word1, err);
	211	return;
	212	}
	213
	214	err = sc_misc_otp_fuse_read(-1, word2, &val2);
	215	if (err != SC_ERR_NONE) {
	216	printf("%s fuse %d read error: %d\n", __func__, word2, err);
	217	return;
	218	}
	219	serialnr->low = val1;
	220	serialnr->high = val2;
	221	}
b9d66a06	222	#endif /CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG/
81037672	223
c1aae21d PF	224	#ifdef CONFIG_ENV_IS_IN_MMC
	225	__weak int board_mmc_get_env_dev(int devno)
	226	{
	227	return CONFIG_SYS_MMC_ENV_DEV;
	228	}
	229
	230	int mmc_get_env_dev(void)
	231	{
	232	sc_rsrc_t dev_rsrc;
	233	int devno;
	234
	235	sc_misc_get_boot_dev(-1, &dev_rsrc);
	236
	237	switch (dev_rsrc) {
	238	case SC_R_SDHC_0:
	239	devno = 0;
	240	break;
	241	case SC_R_SDHC_1:
	242	devno = 1;
	243	break;
	244	case SC_R_SDHC_2:
	245	devno = 2;
	246	break;
	247	default:
	248	/* If not boot from sd/mmc, use default value */
	249	return CONFIG_SYS_MMC_ENV_DEV;
	250	}
	251
	252	return board_mmc_get_env_dev(devno);
	253	}
	254	#endif
930b5952 PF	255
	256	#define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
	257
	258	static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
	259	sc_faddr_t *addr_end)
	260	{
	261	sc_faddr_t start, end;
	262	int ret;
	263	bool owned;
	264
	265	owned = sc_rm_is_memreg_owned(-1, mr);
	266	if (owned) {
	267	ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
	268	if (ret) {
	269	printf("Memreg get info failed, %d\n", ret);
	270	return -EINVAL;
	271	}
	272	debug("0x%llx -- 0x%llx\n", start, end);
	273	*addr_start = start;
	274	*addr_end = end;
	275
	276	return 0;
	277	}
	278
	279	return -EINVAL;
	280	}
	281
2f36a693 MZ	282	__weak void board_mem_get_layout(u64 *phys_sdram_1_start,
	283	u64 *phys_sdram_1_size,
	284	u64 *phys_sdram_2_start,
	285	u64 *phys_sdram_2_size)
	286	{
	287	*phys_sdram_1_start = PHYS_SDRAM_1;
	288	*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
	289	*phys_sdram_2_start = PHYS_SDRAM_2;
	290	*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
	291	}
	292
930b5952 PF	293	phys_size_t get_effective_memsize(void)
	294	{
	295	sc_rm_mr_t mr;
7c351ff5	296	sc_faddr_t start, end, end1, start_aligned;
2f36a693 MZ	297	u64 phys_sdram_1_start, phys_sdram_1_size;
2f36a693 MZ	298	u64 phys_sdram_2_start, phys_sdram_2_size;
930b5952 PF	299	int err;
930b5952 PF	300
2f36a693 MZ	301	board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
	302	&phys_sdram_2_start, &phys_sdram_2_size);
	303
930b5952	304
2f36a693	305	end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
930b5952 PF	306	for (mr = 0; mr < 64; mr++) {
	307	err = get_owned_memreg(mr, &start, &end);
	308	if (!err) {
7c351ff5	309	start_aligned = roundup(start, MEMSTART_ALIGNMENT);
930b5952	310	/* Too small memory region, not use it */
7c351ff5	311	if (start_aligned > end)
930b5952 PF	312	continue;
930b5952 PF	313
1ef20a3d	314	/* Find the memory region runs the U-Boot */
2f36a693	315	if (start >= phys_sdram_1_start && start <= end1 &&
98463903 SG	316	(start <= CONFIG_TEXT_BASE &&
98463903 SG	317	end >= CONFIG_TEXT_BASE)) {
2f36a693 MZ	318	if ((end + 1) <=
	319	((sc_faddr_t)phys_sdram_1_start +
	320	phys_sdram_1_size))
	321	return (end - phys_sdram_1_start + 1);
930b5952	322	else
2f36a693	323	return phys_sdram_1_size;
930b5952 PF	324	}
	325	}
	326	}
	327
2f36a693	328	return phys_sdram_1_size;
930b5952 PF	329	}
	330
	331	int dram_init(void)
	332	{
	333	sc_rm_mr_t mr;
	334	sc_faddr_t start, end, end1, end2;
2f36a693 MZ	335	u64 phys_sdram_1_start, phys_sdram_1_size;
2f36a693 MZ	336	u64 phys_sdram_2_start, phys_sdram_2_size;
930b5952 PF	337	int err;
930b5952 PF	338
2f36a693 MZ	339	board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
	340	&phys_sdram_2_start, &phys_sdram_2_size);
	341
	342	end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
	343	end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
930b5952 PF	344	for (mr = 0; mr < 64; mr++) {
	345	err = get_owned_memreg(mr, &start, &end);
	346	if (!err) {
	347	start = roundup(start, MEMSTART_ALIGNMENT);
	348	/* Too small memory region, not use it */
	349	if (start > end)
	350	continue;
	351
2f36a693	352	if (start >= phys_sdram_1_start && start <= end1) {
930b5952 PF	353	if ((end + 1) <= end1)
	354	gd->ram_size += end - start + 1;
	355	else
	356	gd->ram_size += end1 - start;
2f36a693 MZ	357	} else if (start >= phys_sdram_2_start &&
2f36a693 MZ	358	start <= end2) {
930b5952 PF	359	if ((end + 1) <= end2)
	360	gd->ram_size += end - start + 1;
	361	else
	362	gd->ram_size += end2 - start;
	363	}
	364	}
	365	}
	366
	367	/* If error, set to the default value */
	368	if (!gd->ram_size) {
2f36a693 MZ	369	gd->ram_size = phys_sdram_1_size;
2f36a693 MZ	370	gd->ram_size += phys_sdram_2_size;
930b5952 PF	371	}
	372	return 0;
	373	}
	374
	375	static void dram_bank_sort(int current_bank)
	376	{
	377	phys_addr_t start;
	378	phys_size_t size;
	379
	380	while (current_bank > 0) {
	381	if (gd->bd->bi_dram[current_bank - 1].start >
	382	gd->bd->bi_dram[current_bank].start) {
	383	start = gd->bd->bi_dram[current_bank - 1].start;
	384	size = gd->bd->bi_dram[current_bank - 1].size;
	385
	386	gd->bd->bi_dram[current_bank - 1].start =
	387	gd->bd->bi_dram[current_bank].start;
	388	gd->bd->bi_dram[current_bank - 1].size =
	389	gd->bd->bi_dram[current_bank].size;
	390
	391	gd->bd->bi_dram[current_bank].start = start;
	392	gd->bd->bi_dram[current_bank].size = size;
	393	}
	394	current_bank--;
	395	}
	396	}
	397
	398	int dram_init_banksize(void)
	399	{
	400	sc_rm_mr_t mr;
	401	sc_faddr_t start, end, end1, end2;
	402	int i = 0;
2f36a693 MZ	403	u64 phys_sdram_1_start, phys_sdram_1_size;
2f36a693 MZ	404	u64 phys_sdram_2_start, phys_sdram_2_size;
930b5952 PF	405	int err;
930b5952 PF	406
2f36a693 MZ	407	board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
2f36a693 MZ	408	&phys_sdram_2_start, &phys_sdram_2_size);
930b5952	409
2f36a693 MZ	410	end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
2f36a693 MZ	411	end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
930b5952 PF	412	for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
	413	err = get_owned_memreg(mr, &start, &end);
	414	if (!err) {
	415	start = roundup(start, MEMSTART_ALIGNMENT);
	416	if (start > end) /* Small memory region, no use it */
	417	continue;
	418
2f36a693	419	if (start >= phys_sdram_1_start && start <= end1) {
930b5952 PF	420	gd->bd->bi_dram[i].start = start;
	421
	422	if ((end + 1) <= end1)
	423	gd->bd->bi_dram[i].size =
	424	end - start + 1;
	425	else
	426	gd->bd->bi_dram[i].size = end1 - start;
	427
	428	dram_bank_sort(i);
	429	i++;
2f36a693	430	} else if (start >= phys_sdram_2_start && start <= end2) {
930b5952 PF	431	gd->bd->bi_dram[i].start = start;
	432
	433	if ((end + 1) <= end2)
	434	gd->bd->bi_dram[i].size =
	435	end - start + 1;
	436	else
	437	gd->bd->bi_dram[i].size = end2 - start;
	438
	439	dram_bank_sort(i);
	440	i++;
	441	}
	442	}
	443	}
	444
	445	/* If error, set to the default value */
	446	if (!i) {
2f36a693 MZ	447	gd->bd->bi_dram[0].start = phys_sdram_1_start;
	448	gd->bd->bi_dram[0].size = phys_sdram_1_size;
	449	gd->bd->bi_dram[1].start = phys_sdram_2_start;
	450	gd->bd->bi_dram[1].size = phys_sdram_2_size;
930b5952 PF	451	}
	452
	453	return 0;
	454	}
	455
	456	static u64 get_block_attrs(sc_faddr_t addr_start)
	457	{
	458	u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \| PTE_BLOCK_NON_SHARE \|
	459	PTE_BLOCK_PXN \| PTE_BLOCK_UXN;
2f36a693 MZ	460	u64 phys_sdram_1_start, phys_sdram_1_size;
	461	u64 phys_sdram_2_start, phys_sdram_2_size;
	462
	463	board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
	464	&phys_sdram_2_start, &phys_sdram_2_size);
930b5952	465
2f36a693 MZ	466	if ((addr_start >= phys_sdram_1_start &&
	467	addr_start <= ((sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size)) \|\|
	468	(addr_start >= phys_sdram_2_start &&
	469	addr_start <= ((sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size)))
930b5952 PF	470	return (PTE_BLOCK_MEMTYPE(MT_NORMAL) \| PTE_BLOCK_OUTER_SHARE);
	471
	472	return attr;
	473	}
	474
	475	static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
	476	{
	477	sc_faddr_t end1, end2;
2f36a693 MZ	478	u64 phys_sdram_1_start, phys_sdram_1_size;
	479	u64 phys_sdram_2_start, phys_sdram_2_size;
	480
	481	board_mem_get_layout(&phys_sdram_1_start, &phys_sdram_1_size,
	482	&phys_sdram_2_start, &phys_sdram_2_size);
	483
930b5952	484
2f36a693 MZ	485	end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
2f36a693 MZ	486	end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
930b5952	487
2f36a693	488	if (addr_start >= phys_sdram_1_start && addr_start <= end1) {
930b5952 PF	489	if ((addr_end + 1) > end1)
930b5952 PF	490	return end1 - addr_start;
2f36a693	491	} else if (addr_start >= phys_sdram_2_start && addr_start <= end2) {
930b5952 PF	492	if ((addr_end + 1) > end2)
	493	return end2 - addr_start;
	494	}
	495
	496	return (addr_end - addr_start + 1);
	497	}
	498
	499	#define MAX_PTE_ENTRIES 512
	500	#define MAX_MEM_MAP_REGIONS 16
	501
	502	static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
	503	struct mm_region *mem_map = imx8_mem_map;
	504
	505	void enable_caches(void)
	506	{
	507	sc_rm_mr_t mr;
	508	sc_faddr_t start, end;
	509	int err, i;
	510
	511	/* Create map for registers access from 0x1c000000 to 0x80000000*/
	512	imx8_mem_map[0].virt = 0x1c000000UL;
	513	imx8_mem_map[0].phys = 0x1c000000UL;
	514	imx8_mem_map[0].size = 0x64000000UL;
	515	imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	516	PTE_BLOCK_NON_SHARE \| PTE_BLOCK_PXN \| PTE_BLOCK_UXN;
	517
	518	i = 1;
	519	for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
	520	err = get_owned_memreg(mr, &start, &end);
	521	if (!err) {
	522	imx8_mem_map[i].virt = start;
	523	imx8_mem_map[i].phys = start;
	524	imx8_mem_map[i].size = get_block_size(start, end);
	525	imx8_mem_map[i].attrs = get_block_attrs(start);
	526	i++;
	527	}
	528	}
	529
	530	if (i < MAX_MEM_MAP_REGIONS) {
	531	imx8_mem_map[i].size = 0;
	532	imx8_mem_map[i].attrs = 0;
	533	} else {
	534	puts("Error, need more MEM MAP REGIONS reserved\n");
	535	icache_enable();
	536	return;
	537	}
	538
	539	for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
	540	debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
	541	i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
	542	imx8_mem_map[i].size, imx8_mem_map[i].attrs);
	543	}
	544
	545	icache_enable();
	546	dcache_enable();
	547	}
	548
10015025	549	#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
930b5952 PF	550	u64 get_page_table_size(void)
	551	{
	552	u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
	553	u64 size = 0;
	554
	555	/*
	556	* For each memory region, the max table size:
	557	* 2 level 3 tables + 2 level 2 tables + 1 level 1 table
	558	*/
	559	size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
	560
	561	/*
	562	* We need to duplicate our page table once to have an emergency pt to
	563	* resort to when splitting page tables later on
	564	*/
	565	size *= 2;
	566
	567	/*
	568	* We may need to split page tables later on if dcache settings change,
	569	* so reserve up to 4 (random pick) page tables for that.
	570	*/
	571	size += one_pt * 4;
	572
	573	return size;
	574	}
	575	#endif
70b4b49b	576
bae4e8cb PF	577	#if defined(CONFIG_IMX8QM)
	578	#define FUSE_MAC0_WORD0 452
	579	#define FUSE_MAC0_WORD1 453
	580	#define FUSE_MAC1_WORD0 454
	581	#define FUSE_MAC1_WORD1 455
	582	#elif defined(CONFIG_IMX8QXP)
70b4b49b AG	583	#define FUSE_MAC0_WORD0 708
	584	#define FUSE_MAC0_WORD1 709
	585	#define FUSE_MAC1_WORD0 710
	586	#define FUSE_MAC1_WORD1 711
bae4e8cb	587	#endif
70b4b49b AG	588
	589	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
	590	{
	591	u32 word[2], val[2] = {};
	592	int i, ret;
	593
	594	if (dev_id == 0) {
	595	word[0] = FUSE_MAC0_WORD0;
	596	word[1] = FUSE_MAC0_WORD1;
	597	} else {
	598	word[0] = FUSE_MAC1_WORD0;
	599	word[1] = FUSE_MAC1_WORD1;
	600	}
	601
	602	for (i = 0; i < 2; i++) {
	603	ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
	604	if (ret < 0)
	605	goto err;
	606	}
	607
	608	mac[0] = val[0];
	609	mac[1] = val[0] >> 8;
	610	mac[2] = val[0] >> 16;
	611	mac[3] = val[0] >> 24;
	612	mac[4] = val[1];
	613	mac[5] = val[1] >> 8;
	614
	615	debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
	616	__func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
	617	return;
	618	err:
	619	printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
	620	}
2fdb1a1d	621
2fdb1a1d AG	622	u32 get_cpu_rev(void)
	623	{
	624	u32 id = 0, rev = 0;
	625	int ret;
	626
	627	ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
	628	if (ret)
	629	return 0;
	630
	631	rev = (id >> 5) & 0xf;
	632	id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
	633
	634	return (id << 12) \| rev;
	635	}
42b26ddc YL	636
	637	void board_boot_order(u32 *spl_boot_list)
	638	{
	639	spl_boot_list[0] = spl_boot_device();
	640
	641	if (spl_boot_list[0] == BOOT_DEVICE_SPI) {
	642	/* Check whether we own the flexspi0, if not, use NOR boot */
	643	if (!sc_rm_is_resource_owned(-1, SC_R_FSPI_0))
	644	spl_boot_list[0] = BOOT_DEVICE_NOR;
	645	}
	646	}
ed5b253d PF	647
	648	bool m4_parts_booted(void)
	649	{
	650	sc_rm_pt_t m4_parts[2];
	651	int err;
	652
	653	err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]);
	654	if (err) {
	655	printf("%s get resource [%d] owner error: %d\n", __func__,
	656	SC_R_M4_0_PID0, err);
	657	return false;
	658	}
	659
	660	if (sc_pm_is_partition_started(-1, m4_parts[0]))
	661	return true;
	662
	663	if (is_imx8qm()) {
	664	err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]);
	665	if (err) {
	666	printf("%s get resource [%d] owner error: %d\n",
	667	__func__, SC_R_M4_1_PID0, err);
	668	return false;
	669	}
	670
	671	if (sc_pm_is_partition_started(-1, m4_parts[1]))
	672	return true;
	673	}
	674
	675	return false;
	676	}