[thirdparty/u-boot.git] / arch / arm / mach-imx / imx8 / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018 NXP
 */

#include <common.h>
#include <clk.h>
#include <cpu.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/uclass.h>
#include <errno.h>
#include <thermal.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-imx/cpu.h>
#include <asm/armv8/cpu.h>
#include <asm/armv8/mmu.h>
#include <asm/mach-imx/boot_mode.h>

DECLARE_GLOBAL_DATA_PTR;

#define BT_PASSOVER_TAG	0x504F
struct pass_over_info_t *get_pass_over_info(void)
{
	struct pass_over_info_t *p =
		(struct pass_over_info_t *)PASS_OVER_INFO_ADDR;

	if (p->barker != BT_PASSOVER_TAG ||
	    p->len != sizeof(struct pass_over_info_t))
		return NULL;

	return p;
}

int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
	struct pass_over_info_t *pass_over;

	if (is_soc_rev(CHIP_REV_A)) {
		pass_over = get_pass_over_info();
		if (pass_over && pass_over->g_ap_mu == 0) {
			/*
			 * When ap_mu is 0, means the U-Boot booted
			 * from first container
			 */
			sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
		}
	}
#endif

	return 0;
}

int arch_cpu_init_dm(void)
{
	struct udevice *devp;
	int node, ret;

	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");

	ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
	if (ret) {
		printf("could not get scu %d\n", ret);
		return ret;
	}

	return 0;
}

int print_bootinfo(void)
{
	enum boot_device bt_dev = get_boot_device();

	puts("Boot:  ");
	switch (bt_dev) {
	case SD1_BOOT:
		puts("SD0\n");
		break;
	case SD2_BOOT:
		puts("SD1\n");
		break;
	case SD3_BOOT:
		puts("SD2\n");
		break;
	case MMC1_BOOT:
		puts("MMC0\n");
		break;
	case MMC2_BOOT:
		puts("MMC1\n");
		break;
	case MMC3_BOOT:
		puts("MMC2\n");
		break;
	case FLEXSPI_BOOT:
		puts("FLEXSPI\n");
		break;
	case SATA_BOOT:
		puts("SATA\n");
		break;
	case NAND_BOOT:
		puts("NAND\n");
		break;
	case USB_BOOT:
		puts("USB\n");
		break;
	default:
		printf("Unknown device %u\n", bt_dev);
		break;
	}

	return 0;
}

enum boot_device get_boot_device(void)
{
	enum boot_device boot_dev = SD1_BOOT;

	sc_rsrc_t dev_rsrc;

	sc_misc_get_boot_dev(-1, &dev_rsrc);

	switch (dev_rsrc) {
	case SC_R_SDHC_0:
		boot_dev = MMC1_BOOT;
		break;
	case SC_R_SDHC_1:
		boot_dev = SD2_BOOT;
		break;
	case SC_R_SDHC_2:
		boot_dev = SD3_BOOT;
		break;
	case SC_R_NAND:
		boot_dev = NAND_BOOT;
		break;
	case SC_R_FSPI_0:
		boot_dev = FLEXSPI_BOOT;
		break;
	case SC_R_SATA_0:
		boot_dev = SATA_BOOT;
		break;
	case SC_R_USB_0:
	case SC_R_USB_1:
	case SC_R_USB_2:
		boot_dev = USB_BOOT;
		break;
	default:
		break;
	}

	return boot_dev;
}

#ifdef CONFIG_ENV_IS_IN_MMC
__weak int board_mmc_get_env_dev(int devno)
{
	return CONFIG_SYS_MMC_ENV_DEV;
}

int mmc_get_env_dev(void)
{
	sc_rsrc_t dev_rsrc;
	int devno;

	sc_misc_get_boot_dev(-1, &dev_rsrc);

	switch (dev_rsrc) {
	case SC_R_SDHC_0:
		devno = 0;
		break;
	case SC_R_SDHC_1:
		devno = 1;
		break;
	case SC_R_SDHC_2:
		devno = 2;
		break;
	default:
		/* If not boot from sd/mmc, use default value */
		return CONFIG_SYS_MMC_ENV_DEV;
	}

	return board_mmc_get_env_dev(devno);
}
#endif

#define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */

static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
			    sc_faddr_t *addr_end)
{
	sc_faddr_t start, end;
	int ret;
	bool owned;

	owned = sc_rm_is_memreg_owned(-1, mr);
	if (owned) {
		ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
		if (ret) {
			printf("Memreg get info failed, %d\n", ret);
			return -EINVAL;
		}
		debug("0x%llx -- 0x%llx\n", start, end);
		*addr_start = start;
		*addr_end = end;

		return 0;
	}

	return -EINVAL;
}

phys_size_t get_effective_memsize(void)
{
	sc_rm_mr_t mr;
	sc_faddr_t start, end, end1;
	int err;

	end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;

	for (mr = 0; mr < 64; mr++) {
		err = get_owned_memreg(mr, &start, &end);
		if (!err) {
			start = roundup(start, MEMSTART_ALIGNMENT);
			/* Too small memory region, not use it */
			if (start > end)
				continue;

			/* Find the memory region runs the U-Boot */
			if (start >= PHYS_SDRAM_1 && start <= end1 &&
			    (start <= CONFIG_SYS_TEXT_BASE &&
			    end >= CONFIG_SYS_TEXT_BASE)) {
				if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
				    PHYS_SDRAM_1_SIZE))
					return (end - PHYS_SDRAM_1 + 1);
				else
					return PHYS_SDRAM_1_SIZE;
			}
		}
	}

	return PHYS_SDRAM_1_SIZE;
}

int dram_init(void)
{
	sc_rm_mr_t mr;
	sc_faddr_t start, end, end1, end2;
	int err;

	end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
	end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
	for (mr = 0; mr < 64; mr++) {
		err = get_owned_memreg(mr, &start, &end);
		if (!err) {
			start = roundup(start, MEMSTART_ALIGNMENT);
			/* Too small memory region, not use it */
			if (start > end)
				continue;

			if (start >= PHYS_SDRAM_1 && start <= end1) {
				if ((end + 1) <= end1)
					gd->ram_size += end - start + 1;
				else
					gd->ram_size += end1 - start;
			} else if (start >= PHYS_SDRAM_2 && start <= end2) {
				if ((end + 1) <= end2)
					gd->ram_size += end - start + 1;
				else
					gd->ram_size += end2 - start;
			}
		}
	}

	/* If error, set to the default value */
	if (!gd->ram_size) {
		gd->ram_size = PHYS_SDRAM_1_SIZE;
		gd->ram_size += PHYS_SDRAM_2_SIZE;
	}
	return 0;
}

static void dram_bank_sort(int current_bank)
{
	phys_addr_t start;
	phys_size_t size;

	while (current_bank > 0) {
		if (gd->bd->bi_dram[current_bank - 1].start >
		    gd->bd->bi_dram[current_bank].start) {
			start = gd->bd->bi_dram[current_bank - 1].start;
			size = gd->bd->bi_dram[current_bank - 1].size;

			gd->bd->bi_dram[current_bank - 1].start =
				gd->bd->bi_dram[current_bank].start;
			gd->bd->bi_dram[current_bank - 1].size =
				gd->bd->bi_dram[current_bank].size;

			gd->bd->bi_dram[current_bank].start = start;
			gd->bd->bi_dram[current_bank].size = size;
		}
		current_bank--;
	}
}

int dram_init_banksize(void)
{
	sc_rm_mr_t mr;
	sc_faddr_t start, end, end1, end2;
	int i = 0;
	int err;

	end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
	end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;

	for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
		err = get_owned_memreg(mr, &start, &end);
		if (!err) {
			start = roundup(start, MEMSTART_ALIGNMENT);
			if (start > end) /* Small memory region, no use it */
				continue;

			if (start >= PHYS_SDRAM_1 && start <= end1) {
				gd->bd->bi_dram[i].start = start;

				if ((end + 1) <= end1)
					gd->bd->bi_dram[i].size =
						end - start + 1;
				else
					gd->bd->bi_dram[i].size = end1 - start;

				dram_bank_sort(i);
				i++;
			} else if (start >= PHYS_SDRAM_2 && start <= end2) {
				gd->bd->bi_dram[i].start = start;

				if ((end + 1) <= end2)
					gd->bd->bi_dram[i].size =
						end - start + 1;
				else
					gd->bd->bi_dram[i].size = end2 - start;

				dram_bank_sort(i);
				i++;
			}
		}
	}

	/* If error, set to the default value */
	if (!i) {
		gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
		gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
		gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
	}

	return 0;
}

static u64 get_block_attrs(sc_faddr_t addr_start)
{
	u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
		PTE_BLOCK_PXN | PTE_BLOCK_UXN;

	if ((addr_start >= PHYS_SDRAM_1 &&
	     addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
	    (addr_start >= PHYS_SDRAM_2 &&
	     addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
		return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);

	return attr;
}

static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
{
	sc_faddr_t end1, end2;

	end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
	end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;

	if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
		if ((addr_end + 1) > end1)
			return end1 - addr_start;
	} else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
		if ((addr_end + 1) > end2)
			return end2 - addr_start;
	}

	return (addr_end - addr_start + 1);
}

#define MAX_PTE_ENTRIES 512
#define MAX_MEM_MAP_REGIONS 16

static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
struct mm_region *mem_map = imx8_mem_map;

void enable_caches(void)
{
	sc_rm_mr_t mr;
	sc_faddr_t start, end;
	int err, i;

	/* Create map for registers access from 0x1c000000 to 0x80000000*/
	imx8_mem_map[0].virt = 0x1c000000UL;
	imx8_mem_map[0].phys = 0x1c000000UL;
	imx8_mem_map[0].size = 0x64000000UL;
	imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;

	i = 1;
	for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
		err = get_owned_memreg(mr, &start, &end);
		if (!err) {
			imx8_mem_map[i].virt = start;
			imx8_mem_map[i].phys = start;
			imx8_mem_map[i].size = get_block_size(start, end);
			imx8_mem_map[i].attrs = get_block_attrs(start);
			i++;
		}
	}

	if (i < MAX_MEM_MAP_REGIONS) {
		imx8_mem_map[i].size = 0;
		imx8_mem_map[i].attrs = 0;
	} else {
		puts("Error, need more MEM MAP REGIONS reserved\n");
		icache_enable();
		return;
	}

	for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
		debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
		      i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
		      imx8_mem_map[i].size, imx8_mem_map[i].attrs);
	}

	icache_enable();
	dcache_enable();
}

#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
u64 get_page_table_size(void)
{
	u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
	u64 size = 0;

	/*
	 * For each memory region, the max table size:
	 * 2 level 3 tables + 2 level 2 tables + 1 level 1 table
	 */
	size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;

	/*
	 * We need to duplicate our page table once to have an emergency pt to
	 * resort to when splitting page tables later on
	 */
	size *= 2;

	/*
	 * We may need to split page tables later on if dcache settings change,
	 * so reserve up to 4 (random pick) page tables for that.
	 */
	size += one_pt * 4;

	return size;
}
#endif

#define FUSE_MAC0_WORD0 708
#define FUSE_MAC0_WORD1 709
#define FUSE_MAC1_WORD0 710
#define FUSE_MAC1_WORD1 711

void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	u32 word[2], val[2] = {};
	int i, ret;

	if (dev_id == 0) {
		word[0] = FUSE_MAC0_WORD0;
		word[1] = FUSE_MAC0_WORD1;
	} else {
		word[0] = FUSE_MAC1_WORD0;
		word[1] = FUSE_MAC1_WORD1;
	}

	for (i = 0; i < 2; i++) {
		ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
		if (ret < 0)
			goto err;
	}

	mac[0] = val[0];
	mac[1] = val[0] >> 8;
	mac[2] = val[0] >> 16;
	mac[3] = val[0] >> 24;
	mac[4] = val[1];
	mac[5] = val[1] >> 8;

	debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
	      __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
	return;
err:
	printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
}

u32 get_cpu_rev(void)
{
	u32 id = 0, rev = 0;
	int ret;

	ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
	if (ret)
		return 0;

	rev = (id >> 5)  & 0xf;
	id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */

	return (id << 12) | rev;
}

#if CONFIG_IS_ENABLED(CPU)
struct cpu_imx_platdata {
	const char *name;
	const char *rev;
	const char *type;
	u32 cpurev;
	u32 freq_mhz;
};

const char *get_imx8_type(u32 imxtype)
{
	switch (imxtype) {
	case MXC_CPU_IMX8QXP:
	case MXC_CPU_IMX8QXP_A0:
		return "QXP";
	case MXC_CPU_IMX8QM:
		return "QM";
	default:
		return "??";
	}
}

const char *get_imx8_rev(u32 rev)
{
	switch (rev) {
	case CHIP_REV_A:
		return "A";
	case CHIP_REV_B:
		return "B";
	default:
		return "?";
	}
}

const char *get_core_name(void)
{
	if (is_cortex_a35())
		return "A35";
	else if (is_cortex_a53())
		return "A53";
	else if (is_cortex_a72())
		return "A72";
	else
		return "?";
}

#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
static int cpu_imx_get_temp(void)
{
	struct udevice *thermal_dev;
	int cpu_tmp, ret;

	ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0",
					&thermal_dev);

	if (!ret) {
		ret = thermal_get_temp(thermal_dev, &cpu_tmp);
		if (ret)
			return 0xdeadbeef;
	} else {
		return 0xdeadbeef;
	}

	return cpu_tmp;
}
#else
static int cpu_imx_get_temp(void)
{
	return 0;
}
#endif

int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
{
	struct cpu_imx_platdata *plat = dev_get_platdata(dev);
	int ret;

	if (size < 100)
		return -ENOSPC;

	ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
		       plat->type, plat->rev, plat->name, plat->freq_mhz);

	if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
		buf = buf + ret;
		size = size - ret;
		ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
	}

	snprintf(buf + ret, size - ret, "\n");

	return 0;
}

static int cpu_imx_get_info(struct udevice *dev, struct cpu_info *info)
{
	struct cpu_imx_platdata *plat = dev_get_platdata(dev);

	info->cpu_freq = plat->freq_mhz * 1000;
	info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
	return 0;
}

static int cpu_imx_get_count(struct udevice *dev)
{
	return 4;
}

static int cpu_imx_get_vendor(struct udevice *dev,  char *buf, int size)
{
	snprintf(buf, size, "NXP");
	return 0;
}

static const struct cpu_ops cpu_imx8_ops = {
	.get_desc	= cpu_imx_get_desc,
	.get_info	= cpu_imx_get_info,
	.get_count	= cpu_imx_get_count,
	.get_vendor	= cpu_imx_get_vendor,
};

static const struct udevice_id cpu_imx8_ids[] = {
	{ .compatible = "arm,cortex-a35" },
	{ .compatible = "arm,cortex-a53" },
	{ }
};

static ulong imx8_get_cpu_rate(void)
{
	ulong rate;
	int ret;
	int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ?
		   SC_R_A53 : SC_R_A72;

	ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU,
				   (sc_pm_clock_rate_t *)&rate);
	if (ret) {
		printf("Could not read CPU frequency: %d\n", ret);
		return 0;
	}

	return rate;
}

static int imx8_cpu_probe(struct udevice *dev)
{
	struct cpu_imx_platdata *plat = dev_get_platdata(dev);
	u32 cpurev;

	cpurev = get_cpu_rev();
	plat->cpurev = cpurev;
	plat->name = get_core_name();
	plat->rev = get_imx8_rev(cpurev & 0xFFF);
	plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
	plat->freq_mhz = imx8_get_cpu_rate() / 1000000;
	return 0;
}

U_BOOT_DRIVER(cpu_imx8_drv) = {
	.name		= "imx8x_cpu",
	.id		= UCLASS_CPU,
	.of_match	= cpu_imx8_ids,
	.ops		= &cpu_imx8_ops,
	.probe		= imx8_cpu_probe,
	.platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata),
	.flags		= DM_FLAG_PRE_RELOC,
};
#endif
Commit	Line	Data
60d33fcd PF	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright 2018 NXP
	4	*/
	5
	6	#include <common.h>
	7	#include <clk.h>
2fdb1a1d	8	#include <cpu.h>
60d33fcd PF	9	#include <dm.h>
	10	#include <dm/device-internal.h>
	11	#include <dm/lists.h>
	12	#include <dm/uclass.h>
	13	#include <errno.h>
1796e509	14	#include <thermal.h>
60d33fcd	15	#include <asm/arch/sci/sci.h>
8aa1505b	16	#include <asm/arch/sys_proto.h>
60d33fcd PF	17	#include <asm/arch-imx/cpu.h>
60d33fcd PF	18	#include <asm/armv8/cpu.h>
930b5952	19	#include <asm/armv8/mmu.h>
8aa1505b	20	#include <asm/mach-imx/boot_mode.h>
60d33fcd PF	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
1ef20a3d PF	24	#define BT_PASSOVER_TAG 0x504F
	25	struct pass_over_info_t *get_pass_over_info(void)
	26	{
	27	struct pass_over_info_t *p =
	28	(struct pass_over_info_t *)PASS_OVER_INFO_ADDR;
	29
	30	if (p->barker != BT_PASSOVER_TAG \|\|
	31	p->len != sizeof(struct pass_over_info_t))
	32	return NULL;
	33
	34	return p;
	35	}
	36
	37	int arch_cpu_init(void)
	38	{
9382f73b PF	39	#ifdef CONFIG_SPL_BUILD
	40	struct pass_over_info_t *pass_over;
	41
	42	if (is_soc_rev(CHIP_REV_A)) {
	43	pass_over = get_pass_over_info();
	44	if (pass_over && pass_over->g_ap_mu == 0) {
	45	/*
	46	* When ap_mu is 0, means the U-Boot booted
	47	* from first container
	48	*/
	49	sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
	50	}
1ef20a3d	51	}
9382f73b	52	#endif
1ef20a3d PF	53
	54	return 0;
	55	}
	56
	57	int arch_cpu_init_dm(void)
	58	{
	59	struct udevice *devp;
	60	int node, ret;
	61
	62	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu");
1ef20a3d	63
bcf94abd	64	ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
1ef20a3d	65	if (ret) {
bcf94abd	66	printf("could not get scu %d\n", ret);
1ef20a3d PF	67	return ret;
	68	}
	69
	70	return 0;
	71	}
	72
8aa1505b PF	73	int print_bootinfo(void)
	74	{
	75	enum boot_device bt_dev = get_boot_device();
	76
	77	puts("Boot: ");
	78	switch (bt_dev) {
	79	case SD1_BOOT:
	80	puts("SD0\n");
	81	break;
	82	case SD2_BOOT:
	83	puts("SD1\n");
	84	break;
	85	case SD3_BOOT:
	86	puts("SD2\n");
	87	break;
	88	case MMC1_BOOT:
	89	puts("MMC0\n");
	90	break;
	91	case MMC2_BOOT:
	92	puts("MMC1\n");
	93	break;
	94	case MMC3_BOOT:
	95	puts("MMC2\n");
	96	break;
	97	case FLEXSPI_BOOT:
	98	puts("FLEXSPI\n");
	99	break;
	100	case SATA_BOOT:
	101	puts("SATA\n");
	102	break;
	103	case NAND_BOOT:
	104	puts("NAND\n");
	105	break;
	106	case USB_BOOT:
	107	puts("USB\n");
	108	break;
	109	default:
	110	printf("Unknown device %u\n", bt_dev);
	111	break;
	112	}
	113
	114	return 0;
	115	}
	116
	117	enum boot_device get_boot_device(void)
	118	{
	119	enum boot_device boot_dev = SD1_BOOT;
	120
	121	sc_rsrc_t dev_rsrc;
	122
	123	sc_misc_get_boot_dev(-1, &dev_rsrc);
	124
	125	switch (dev_rsrc) {
	126	case SC_R_SDHC_0:
	127	boot_dev = MMC1_BOOT;
	128	break;
	129	case SC_R_SDHC_1:
	130	boot_dev = SD2_BOOT;
	131	break;
	132	case SC_R_SDHC_2:
	133	boot_dev = SD3_BOOT;
	134	break;
	135	case SC_R_NAND:
	136	boot_dev = NAND_BOOT;
137	break;
138	case SC_R_FSPI_0:
139	boot_dev = FLEXSPI_BOOT;
140	break;
141	case SC_R_SATA_0:
142	boot_dev = SATA_BOOT;
143	break;
144	case SC_R_USB_0:
145	case SC_R_USB_1:
146	case SC_R_USB_2:
147	boot_dev = USB_BOOT;
148	break;
149	default:
150	break;
151	}
152
153	return boot_dev;
154	}
c1aae21d PF	155
	156	#ifdef CONFIG_ENV_IS_IN_MMC
	157	__weak int board_mmc_get_env_dev(int devno)
	158	{
	159	return CONFIG_SYS_MMC_ENV_DEV;
	160	}
	161
	162	int mmc_get_env_dev(void)
	163	{
	164	sc_rsrc_t dev_rsrc;
	165	int devno;
	166
	167	sc_misc_get_boot_dev(-1, &dev_rsrc);
	168
	169	switch (dev_rsrc) {
	170	case SC_R_SDHC_0:
	171	devno = 0;
	172	break;
	173	case SC_R_SDHC_1:
	174	devno = 1;
	175	break;
	176	case SC_R_SDHC_2:
	177	devno = 2;
	178	break;
	179	default:
	180	/* If not boot from sd/mmc, use default value */
	181	return CONFIG_SYS_MMC_ENV_DEV;
	182	}
	183
	184	return board_mmc_get_env_dev(devno);
	185	}
	186	#endif
930b5952 PF	187
	188	#define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
	189
	190	static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
	191	sc_faddr_t *addr_end)
	192	{
	193	sc_faddr_t start, end;
	194	int ret;
	195	bool owned;
	196
	197	owned = sc_rm_is_memreg_owned(-1, mr);
	198	if (owned) {
	199	ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
	200	if (ret) {
	201	printf("Memreg get info failed, %d\n", ret);
	202	return -EINVAL;
	203	}
	204	debug("0x%llx -- 0x%llx\n", start, end);
	205	*addr_start = start;
	206	*addr_end = end;
	207
	208	return 0;
	209	}
	210
	211	return -EINVAL;
	212	}
	213
	214	phys_size_t get_effective_memsize(void)
	215	{
	216	sc_rm_mr_t mr;
	217	sc_faddr_t start, end, end1;
	218	int err;
	219
	220	end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
	221
	222	for (mr = 0; mr < 64; mr++) {
	223	err = get_owned_memreg(mr, &start, &end);
	224	if (!err) {
	225	start = roundup(start, MEMSTART_ALIGNMENT);
	226	/* Too small memory region, not use it */
	227	if (start > end)
	228	continue;
	229
1ef20a3d	230	/* Find the memory region runs the U-Boot */
930b5952 PF	231	if (start >= PHYS_SDRAM_1 && start <= end1 &&
	232	(start <= CONFIG_SYS_TEXT_BASE &&
	233	end >= CONFIG_SYS_TEXT_BASE)) {
	234	if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
	235	PHYS_SDRAM_1_SIZE))
	236	return (end - PHYS_SDRAM_1 + 1);
	237	else
	238	return PHYS_SDRAM_1_SIZE;
	239	}
	240	}
	241	}
	242
	243	return PHYS_SDRAM_1_SIZE;
	244	}
	245
	246	int dram_init(void)
	247	{
	248	sc_rm_mr_t mr;
	249	sc_faddr_t start, end, end1, end2;
	250	int err;
	251
	252	end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
	253	end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
	254	for (mr = 0; mr < 64; mr++) {
	255	err = get_owned_memreg(mr, &start, &end);
	256	if (!err) {
	257	start = roundup(start, MEMSTART_ALIGNMENT);
	258	/* Too small memory region, not use it */
	259	if (start > end)
	260	continue;
	261
	262	if (start >= PHYS_SDRAM_1 && start <= end1) {
	263	if ((end + 1) <= end1)
	264	gd->ram_size += end - start + 1;
	265	else
	266	gd->ram_size += end1 - start;
	267	} else if (start >= PHYS_SDRAM_2 && start <= end2) {
	268	if ((end + 1) <= end2)
	269	gd->ram_size += end - start + 1;
	270	else
	271	gd->ram_size += end2 - start;
	272	}
	273	}
	274	}
	275
	276	/* If error, set to the default value */
	277	if (!gd->ram_size) {
	278	gd->ram_size = PHYS_SDRAM_1_SIZE;
	279	gd->ram_size += PHYS_SDRAM_2_SIZE;
	280	}
	281	return 0;
	282	}
	283
	284	static void dram_bank_sort(int current_bank)
	285	{
	286	phys_addr_t start;
	287	phys_size_t size;
	288
	289	while (current_bank > 0) {
	290	if (gd->bd->bi_dram[current_bank - 1].start >
	291	gd->bd->bi_dram[current_bank].start) {
	292	start = gd->bd->bi_dram[current_bank - 1].start;
	293	size = gd->bd->bi_dram[current_bank - 1].size;
	294
295	gd->bd->bi_dram[current_bank - 1].start =
296	gd->bd->bi_dram[current_bank].start;
297	gd->bd->bi_dram[current_bank - 1].size =
298	gd->bd->bi_dram[current_bank].size;
299
300	gd->bd->bi_dram[current_bank].start = start;
301	gd->bd->bi_dram[current_bank].size = size;
302	}
303	current_bank--;
304	}
305	}
306
307	int dram_init_banksize(void)
308	{
309	sc_rm_mr_t mr;
310	sc_faddr_t start, end, end1, end2;
311	int i = 0;
312	int err;
313
314	end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
315	end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
316
317	for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
318	err = get_owned_memreg(mr, &start, &end);
319	if (!err) {
320	start = roundup(start, MEMSTART_ALIGNMENT);
321	if (start > end) /* Small memory region, no use it */
322	continue;
323
324	if (start >= PHYS_SDRAM_1 && start <= end1) {
325	gd->bd->bi_dram[i].start = start;
326
327	if ((end + 1) <= end1)
328	gd->bd->bi_dram[i].size =
329	end - start + 1;
330	else
331	gd->bd->bi_dram[i].size = end1 - start;
332
333	dram_bank_sort(i);
334	i++;
335	} else if (start >= PHYS_SDRAM_2 && start <= end2) {
336	gd->bd->bi_dram[i].start = start;
337
338	if ((end + 1) <= end2)
339	gd->bd->bi_dram[i].size =
340	end - start + 1;
341	else
342	gd->bd->bi_dram[i].size = end2 - start;
343
344	dram_bank_sort(i);
345	i++;
346	}
347	}
348	}
349
350	/* If error, set to the default value */
351	if (!i) {
352	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
353	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
354	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
355	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
356	}
357
358	return 0;
359	}
360
361	static u64 get_block_attrs(sc_faddr_t addr_start)
362	{
363	u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \| PTE_BLOCK_NON_SHARE \|
364	PTE_BLOCK_PXN \| PTE_BLOCK_UXN;
365
366	if ((addr_start >= PHYS_SDRAM_1 &&
367	addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) \|\|
368	(addr_start >= PHYS_SDRAM_2 &&
369	addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
370	return (PTE_BLOCK_MEMTYPE(MT_NORMAL) \| PTE_BLOCK_OUTER_SHARE);
371
372	return attr;
373	}
374
375	static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
376	{
377	sc_faddr_t end1, end2;
378
379	end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
380	end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
381
382	if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
383	if ((addr_end + 1) > end1)
384	return end1 - addr_start;
385	} else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
386	if ((addr_end + 1) > end2)
387	return end2 - addr_start;
388	}
389
390	return (addr_end - addr_start + 1);
391	}
392
393	#define MAX_PTE_ENTRIES 512
394	#define MAX_MEM_MAP_REGIONS 16
395
396	static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
397	struct mm_region *mem_map = imx8_mem_map;
398
399	void enable_caches(void)
400	{
401	sc_rm_mr_t mr;
402	sc_faddr_t start, end;
403	int err, i;
404
405	/* Create map for registers access from 0x1c000000 to 0x80000000*/
406	imx8_mem_map[0].virt = 0x1c000000UL;
407	imx8_mem_map[0].phys = 0x1c000000UL;
408	imx8_mem_map[0].size = 0x64000000UL;
409	imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
410	PTE_BLOCK_NON_SHARE \| PTE_BLOCK_PXN \| PTE_BLOCK_UXN;
411
412	i = 1;
413	for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
414	err = get_owned_memreg(mr, &start, &end);
415	if (!err) {
416	imx8_mem_map[i].virt = start;
417	imx8_mem_map[i].phys = start;
418	imx8_mem_map[i].size = get_block_size(start, end);
419	imx8_mem_map[i].attrs = get_block_attrs(start);
420	i++;
421	}
422	}
423
424	if (i < MAX_MEM_MAP_REGIONS) {
425	imx8_mem_map[i].size = 0;
426	imx8_mem_map[i].attrs = 0;
427	} else {
428	puts("Error, need more MEM MAP REGIONS reserved\n");
429	icache_enable();
430	return;
431	}
432
433	for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
434	debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
435	i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
436	imx8_mem_map[i].size, imx8_mem_map[i].attrs);
437	}
438
439	icache_enable();
440	dcache_enable();
441	}
442
10015025	443	#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
930b5952 PF	444	u64 get_page_table_size(void)
	445	{
	446	u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
	447	u64 size = 0;
	448
	449	/*
	450	* For each memory region, the max table size:
	451	* 2 level 3 tables + 2 level 2 tables + 1 level 1 table
	452	*/
	453	size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
	454
	455	/*
	456	* We need to duplicate our page table once to have an emergency pt to
	457	* resort to when splitting page tables later on
	458	*/
	459	size *= 2;
	460
	461	/*
	462	* We may need to split page tables later on if dcache settings change,
	463	* so reserve up to 4 (random pick) page tables for that.
	464	*/
	465	size += one_pt * 4;
	466
	467	return size;
	468	}
	469	#endif
70b4b49b AG	470
	471	#define FUSE_MAC0_WORD0 708
	472	#define FUSE_MAC0_WORD1 709
	473	#define FUSE_MAC1_WORD0 710
	474	#define FUSE_MAC1_WORD1 711
	475
	476	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
	477	{
	478	u32 word[2], val[2] = {};
	479	int i, ret;
	480
	481	if (dev_id == 0) {
	482	word[0] = FUSE_MAC0_WORD0;
	483	word[1] = FUSE_MAC0_WORD1;
	484	} else {
	485	word[0] = FUSE_MAC1_WORD0;
	486	word[1] = FUSE_MAC1_WORD1;
	487	}
	488
	489	for (i = 0; i < 2; i++) {
	490	ret = sc_misc_otp_fuse_read(-1, word[i], &val[i]);
	491	if (ret < 0)
	492	goto err;
	493	}
	494
	495	mac[0] = val[0];
	496	mac[1] = val[0] >> 8;
	497	mac[2] = val[0] >> 16;
	498	mac[3] = val[0] >> 24;
	499	mac[4] = val[1];
	500	mac[5] = val[1] >> 8;
	501
	502	debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
	503	__func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
	504	return;
	505	err:
	506	printf("%s: fuse %d, err: %d\n", __func__, word[i], ret);
	507	}
2fdb1a1d	508
2fdb1a1d AG	509	u32 get_cpu_rev(void)
	510	{
	511	u32 id = 0, rev = 0;
	512	int ret;
	513
	514	ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
	515	if (ret)
	516	return 0;
	517
	518	rev = (id >> 5) & 0xf;
	519	id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */
	520
	521	return (id << 12) \| rev;
	522	}
	523
9382f73b PF	524	#if CONFIG_IS_ENABLED(CPU)
	525	struct cpu_imx_platdata {
	526	const char *name;
	527	const char *rev;
	528	const char *type;
	529	u32 cpurev;
	530	u32 freq_mhz;
	531	};
	532
2fdb1a1d AG	533	const char *get_imx8_type(u32 imxtype)
	534	{
	535	switch (imxtype) {
	536	case MXC_CPU_IMX8QXP:
	537	case MXC_CPU_IMX8QXP_A0:
	538	return "QXP";
7f50af60 PF	539	case MXC_CPU_IMX8QM:
7f50af60 PF	540	return "QM";
2fdb1a1d AG	541	default:
	542	return "??";
	543	}
	544	}
	545
	546	const char *get_imx8_rev(u32 rev)
	547	{
	548	switch (rev) {
	549	case CHIP_REV_A:
	550	return "A";
	551	case CHIP_REV_B:
	552	return "B";
	553	default:
	554	return "?";
	555	}
	556	}
	557
	558	const char *get_core_name(void)
	559	{
	560	if (is_cortex_a35())
	561	return "A35";
	562	else if (is_cortex_a53())
	563	return "A53";
	564	else if (is_cortex_a72())
	565	return "A72";
	566	else
	567	return "?";
	568	}
	569
1796e509 PF	570	#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
	571	static int cpu_imx_get_temp(void)
	572	{
	573	struct udevice *thermal_dev;
	574	int cpu_tmp, ret;
	575
	576	ret = uclass_get_device_by_name(UCLASS_THERMAL, "cpu-thermal0",
	577	&thermal_dev);
	578
	579	if (!ret) {
	580	ret = thermal_get_temp(thermal_dev, &cpu_tmp);
	581	if (ret)
	582	return 0xdeadbeef;
	583	} else {
	584	return 0xdeadbeef;
	585	}
	586
	587	return cpu_tmp;
	588	}
	589	#else
	590	static int cpu_imx_get_temp(void)
	591	{
	592	return 0;
	593	}
	594	#endif
	595
2fdb1a1d AG	596	int cpu_imx_get_desc(struct udevice dev, char buf, int size)
	597	{
	598	struct cpu_imx_platdata *plat = dev_get_platdata(dev);
1796e509	599	int ret;
2fdb1a1d AG	600
	601	if (size < 100)
	602	return -ENOSPC;
	603
1796e509 PF	604	ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
	605	plat->type, plat->rev, plat->name, plat->freq_mhz);
	606
	607	if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
	608	buf = buf + ret;
	609	size = size - ret;
	610	ret = snprintf(buf, size, " at %dC", cpu_imx_get_temp());
	611	}
	612
	613	snprintf(buf + ret, size - ret, "\n");
2fdb1a1d AG	614
	615	return 0;
	616	}
	617
	618	static int cpu_imx_get_info(struct udevice dev, struct cpu_info info)
	619	{
	620	struct cpu_imx_platdata *plat = dev_get_platdata(dev);
	621
	622	info->cpu_freq = plat->freq_mhz * 1000;
	623	info->features = BIT(CPU_FEAT_L1_CACHE) \| BIT(CPU_FEAT_MMU);
	624	return 0;
	625	}
	626
	627	static int cpu_imx_get_count(struct udevice *dev)
	628	{
	629	return 4;
	630	}
	631
	632	static int cpu_imx_get_vendor(struct udevice dev, char buf, int size)
	633	{
	634	snprintf(buf, size, "NXP");
	635	return 0;
	636	}
	637
	638	static const struct cpu_ops cpu_imx8_ops = {
	639	.get_desc = cpu_imx_get_desc,
	640	.get_info = cpu_imx_get_info,
	641	.get_count = cpu_imx_get_count,
	642	.get_vendor = cpu_imx_get_vendor,
	643	};
	644
	645	static const struct udevice_id cpu_imx8_ids[] = {
	646	{ .compatible = "arm,cortex-a35" },
7f50af60	647	{ .compatible = "arm,cortex-a53" },
2fdb1a1d AG	648	{ }
	649	};
	650
75cd09cb FE	651	static ulong imx8_get_cpu_rate(void)
	652	{
	653	ulong rate;
	654	int ret;
1da39d3c MZ	655	int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ?
1da39d3c MZ	656	SC_R_A53 : SC_R_A72;
75cd09cb	657
1da39d3c	658	ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU,
75cd09cb FE	659	(sc_pm_clock_rate_t *)&rate);
	660	if (ret) {
	661	printf("Could not read CPU frequency: %d\n", ret);
	662	return 0;
	663	}
	664
	665	return rate;
	666	}
	667
2fdb1a1d AG	668	static int imx8_cpu_probe(struct udevice *dev)
	669	{
	670	struct cpu_imx_platdata *plat = dev_get_platdata(dev);
2fdb1a1d	671	u32 cpurev;
2fdb1a1d AG	672
	673	cpurev = get_cpu_rev();
	674	plat->cpurev = cpurev;
	675	plat->name = get_core_name();
	676	plat->rev = get_imx8_rev(cpurev & 0xFFF);
	677	plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
75cd09cb	678	plat->freq_mhz = imx8_get_cpu_rate() / 1000000;
2fdb1a1d AG	679	return 0;
	680	}
	681
	682	U_BOOT_DRIVER(cpu_imx8_drv) = {
	683	.name = "imx8x_cpu",
	684	.id = UCLASS_CPU,
	685	.of_match = cpu_imx8_ids,
	686	.ops = &cpu_imx8_ops,
	687	.probe = imx8_cpu_probe,
	688	.platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata),
	689	.flags = DM_FLAG_PRE_RELOC,
	690	};
	691	#endif