[thirdparty/linux.git] / arch / arm / mach-imx / irq.c

/*
 *  linux/arch/arm/mach-imx/irq.c
 *
 *  Copyright (C) 1999 ARM Limited
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *  03/03/2004   Sascha Hauer <sascha@saschahauer.de>
 *               Copied from the motorola bsp package and added gpio demux
 *               interrupt handler
 */

#include <linux/init.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <asm/irq.h>

#include <asm/mach/irq.h>

/*
 *
 * We simply use the ENABLE DISABLE registers inside of the IMX
 * to turn on/off specific interrupts.  FIXME- We should
 * also add support for the accelerated interrupt controller
 * by putting offets to irq jump code in the appropriate
 * places.
 *
 */

#define INTCNTL_OFF               0x00
#define NIMASK_OFF                0x04
#define INTENNUM_OFF              0x08
#define INTDISNUM_OFF             0x0C
#define INTENABLEH_OFF            0x10
#define INTENABLEL_OFF            0x14
#define INTTYPEH_OFF              0x18
#define INTTYPEL_OFF              0x1C
#define NIPRIORITY_OFF(x)         (0x20+4*(7-(x)))
#define NIVECSR_OFF               0x40
#define FIVECSR_OFF               0x44
#define INTSRCH_OFF               0x48
#define INTSRCL_OFF               0x4C
#define INTFRCH_OFF               0x50
#define INTFRCL_OFF               0x54
#define NIPNDH_OFF                0x58
#define NIPNDL_OFF                0x5C
#define FIPNDH_OFF                0x60
#define FIPNDL_OFF                0x64

#define VA_AITC_BASE              IO_ADDRESS(IMX_AITC_BASE)
#define IMX_AITC_INTCNTL         (VA_AITC_BASE + INTCNTL_OFF)
#define IMX_AITC_NIMASK          (VA_AITC_BASE + NIMASK_OFF)
#define IMX_AITC_INTENNUM        (VA_AITC_BASE + INTENNUM_OFF)
#define IMX_AITC_INTDISNUM       (VA_AITC_BASE + INTDISNUM_OFF)
#define IMX_AITC_INTENABLEH      (VA_AITC_BASE + INTENABLEH_OFF)
#define IMX_AITC_INTENABLEL      (VA_AITC_BASE + INTENABLEL_OFF)
#define IMX_AITC_INTTYPEH        (VA_AITC_BASE + INTTYPEH_OFF)
#define IMX_AITC_INTTYPEL        (VA_AITC_BASE + INTTYPEL_OFF)
#define IMX_AITC_NIPRIORITY(x)   (VA_AITC_BASE + NIPRIORITY_OFF(x))
#define IMX_AITC_NIVECSR         (VA_AITC_BASE + NIVECSR_OFF)
#define IMX_AITC_FIVECSR         (VA_AITC_BASE + FIVECSR_OFF)
#define IMX_AITC_INTSRCH         (VA_AITC_BASE + INTSRCH_OFF)
#define IMX_AITC_INTSRCL         (VA_AITC_BASE + INTSRCL_OFF)
#define IMX_AITC_INTFRCH         (VA_AITC_BASE + INTFRCH_OFF)
#define IMX_AITC_INTFRCL         (VA_AITC_BASE + INTFRCL_OFF)
#define IMX_AITC_NIPNDH          (VA_AITC_BASE + NIPNDH_OFF)
#define IMX_AITC_NIPNDL          (VA_AITC_BASE + NIPNDL_OFF)
#define IMX_AITC_FIPNDH          (VA_AITC_BASE + FIPNDH_OFF)
#define IMX_AITC_FIPNDL          (VA_AITC_BASE + FIPNDL_OFF)

#if 0
#define DEBUG_IRQ(fmt...)	printk(fmt)
#else
#define DEBUG_IRQ(fmt...)	do { } while (0)
#endif

static void
imx_mask_irq(unsigned int irq)
{
	__raw_writel(irq, IMX_AITC_INTDISNUM);
}

static void
imx_unmask_irq(unsigned int irq)
{
	__raw_writel(irq, IMX_AITC_INTENNUM);
}

static int
imx_gpio_irq_type(unsigned int _irq, unsigned int type)
{
	unsigned int irq_type = 0, irq, reg, bit;

	irq = _irq - IRQ_GPIOA(0);
	reg = irq >> 5;
	bit = 1 << (irq % 32);

	if (type == IRQ_TYPE_PROBE) {
		/* Don't mess with enabled GPIOs using preconfigured edges or
		   GPIOs set to alternate function during probe */
		/* TODO: support probe */
//              if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
//                  GPIO_bit(gpio))
//                      return 0;
//              if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
//                      return 0;
//              type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	}

	GIUS(reg) |= bit;
	DDIR(reg) &= ~(bit);

	DEBUG_IRQ("setting type of irq %d to ", _irq);

	if (type & IRQ_TYPE_EDGE_RISING) {
		DEBUG_IRQ("rising edges\n");
		irq_type = 0x0;
	}
	if (type & IRQ_TYPE_EDGE_FALLING) {
		DEBUG_IRQ("falling edges\n");
		irq_type = 0x1;
	}
	if (type & IRQ_TYPE_LEVEL_LOW) {
		DEBUG_IRQ("low level\n");
		irq_type = 0x3;
	}
	if (type & IRQ_TYPE_LEVEL_HIGH) {
		DEBUG_IRQ("high level\n");
		irq_type = 0x2;
	}

	if (irq % 32 < 16) {
		ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) |
		    (irq_type << ((irq % 16) * 2));
	} else {
		ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) |
		    (irq_type << ((irq % 16) * 2));
	}

	return 0;

}

static void
imx_gpio_ack_irq(unsigned int irq)
{
	DEBUG_IRQ("%s: irq %d\n", __func__, irq);
	ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
}

static void
imx_gpio_mask_irq(unsigned int irq)
{
	DEBUG_IRQ("%s: irq %d\n", __func__, irq);
	IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
}

static void
imx_gpio_unmask_irq(unsigned int irq)
{
	DEBUG_IRQ("%s: irq %d\n", __func__, irq);
	IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
}

static void
imx_gpio_handler(unsigned int mask, unsigned int irq,
                 struct irq_desc *desc)
{
	desc = irq_desc + irq;
	while (mask) {
		if (mask & 1) {
			DEBUG_IRQ("handling irq %d\n", irq);
			desc_handle_irq(irq, desc);
		}
		irq++;
		desc++;
		mask >>= 1;
	}
}

static void
imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = ISR(0);
	irq = IRQ_GPIOA(0);
	imx_gpio_handler(mask, irq, desc);
}

static void
imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = ISR(1);
	irq = IRQ_GPIOB(0);
	imx_gpio_handler(mask, irq, desc);
}

static void
imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = ISR(2);
	irq = IRQ_GPIOC(0);
	imx_gpio_handler(mask, irq, desc);
}

static void
imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
	unsigned int mask, irq;

	mask = ISR(3);
	irq = IRQ_GPIOD(0);
	imx_gpio_handler(mask, irq, desc);
}

static struct irq_chip imx_internal_chip = {
	.name = "MPU",
	.ack = imx_mask_irq,
	.mask = imx_mask_irq,
	.unmask = imx_unmask_irq,
};

static struct irq_chip imx_gpio_chip = {
	.name = "GPIO",
	.ack = imx_gpio_ack_irq,
	.mask = imx_gpio_mask_irq,
	.unmask = imx_gpio_unmask_irq,
	.set_type = imx_gpio_irq_type,
};

void __init
imx_init_irq(void)
{
	unsigned int irq;

	DEBUG_IRQ("Initializing imx interrupts\n");

	/* Disable all interrupts initially. */
	/* Do not rely on the bootloader. */
	__raw_writel(0, IMX_AITC_INTENABLEH);
	__raw_writel(0, IMX_AITC_INTENABLEL);

	/* Mask all GPIO interrupts as well */
	IMR(0) = 0;
	IMR(1) = 0;
	IMR(2) = 0;
	IMR(3) = 0;

	for (irq = 0; irq < IMX_IRQS; irq++) {
		set_irq_chip(irq, &imx_internal_chip);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
		set_irq_chip(irq, &imx_gpio_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
	set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
	set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
	set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);

	/* Release masking of interrupts according to priority */
	__raw_writel(-1, IMX_AITC_NIMASK);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-imx/irq.c
	3	*
	4	* Copyright (C) 1999 ARM Limited
	5	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*
	21	* 03/03/2004 Sascha Hauer <sascha@saschahauer.de>
	22	* Copied from the motorola bsp package and added gpio demux
	23	* interrupt handler
	24	*/
	25
	26	#include <linux/init.h>
	27	#include <linux/list.h>
	28	#include <linux/timer.h>
fced80c7	29	#include <linux/io.h>
1da177e4	30
a09e64fb	31	#include <mach/hardware.h>
1da177e4	32	#include <asm/irq.h>
1da177e4 LT	33
	34	#include <asm/mach/irq.h>
	35
	36	/*
	37	*
	38	* We simply use the ENABLE DISABLE registers inside of the IMX
	39	* to turn on/off specific interrupts. FIXME- We should
	40	* also add support for the accelerated interrupt controller
	41	* by putting offets to irq jump code in the appropriate
	42	* places.
	43	*
	44	*/
	45
1c016b2c PP	46	#define INTCNTL_OFF 0x00
	47	#define NIMASK_OFF 0x04
	48	#define INTENNUM_OFF 0x08
	49	#define INTDISNUM_OFF 0x0C
	50	#define INTENABLEH_OFF 0x10
	51	#define INTENABLEL_OFF 0x14
	52	#define INTTYPEH_OFF 0x18
	53	#define INTTYPEL_OFF 0x1C
	54	#define NIPRIORITY_OFF(x) (0x20+4*(7-(x)))
	55	#define NIVECSR_OFF 0x40
	56	#define FIVECSR_OFF 0x44
	57	#define INTSRCH_OFF 0x48
	58	#define INTSRCL_OFF 0x4C
	59	#define INTFRCH_OFF 0x50
	60	#define INTFRCL_OFF 0x54
	61	#define NIPNDH_OFF 0x58
	62	#define NIPNDL_OFF 0x5C
	63	#define FIPNDH_OFF 0x60
	64	#define FIPNDL_OFF 0x64
1da177e4 LT	65
1da177e4 LT	66	#define VA_AITC_BASE IO_ADDRESS(IMX_AITC_BASE)
1c016b2c PP	67	#define IMX_AITC_INTCNTL (VA_AITC_BASE + INTCNTL_OFF)
1c016b2c PP	68	#define IMX_AITC_NIMASK (VA_AITC_BASE + NIMASK_OFF)
1da177e4	69	#define IMX_AITC_INTENNUM (VA_AITC_BASE + INTENNUM_OFF)
1c016b2c PP	70	#define IMX_AITC_INTDISNUM (VA_AITC_BASE + INTDISNUM_OFF)
	71	#define IMX_AITC_INTENABLEH (VA_AITC_BASE + INTENABLEH_OFF)
	72	#define IMX_AITC_INTENABLEL (VA_AITC_BASE + INTENABLEL_OFF)
	73	#define IMX_AITC_INTTYPEH (VA_AITC_BASE + INTTYPEH_OFF)
	74	#define IMX_AITC_INTTYPEL (VA_AITC_BASE + INTTYPEL_OFF)
	75	#define IMX_AITC_NIPRIORITY(x) (VA_AITC_BASE + NIPRIORITY_OFF(x))
	76	#define IMX_AITC_NIVECSR (VA_AITC_BASE + NIVECSR_OFF)
	77	#define IMX_AITC_FIVECSR (VA_AITC_BASE + FIVECSR_OFF)
	78	#define IMX_AITC_INTSRCH (VA_AITC_BASE + INTSRCH_OFF)
	79	#define IMX_AITC_INTSRCL (VA_AITC_BASE + INTSRCL_OFF)
	80	#define IMX_AITC_INTFRCH (VA_AITC_BASE + INTFRCH_OFF)
	81	#define IMX_AITC_INTFRCL (VA_AITC_BASE + INTFRCL_OFF)
	82	#define IMX_AITC_NIPNDH (VA_AITC_BASE + NIPNDH_OFF)
	83	#define IMX_AITC_NIPNDL (VA_AITC_BASE + NIPNDL_OFF)
	84	#define IMX_AITC_FIPNDH (VA_AITC_BASE + FIPNDH_OFF)
	85	#define IMX_AITC_FIPNDL (VA_AITC_BASE + FIPNDL_OFF)
1da177e4 LT	86
	87	#if 0
	88	#define DEBUG_IRQ(fmt...) printk(fmt)
	89	#else
	90	#define DEBUG_IRQ(fmt...) do { } while (0)
	91	#endif
	92
	93	static void
	94	imx_mask_irq(unsigned int irq)
	95	{
	96	__raw_writel(irq, IMX_AITC_INTDISNUM);
	97	}
	98
	99	static void
	100	imx_unmask_irq(unsigned int irq)
	101	{
	102	__raw_writel(irq, IMX_AITC_INTENNUM);
	103	}
	104
	105	static int
	106	imx_gpio_irq_type(unsigned int _irq, unsigned int type)
	107	{
	108	unsigned int irq_type = 0, irq, reg, bit;
	109
	110	irq = _irq - IRQ_GPIOA(0);
	111	reg = irq >> 5;
	112	bit = 1 << (irq % 32);
	113
6cab4860	114	if (type == IRQ_TYPE_PROBE) {
1da177e4 LT	115	/* Don't mess with enabled GPIOs using preconfigured edges or
	116	GPIOs set to alternate function during probe */
	117	/* TODO: support probe */
	118	// if ((GPIO_IRQ_rising_edge[idx] \| GPIO_IRQ_falling_edge[idx]) &
	119	// GPIO_bit(gpio))
	120	// return 0;
	121	// if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
	122	// return 0;
6cab4860	123	// type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
1da177e4 LT	124	}
	125
	126	GIUS(reg) \|= bit;
	127	DDIR(reg) &= ~(bit);
	128
	129	DEBUG_IRQ("setting type of irq %d to ", _irq);
	130
6cab4860	131	if (type & IRQ_TYPE_EDGE_RISING) {
1da177e4 LT	132	DEBUG_IRQ("rising edges\n");
	133	irq_type = 0x0;
	134	}
6cab4860	135	if (type & IRQ_TYPE_EDGE_FALLING) {
1da177e4 LT	136	DEBUG_IRQ("falling edges\n");
	137	irq_type = 0x1;
	138	}
6cab4860	139	if (type & IRQ_TYPE_LEVEL_LOW) {
1da177e4 LT	140	DEBUG_IRQ("low level\n");
	141	irq_type = 0x3;
	142	}
6cab4860	143	if (type & IRQ_TYPE_LEVEL_HIGH) {
1da177e4 LT	144	DEBUG_IRQ("high level\n");
	145	irq_type = 0x2;
	146	}
	147
	148	if (irq % 32 < 16) {
	149	ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) \|
	150	(irq_type << ((irq % 16) * 2));
	151	} else {
	152	ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) \|
	153	(irq_type << ((irq % 16) * 2));
	154	}
	155
	156	return 0;
	157
	158	}
	159
	160	static void
	161	imx_gpio_ack_irq(unsigned int irq)
	162	{
8e86f427	163	DEBUG_IRQ("%s: irq %d\n", __func__, irq);
e2f04e18	164	ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
1da177e4 LT	165	}
	166
	167	static void
	168	imx_gpio_mask_irq(unsigned int irq)
	169	{
8e86f427	170	DEBUG_IRQ("%s: irq %d\n", __func__, irq);
1da177e4 LT	171	IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
	172	}
	173
	174	static void
	175	imx_gpio_unmask_irq(unsigned int irq)
	176	{
8e86f427	177	DEBUG_IRQ("%s: irq %d\n", __func__, irq);
1da177e4 LT	178	IMR(IRQ_TO_REG(irq)) \|= 1 << ((irq - IRQ_GPIOA(0)) % 32);
	179	}
	180
	181	static void
	182	imx_gpio_handler(unsigned int mask, unsigned int irq,
10dd5ce2	183	struct irq_desc *desc)
1da177e4 LT	184	{
	185	desc = irq_desc + irq;
	186	while (mask) {
	187	if (mask & 1) {
	188	DEBUG_IRQ("handling irq %d\n", irq);
0cd61b68	189	desc_handle_irq(irq, desc);
1da177e4 LT	190	}
	191	irq++;
	192	desc++;
	193	mask >>= 1;
	194	}
	195	}
	196
	197	static void
10dd5ce2	198	imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	199	{
	200	unsigned int mask, irq;
	201
	202	mask = ISR(0);
	203	irq = IRQ_GPIOA(0);
0cd61b68	204	imx_gpio_handler(mask, irq, desc);
1da177e4 LT	205	}
	206
	207	static void
10dd5ce2	208	imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	209	{
	210	unsigned int mask, irq;
	211
	212	mask = ISR(1);
	213	irq = IRQ_GPIOB(0);
0cd61b68	214	imx_gpio_handler(mask, irq, desc);
1da177e4 LT	215	}
	216
	217	static void
10dd5ce2	218	imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	219	{
	220	unsigned int mask, irq;
	221
	222	mask = ISR(2);
	223	irq = IRQ_GPIOC(0);
0cd61b68	224	imx_gpio_handler(mask, irq, desc);
1da177e4 LT	225	}
	226
	227	static void
10dd5ce2	228	imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
1da177e4 LT	229	{
	230	unsigned int mask, irq;
	231
	232	mask = ISR(3);
	233	irq = IRQ_GPIOD(0);
0cd61b68	234	imx_gpio_handler(mask, irq, desc);
1da177e4 LT	235	}
1da177e4 LT	236
38c677cb DB	237	static struct irq_chip imx_internal_chip = {
38c677cb DB	238	.name = "MPU",
1da177e4 LT	239	.ack = imx_mask_irq,
	240	.mask = imx_mask_irq,
	241	.unmask = imx_unmask_irq,
	242	};
	243
38c677cb DB	244	static struct irq_chip imx_gpio_chip = {
38c677cb DB	245	.name = "GPIO",
1da177e4 LT	246	.ack = imx_gpio_ack_irq,
	247	.mask = imx_gpio_mask_irq,
	248	.unmask = imx_gpio_unmask_irq,
7801907b	249	.set_type = imx_gpio_irq_type,
1da177e4 LT	250	};
	251
	252	void __init
	253	imx_init_irq(void)
	254	{
	255	unsigned int irq;
	256
	257	DEBUG_IRQ("Initializing imx interrupts\n");
	258
1c016b2c PP	259	/* Disable all interrupts initially. */
	260	/* Do not rely on the bootloader. */
	261	__raw_writel(0, IMX_AITC_INTENABLEH);
	262	__raw_writel(0, IMX_AITC_INTENABLEL);
	263
	264	/* Mask all GPIO interrupts as well */
1da177e4 LT	265	IMR(0) = 0;
	266	IMR(1) = 0;
	267	IMR(2) = 0;
	268	IMR(3) = 0;
	269
	270	for (irq = 0; irq < IMX_IRQS; irq++) {
	271	set_irq_chip(irq, &imx_internal_chip);
10dd5ce2	272	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	273	set_irq_flags(irq, IRQF_VALID);
	274	}
	275
	276	for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
	277	set_irq_chip(irq, &imx_gpio_chip);
10dd5ce2	278	set_irq_handler(irq, handle_edge_irq);
1da177e4 LT	279	set_irq_flags(irq, IRQF_VALID);
	280	}
	281
	282	set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
	283	set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
	284	set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
	285	set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);
	286
1c016b2c PP	287	/* Release masking of interrupts according to priority */
1c016b2c PP	288	__raw_writel(-1, IMX_AITC_NIMASK);
1da177e4	289	}