[thirdparty/linux.git] / arch / arm / mach-imx / mach-mx51_babbage.c

/*
 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/input.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>

#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>

#include "common.h"
#include "devices-imx51.h"
#include "cpu_op-mx51.h"
#include "hardware.h"
#include "iomux-mx51.h"

#define BABBAGE_USB_HUB_RESET	IMX_GPIO_NR(1, 7)
#define BABBAGE_USBH1_STP	IMX_GPIO_NR(1, 27)
#define BABBAGE_USB_PHY_RESET	IMX_GPIO_NR(2, 5)
#define BABBAGE_FEC_PHY_RESET	IMX_GPIO_NR(2, 14)
#define BABBAGE_POWER_KEY	IMX_GPIO_NR(2, 21)
#define BABBAGE_ECSPI1_CS0	IMX_GPIO_NR(4, 24)
#define BABBAGE_ECSPI1_CS1	IMX_GPIO_NR(4, 25)
#define BABBAGE_SD2_CD		IMX_GPIO_NR(1, 6)
#define BABBAGE_SD2_WP		IMX_GPIO_NR(1, 5)

/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET			0x10
#define MX51_USB_CTRL_UH1_EXT_CLK_EN		(1 << 25)

#define	MX51_USB_PLLDIV_12_MHZ		0x00
#define	MX51_USB_PLL_DIV_19_2_MHZ	0x01
#define	MX51_USB_PLL_DIV_24_MHZ	0x02

static struct gpio_keys_button babbage_buttons[] = {
	{
		.gpio		= BABBAGE_POWER_KEY,
		.code		= BTN_0,
		.desc		= "PWR",
		.active_low	= 1,
		.wakeup		= 1,
	},
};

static const struct gpio_keys_platform_data imx_button_data __initconst = {
	.buttons	= babbage_buttons,
	.nbuttons	= ARRAY_SIZE(babbage_buttons),
};

static iomux_v3_cfg_t mx51babbage_pads[] = {
	/* UART1 */
	MX51_PAD_UART1_RXD__UART1_RXD,
	MX51_PAD_UART1_TXD__UART1_TXD,
	MX51_PAD_UART1_RTS__UART1_RTS,
	MX51_PAD_UART1_CTS__UART1_CTS,

	/* UART2 */
	MX51_PAD_UART2_RXD__UART2_RXD,
	MX51_PAD_UART2_TXD__UART2_TXD,

	/* UART3 */
	MX51_PAD_EIM_D25__UART3_RXD,
	MX51_PAD_EIM_D26__UART3_TXD,
	MX51_PAD_EIM_D27__UART3_RTS,
	MX51_PAD_EIM_D24__UART3_CTS,

	/* I2C1 */
	MX51_PAD_EIM_D16__I2C1_SDA,
	MX51_PAD_EIM_D19__I2C1_SCL,

	/* I2C2 */
	MX51_PAD_KEY_COL4__I2C2_SCL,
	MX51_PAD_KEY_COL5__I2C2_SDA,

	/* HSI2C */
	MX51_PAD_I2C1_CLK__I2C1_CLK,
	MX51_PAD_I2C1_DAT__I2C1_DAT,

	/* USB HOST1 */
	MX51_PAD_USBH1_CLK__USBH1_CLK,
	MX51_PAD_USBH1_DIR__USBH1_DIR,
	MX51_PAD_USBH1_NXT__USBH1_NXT,
	MX51_PAD_USBH1_DATA0__USBH1_DATA0,
	MX51_PAD_USBH1_DATA1__USBH1_DATA1,
	MX51_PAD_USBH1_DATA2__USBH1_DATA2,
	MX51_PAD_USBH1_DATA3__USBH1_DATA3,
	MX51_PAD_USBH1_DATA4__USBH1_DATA4,
	MX51_PAD_USBH1_DATA5__USBH1_DATA5,
	MX51_PAD_USBH1_DATA6__USBH1_DATA6,
	MX51_PAD_USBH1_DATA7__USBH1_DATA7,

	/* USB HUB reset line*/
	MX51_PAD_GPIO1_7__GPIO1_7,

	/* USB PHY reset line */
	MX51_PAD_EIM_D21__GPIO2_5,

	/* FEC */
	MX51_PAD_EIM_EB2__FEC_MDIO,
	MX51_PAD_EIM_EB3__FEC_RDATA1,
	MX51_PAD_EIM_CS2__FEC_RDATA2,
	MX51_PAD_EIM_CS3__FEC_RDATA3,
	MX51_PAD_EIM_CS4__FEC_RX_ER,
	MX51_PAD_EIM_CS5__FEC_CRS,
	MX51_PAD_NANDF_RB2__FEC_COL,
	MX51_PAD_NANDF_RB3__FEC_RX_CLK,
	MX51_PAD_NANDF_D9__FEC_RDATA0,
	MX51_PAD_NANDF_D8__FEC_TDATA0,
	MX51_PAD_NANDF_CS2__FEC_TX_ER,
	MX51_PAD_NANDF_CS3__FEC_MDC,
	MX51_PAD_NANDF_CS4__FEC_TDATA1,
	MX51_PAD_NANDF_CS5__FEC_TDATA2,
	MX51_PAD_NANDF_CS6__FEC_TDATA3,
	MX51_PAD_NANDF_CS7__FEC_TX_EN,
	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,

	/* FEC PHY reset line */
	MX51_PAD_EIM_A20__GPIO2_14,

	/* SD 1 */
	MX51_PAD_SD1_CMD__SD1_CMD,
	MX51_PAD_SD1_CLK__SD1_CLK,
	MX51_PAD_SD1_DATA0__SD1_DATA0,
	MX51_PAD_SD1_DATA1__SD1_DATA1,
	MX51_PAD_SD1_DATA2__SD1_DATA2,
	MX51_PAD_SD1_DATA3__SD1_DATA3,
	/* CD/WP from controller */
	MX51_PAD_GPIO1_0__SD1_CD,
	MX51_PAD_GPIO1_1__SD1_WP,

	/* SD 2 */
	MX51_PAD_SD2_CMD__SD2_CMD,
	MX51_PAD_SD2_CLK__SD2_CLK,
	MX51_PAD_SD2_DATA0__SD2_DATA0,
	MX51_PAD_SD2_DATA1__SD2_DATA1,
	MX51_PAD_SD2_DATA2__SD2_DATA2,
	MX51_PAD_SD2_DATA3__SD2_DATA3,
	/* CD/WP gpio */
	MX51_PAD_GPIO1_6__GPIO1_6,
	MX51_PAD_GPIO1_5__GPIO1_5,

	/* eCSPI1 */
	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
	MX51_PAD_CSPI1_SS0__GPIO4_24,
	MX51_PAD_CSPI1_SS1__GPIO4_25,

	/* Audio */
	MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
	MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
	MX51_PAD_AUD3_BB_CK__AUD3_TXC,
	MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
};

/* Serial ports */
static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
	.bitrate = 100000,
};

static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
	.bitrate = 400000,
};

static struct gpio mx51_babbage_usbh1_gpios[] = {
	{ BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
	{ BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
};

static int gpio_usbh1_active(void)
{
	iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
	int ret;

	/* Set USBH1_STP to GPIO and toggle it */
	mxc_iomux_v3_setup_pad(usbh1stp_gpio);
	ret = gpio_request_array(mx51_babbage_usbh1_gpios,
					ARRAY_SIZE(mx51_babbage_usbh1_gpios));

	if (ret) {
		pr_debug("failed to get USBH1 pins: %d\n", ret);
		return ret;
	}

	msleep(100);
	gpio_set_value(BABBAGE_USBH1_STP, 1);
	gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
	gpio_free_array(mx51_babbage_usbh1_gpios,
					ARRAY_SIZE(mx51_babbage_usbh1_gpios));
	return 0;
}

static inline void babbage_usbhub_reset(void)
{
	int ret;

	/* Reset USB hub */
	ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
					GPIOF_OUT_INIT_LOW, "GPIO1_7");
	if (ret) {
		printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
		return;
	}

	msleep(2);
	/* Deassert reset */
	gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
}

static inline void babbage_fec_reset(void)
{
	int ret;

	/* reset FEC PHY */
	ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
					GPIOF_OUT_INIT_LOW, "fec-phy-reset");
	if (ret) {
		printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
		return;
	}
	msleep(1);
	gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
}

/* This function is board specific as the bit mask for the plldiv will also
be different for other Freescale SoCs, thus a common bitmask is not
possible and cannot get place in /plat-mxc/ehci.c.*/
static int initialize_otg_port(struct platform_device *pdev)
{
	u32 v;
	void __iomem *usb_base;
	void __iomem *usbother_base;

	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
	if (!usb_base)
		return -ENOMEM;
	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

	/* Set the PHY clock to 19.2MHz */
	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
	v |= MX51_USB_PLL_DIV_19_2_MHZ;
	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	iounmap(usb_base);

	mdelay(10);

	return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
}

static int initialize_usbh1_port(struct platform_device *pdev)
{
	u32 v;
	void __iomem *usb_base;
	void __iomem *usbother_base;

	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
	if (!usb_base)
		return -ENOMEM;
	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

	/* The clock for the USBH1 ULPI port will come externally from the PHY. */
	v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
	__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
	iounmap(usb_base);

	mdelay(10);

	return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
			MXC_EHCI_ITC_NO_THRESHOLD);
}

static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
	.init		= initialize_otg_port,
	.portsc	= MXC_EHCI_UTMI_16BIT,
};

static const struct fsl_usb2_platform_data usb_pdata __initconst = {
	.operating_mode	= FSL_USB2_DR_DEVICE,
	.phy_mode	= FSL_USB2_PHY_UTMI_WIDE,
};

static const struct mxc_usbh_platform_data usbh1_config __initconst = {
	.init		= initialize_usbh1_port,
	.portsc	= MXC_EHCI_MODE_ULPI,
};

static bool otg_mode_host __initdata;

static int __init babbage_otg_mode(char *options)
{
	if (!strcmp(options, "host"))
		otg_mode_host = true;
	else if (!strcmp(options, "device"))
		otg_mode_host = false;
	else
		pr_info("otg_mode neither \"host\" nor \"device\". "
			"Defaulting to device\n");
	return 1;
}
__setup("otg_mode=", babbage_otg_mode);

static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
	{
		.modalias = "mtd_dataflash",
		.max_speed_hz = 25000000,
		.bus_num = 0,
		.chip_select = 1,
		.mode = SPI_MODE_0,
		.platform_data = NULL,
	},
};

static int mx51_babbage_spi_cs[] = {
	BABBAGE_ECSPI1_CS0,
	BABBAGE_ECSPI1_CS1,
};

static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
	.chipselect     = mx51_babbage_spi_cs,
	.num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
};

static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
	.cd_type = ESDHC_CD_CONTROLLER,
	.wp_type = ESDHC_WP_CONTROLLER,
};

static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
	.cd_gpio = BABBAGE_SD2_CD,
	.wp_gpio = BABBAGE_SD2_WP,
	.cd_type = ESDHC_CD_GPIO,
	.wp_type = ESDHC_WP_GPIO,
};

void __init imx51_babbage_common_init(void)
{
	mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
					 ARRAY_SIZE(mx51babbage_pads));
}

/*
 * Board specific initialization.
 */
static void __init mx51_babbage_init(void)
{
	iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
	iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
		PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH);

	imx51_soc_init();

#if defined(CONFIG_CPU_FREQ_IMX)
	get_cpu_op = mx51_get_cpu_op;
#endif
	imx51_babbage_common_init();

	imx51_add_imx_uart(0, &uart_pdata);
	imx51_add_imx_uart(1, NULL);
	imx51_add_imx_uart(2, &uart_pdata);

	babbage_fec_reset();
	imx51_add_fec(NULL);

	/* Set the PAD settings for the pwr key. */
	mxc_iomux_v3_setup_pad(power_key);
	imx_add_gpio_keys(&imx_button_data);

	imx51_add_imx_i2c(0, &babbage_i2c_data);
	imx51_add_imx_i2c(1, &babbage_i2c_data);
	imx51_add_hsi2c(&babbage_hsi2c_data);

	if (otg_mode_host)
		imx51_add_mxc_ehci_otg(&dr_utmi_config);
	else {
		initialize_otg_port(NULL);
		imx51_add_fsl_usb2_udc(&usb_pdata);
	}

	gpio_usbh1_active();
	imx51_add_mxc_ehci_hs(1, &usbh1_config);
	/* setback USBH1_STP to be function */
	mxc_iomux_v3_setup_pad(usbh1stp);
	babbage_usbhub_reset();

	imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
	imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);

	spi_register_board_info(mx51_babbage_spi_board_info,
		ARRAY_SIZE(mx51_babbage_spi_board_info));
	imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
	imx51_add_imx2_wdt(0);
}

static void __init mx51_babbage_timer_init(void)
{
	mx51_clocks_init(32768, 24000000, 22579200, 0);
}

MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
	/* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
	.atag_offset = 0x100,
	.map_io = mx51_map_io,
	.init_early = imx51_init_early,
	.init_irq = mx51_init_irq,
	.handle_irq = imx51_handle_irq,
	.init_time	= mx51_babbage_timer_init,
	.init_machine = mx51_babbage_init,
	.init_late	= imx51_init_late,
	.restart	= mxc_restart,
MACHINE_END
Commit	Line	Data
b996b583	1	/*
64f102b6	2	* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
b996b583 AK	3	* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
	4	*
	5	* The code contained herein is licensed under the GNU General Public
	6	* License. You may obtain a copy of the GNU General Public License
	7	* Version 2 or later at the following locations:
	8	*
	9	* http://www.opensource.org/licenses/gpl-license.html
	10	* http://www.gnu.org/copyleft/gpl.html
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/platform_device.h>
f00b771a	15	#include <linux/i2c.h>
231637f5 DN	16	#include <linux/gpio.h>
	17	#include <linux/delay.h>
	18	#include <linux/io.h>
f2d36ecb	19	#include <linux/input.h>
374daa4f FE	20	#include <linux/spi/flash.h>
374daa4f FE	21	#include <linux/spi/spi.h>
b996b583	22
b996b583 AK	23	#include <asm/setup.h>
	24	#include <asm/mach-types.h>
	25	#include <asm/mach/arch.h>
	26	#include <asm/mach/time.h>
	27
e3372474	28	#include "common.h"
04b73b15	29	#include "devices-imx51.h"
64f102b6	30	#include "cpu_op-mx51.h"
50f2de61	31	#include "hardware.h"
267dd34c	32	#include "iomux-mx51.h"
b996b583	33
96886c43 AP	34	#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
96886c43 AP	35	#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
2e7b1bfc	36	#define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5)
96886c43 AP	37	#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
	38	#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
	39	#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
	40	#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
6ecdc11b AS	41	#define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6)
6ecdc11b AS	42	#define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5)
231637f5 DN	43
	44	/* USB_CTRL_1 */
	45	#define MX51_USB_CTRL_1_OFFSET 0x10
	46	#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
	47
	48	#define MX51_USB_PLLDIV_12_MHZ 0x00
	49	#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
	50	#define MX51_USB_PLL_DIV_24_MHZ 0x02
	51
f2d36ecb DN	52	static struct gpio_keys_button babbage_buttons[] = {
	53	{
	54	.gpio = BABBAGE_POWER_KEY,
	55	.code = BTN_0,
	56	.desc = "PWR",
	57	.active_low = 1,
	58	.wakeup = 1,
	59	},
	60	};
	61
	62	static const struct gpio_keys_platform_data imx_button_data __initconst = {
	63	.buttons = babbage_buttons,
	64	.nbuttons = ARRAY_SIZE(babbage_buttons),
	65	};
	66
8f5260c8	67	static iomux_v3_cfg_t mx51babbage_pads[] = {
b996b583 AK	68	/* UART1 */
	69	MX51_PAD_UART1_RXD__UART1_RXD,
	70	MX51_PAD_UART1_TXD__UART1_TXD,
	71	MX51_PAD_UART1_RTS__UART1_RTS,
	72	MX51_PAD_UART1_CTS__UART1_CTS,
	73
	74	/* UART2 */
	75	MX51_PAD_UART2_RXD__UART2_RXD,
	76	MX51_PAD_UART2_TXD__UART2_TXD,
	77
	78	/* UART3 */
	79	MX51_PAD_EIM_D25__UART3_RXD,
	80	MX51_PAD_EIM_D26__UART3_TXD,
	81	MX51_PAD_EIM_D27__UART3_RTS,
	82	MX51_PAD_EIM_D24__UART3_CTS,
231637f5	83
f00b771a DN	84	/* I2C1 */
	85	MX51_PAD_EIM_D16__I2C1_SDA,
	86	MX51_PAD_EIM_D19__I2C1_SCL,
	87
	88	/* I2C2 */
	89	MX51_PAD_KEY_COL4__I2C2_SCL,
	90	MX51_PAD_KEY_COL5__I2C2_SDA,
	91
	92	/* HSI2C */
ee1ae4d7 SH	93	MX51_PAD_I2C1_CLK__I2C1_CLK,
ee1ae4d7 SH	94	MX51_PAD_I2C1_DAT__I2C1_DAT,
f00b771a	95
231637f5 DN	96	/* USB HOST1 */
	97	MX51_PAD_USBH1_CLK__USBH1_CLK,
	98	MX51_PAD_USBH1_DIR__USBH1_DIR,
	99	MX51_PAD_USBH1_NXT__USBH1_NXT,
	100	MX51_PAD_USBH1_DATA0__USBH1_DATA0,
	101	MX51_PAD_USBH1_DATA1__USBH1_DATA1,
	102	MX51_PAD_USBH1_DATA2__USBH1_DATA2,
	103	MX51_PAD_USBH1_DATA3__USBH1_DATA3,
	104	MX51_PAD_USBH1_DATA4__USBH1_DATA4,
	105	MX51_PAD_USBH1_DATA5__USBH1_DATA5,
	106	MX51_PAD_USBH1_DATA6__USBH1_DATA6,
	107	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
	108
	109	/* USB HUB reset line*/
ee1ae4d7	110	MX51_PAD_GPIO1_7__GPIO1_7,
3efee47d	111
2e7b1bfc FE	112	/* USB PHY reset line */
	113	MX51_PAD_EIM_D21__GPIO2_5,
	114
3efee47d FE	115	/* FEC */
3efee47d FE	116	MX51_PAD_EIM_EB2__FEC_MDIO,
ee1ae4d7 SH	117	MX51_PAD_EIM_EB3__FEC_RDATA1,
	118	MX51_PAD_EIM_CS2__FEC_RDATA2,
	119	MX51_PAD_EIM_CS3__FEC_RDATA3,
3efee47d FE	120	MX51_PAD_EIM_CS4__FEC_RX_ER,
	121	MX51_PAD_EIM_CS5__FEC_CRS,
	122	MX51_PAD_NANDF_RB2__FEC_COL,
ee1ae4d7 SH	123	MX51_PAD_NANDF_RB3__FEC_RX_CLK,
	124	MX51_PAD_NANDF_D9__FEC_RDATA0,
	125	MX51_PAD_NANDF_D8__FEC_TDATA0,
3efee47d FE	126	MX51_PAD_NANDF_CS2__FEC_TX_ER,
3efee47d FE	127	MX51_PAD_NANDF_CS3__FEC_MDC,
ee1ae4d7 SH	128	MX51_PAD_NANDF_CS4__FEC_TDATA1,
	129	MX51_PAD_NANDF_CS5__FEC_TDATA2,
	130	MX51_PAD_NANDF_CS6__FEC_TDATA3,
3efee47d FE	131	MX51_PAD_NANDF_CS7__FEC_TX_EN,
	132	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
	133
	134	/* FEC PHY reset line */
ee1ae4d7	135	MX51_PAD_EIM_A20__GPIO2_14,
7223066c SG	136
	137	/* SD 1 */
	138	MX51_PAD_SD1_CMD__SD1_CMD,
	139	MX51_PAD_SD1_CLK__SD1_CLK,
	140	MX51_PAD_SD1_DATA0__SD1_DATA0,
	141	MX51_PAD_SD1_DATA1__SD1_DATA1,
	142	MX51_PAD_SD1_DATA2__SD1_DATA2,
	143	MX51_PAD_SD1_DATA3__SD1_DATA3,
913413c3 SG	144	/* CD/WP from controller */
	145	MX51_PAD_GPIO1_0__SD1_CD,
	146	MX51_PAD_GPIO1_1__SD1_WP,
7223066c SG	147
	148	/* SD 2 */
	149	MX51_PAD_SD2_CMD__SD2_CMD,
	150	MX51_PAD_SD2_CLK__SD2_CLK,
	151	MX51_PAD_SD2_DATA0__SD2_DATA0,
	152	MX51_PAD_SD2_DATA1__SD2_DATA1,
	153	MX51_PAD_SD2_DATA2__SD2_DATA2,
	154	MX51_PAD_SD2_DATA3__SD2_DATA3,
913413c3	155	/* CD/WP gpio */
6ecdc11b AS	156	MX51_PAD_GPIO1_6__GPIO1_6,
6ecdc11b AS	157	MX51_PAD_GPIO1_5__GPIO1_5,
374daa4f FE	158
	159	/* eCSPI1 */
	160	MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
	161	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
	162	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
ee1ae4d7 SH	163	MX51_PAD_CSPI1_SS0__GPIO4_24,
ee1ae4d7 SH	164	MX51_PAD_CSPI1_SS1__GPIO4_25,
bf22e530 SG	165
	166	/* Audio */
	167	MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
	168	MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
	169	MX51_PAD_AUD3_BB_CK__AUD3_TXC,
	170	MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
b996b583 AK	171	};
	172
	173	/* Serial ports */
04b73b15	174	static const struct imxuart_platform_data uart_pdata __initconst = {
b996b583 AK	175	.flags = IMXUART_HAVE_RTSCTS,
	176	};
	177
44505c07	178	static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
f00b771a DN	179	.bitrate = 100000,
	180	};
	181
f2688854	182	static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
f00b771a DN	183	.bitrate = 400000,
	184	};
	185
72370a5c FE	186	static struct gpio mx51_babbage_usbh1_gpios[] = {
	187	{ BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
	188	{ BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
	189	};
	190
231637f5 DN	191	static int gpio_usbh1_active(void)
231637f5 DN	192	{
ee1ae4d7	193	iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
231637f5 DN	194	int ret;
	195
	196	/* Set USBH1_STP to GPIO and toggle it */
96f3e256	197	mxc_iomux_v3_setup_pad(usbh1stp_gpio);
72370a5c FE	198	ret = gpio_request_array(mx51_babbage_usbh1_gpios,
72370a5c FE	199	ARRAY_SIZE(mx51_babbage_usbh1_gpios));
231637f5 DN	200
231637f5 DN	201	if (ret) {
72370a5c	202	pr_debug("failed to get USBH1 pins: %d\n", ret);
231637f5 DN	203	return ret;
231637f5 DN	204	}
d6b273bf	205
72370a5c FE	206	msleep(100);
	207	gpio_set_value(BABBAGE_USBH1_STP, 1);
	208	gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
	209	gpio_free_array(mx51_babbage_usbh1_gpios,
	210	ARRAY_SIZE(mx51_babbage_usbh1_gpios));
231637f5 DN	211	return 0;
	212	}
	213
	214	static inline void babbage_usbhub_reset(void)
	215	{
	216	int ret;
	217
6f9ec442 FE	218	/* Reset USB hub */
	219	ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
	220	GPIOF_OUT_INIT_LOW, "GPIO1_7");
231637f5 DN	221	if (ret) {
	222	printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
	223	return;
	224	}
231637f5	225
6f9ec442 FE	226	msleep(2);
6f9ec442 FE	227	/* Deassert reset */
231637f5 DN	228	gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
	229	}
	230
3efee47d FE	231	static inline void babbage_fec_reset(void)
	232	{
	233	int ret;
	234
	235	/* reset FEC PHY */
ce191e41 FE	236	ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
ce191e41 FE	237	GPIOF_OUT_INIT_LOW, "fec-phy-reset");
3efee47d FE	238	if (ret) {
	239	printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
	240	return;
	241	}
3efee47d FE	242	msleep(1);
	243	gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
	244	}
	245
231637f5 DN	246	/* This function is board specific as the bit mask for the plldiv will also
	247	be different for other Freescale SoCs, thus a common bitmask is not
	248	possible and cannot get place in /plat-mxc/ehci.c.*/
	249	static int initialize_otg_port(struct platform_device *pdev)
	250	{
	251	u32 v;
	252	void __iomem *usb_base;
e7a895bf	253	void __iomem *usbother_base;
231637f5	254
7d92e8e6	255	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
28a4f908 FE	256	if (!usb_base)
28a4f908 FE	257	return -ENOMEM;
231637f5 DN	258	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	259
	260	/* Set the PHY clock to 19.2MHz */
	261	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	262	v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
	263	v \|= MX51_USB_PLL_DIV_19_2_MHZ;
	264	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	265	iounmap(usb_base);
4bd597b6 SH	266
	267	mdelay(10);
	268
	269	return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
231637f5 DN	270	}
	271
	272	static int initialize_usbh1_port(struct platform_device *pdev)
	273	{
	274	u32 v;
	275	void __iomem *usb_base;
e7a895bf	276	void __iomem *usbother_base;
231637f5	277
7d92e8e6	278	usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
28a4f908 FE	279	if (!usb_base)
28a4f908 FE	280	return -ENOMEM;
231637f5 DN	281	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	282
	283	/* The clock for the USBH1 ULPI port will come externally from the PHY. */
	284	v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
	285	__raw_writel(v \| MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
	286	iounmap(usb_base);
4bd597b6 SH	287
	288	mdelay(10);
	289
	290	return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED \|
	291	MXC_EHCI_ITC_NO_THRESHOLD);
231637f5 DN	292	}
231637f5 DN	293
7d92e8e6	294	static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
231637f5 DN	295	.init = initialize_otg_port,
231637f5 DN	296	.portsc = MXC_EHCI_UTMI_16BIT,
231637f5 DN	297	};
231637f5 DN	298
6cafe48a	299	static const struct fsl_usb2_platform_data usb_pdata __initconst = {
2ba5a2c0 DN	300	.operating_mode = FSL_USB2_DR_DEVICE,
	301	.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
	302	};
	303
7d92e8e6	304	static const struct mxc_usbh_platform_data usbh1_config __initconst = {
231637f5 DN	305	.init = initialize_usbh1_port,
231637f5 DN	306	.portsc = MXC_EHCI_MODE_ULPI,
231637f5 DN	307	};
231637f5 DN	308
33a264dd	309	static bool otg_mode_host __initdata;
2ba5a2c0 DN	310
	311	static int __init babbage_otg_mode(char *options)
	312	{
	313	if (!strcmp(options, "host"))
33a264dd	314	otg_mode_host = true;
2ba5a2c0	315	else if (!strcmp(options, "device"))
33a264dd	316	otg_mode_host = false;
2ba5a2c0 DN	317	else
	318	pr_info("otg_mode neither \"host\" nor \"device\". "
	319	"Defaulting to device\n");
33a264dd	320	return 1;
2ba5a2c0 DN	321	}
	322	__setup("otg_mode=", babbage_otg_mode);
	323
374daa4f FE	324	static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
	325	{
	326	.modalias = "mtd_dataflash",
	327	.max_speed_hz = 25000000,
	328	.bus_num = 0,
	329	.chip_select = 1,
	330	.mode = SPI_MODE_0,
	331	.platform_data = NULL,
	332	},
	333	};
	334
	335	static int mx51_babbage_spi_cs[] = {
	336	BABBAGE_ECSPI1_CS0,
	337	BABBAGE_ECSPI1_CS1,
	338	};
	339
	340	static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
	341	.chipselect = mx51_babbage_spi_cs,
	342	.num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
	343	};
	344
6ecdc11b	345	static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
913413c3 SG	346	.cd_type = ESDHC_CD_CONTROLLER,
913413c3 SG	347	.wp_type = ESDHC_WP_CONTROLLER,
6ecdc11b AS	348	};
	349
	350	static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
	351	.cd_gpio = BABBAGE_SD2_CD,
	352	.wp_gpio = BABBAGE_SD2_WP,
913413c3 SG	353	.cd_type = ESDHC_CD_GPIO,
913413c3 SG	354	.wp_type = ESDHC_WP_GPIO,
6ecdc11b AS	355	};
6ecdc11b AS	356
9daaf31a SG	357	void __init imx51_babbage_common_init(void)
	358	{
	359	mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
	360	ARRAY_SIZE(mx51babbage_pads));
	361	}
	362
b996b583 AK	363	/*
	364	* Board specific initialization.
	365	*/
e134fb2b	366	static void __init mx51_babbage_init(void)
b996b583	367	{
8f5260c8	368	iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
7242e24a	369	iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
847a2ee7	370	PAD_CTL_SRE_FAST \| PAD_CTL_DSE_HIGH);
231637f5	371
b78d8e59 SG	372	imx51_soc_init();
b78d8e59 SG	373
64f102b6 YS	374	#if defined(CONFIG_CPU_FREQ_IMX)
	375	get_cpu_op = mx51_get_cpu_op;
	376	#endif
9daaf31a	377	imx51_babbage_common_init();
27d2d62b SH	378
27d2d62b SH	379	imx51_add_imx_uart(0, &uart_pdata);
1c4b45d8	380	imx51_add_imx_uart(1, NULL);
27d2d62b SH	381	imx51_add_imx_uart(2, &uart_pdata);
27d2d62b SH	382
3efee47d	383	babbage_fec_reset();
6bd96f3c	384	imx51_add_fec(NULL);
231637f5	385
f2d36ecb	386	/* Set the PAD settings for the pwr key. */
96f3e256	387	mxc_iomux_v3_setup_pad(power_key);
ba8a6c04	388	imx_add_gpio_keys(&imx_button_data);
f2d36ecb	389
44505c07 UKK	390	imx51_add_imx_i2c(0, &babbage_i2c_data);
44505c07 UKK	391	imx51_add_imx_i2c(1, &babbage_i2c_data);
f2688854	392	imx51_add_hsi2c(&babbage_hsi2c_data);
f00b771a	393
2ba5a2c0	394	if (otg_mode_host)
7d92e8e6	395	imx51_add_mxc_ehci_otg(&dr_utmi_config);
2ba5a2c0 DN	396	else {
2ba5a2c0 DN	397	initialize_otg_port(NULL);
6cafe48a	398	imx51_add_fsl_usb2_udc(&usb_pdata);
2ba5a2c0	399	}
231637f5 DN	400
231637f5 DN	401	gpio_usbh1_active();
7d92e8e6	402	imx51_add_mxc_ehci_hs(1, &usbh1_config);
231637f5	403	/* setback USBH1_STP to be function */
96f3e256	404	mxc_iomux_v3_setup_pad(usbh1stp);
231637f5	405	babbage_usbhub_reset();
7223066c	406
6ecdc11b AS	407	imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
6ecdc11b AS	408	imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
374daa4f FE	409
	410	spi_register_board_info(mx51_babbage_spi_board_info,
	411	ARRAY_SIZE(mx51_babbage_spi_board_info));
	412	imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
bec31a85	413	imx51_add_imx2_wdt(0);
b996b583 AK	414	}
	415
	416	static void __init mx51_babbage_timer_init(void)
	417	{
82d52a19	418	mx51_clocks_init(32768, 24000000, 22579200, 0);
b996b583 AK	419	}
b996b583 AK	420
b996b583 AK	421	MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
b996b583 AK	422	/* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
6192935c	423	.atag_offset = 0x100,
b996b583	424	.map_io = mx51_map_io,
ab130421	425	.init_early = imx51_init_early,
b996b583	426	.init_irq = mx51_init_irq,
ffa2ea3f	427	.handle_irq = imx51_handle_irq,
6bb27d73	428	.init_time = mx51_babbage_timer_init,
e134fb2b	429	.init_machine = mx51_babbage_init,
8321b758	430	.init_late = imx51_init_late,
65ea7884	431	.restart = mxc_restart,
b996b583	432	MACHINE_END