[thirdparty/kernel/stable.git] / arch / arm / mach-imx / mach-pcm037.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Copyright (C) 2008 Sascha Hauer, Pengutronix
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/plat-ram.h>
#include <linux/memory.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/property.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/irq.h>
#include <linux/can/platform/sja1000.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/gfp.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>

#include "common.h"
#include "devices-imx31.h"
#include "ehci.h"
#include "hardware.h"
#include "iomux-mx3.h"
#include "pcm037.h"
#include "ulpi.h"

static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;

static int __init pcm037_variant_setup(char *str)
{
	if (!strcmp("eet", str))
		pcm037_instance = PCM037_EET;
	else if (strcmp("pcm970", str))
		pr_warn("Unknown pcm037 baseboard variant %s\n", str);

	return 1;
}

/* Supported values: "pcm970" (default) and "eet" */
__setup("pcm037_variant=", pcm037_variant_setup);

enum pcm037_board_variant pcm037_variant(void)
{
	return pcm037_instance;
}

/* UART1 with RTS/CTS handshake signals */
static unsigned int pcm037_uart1_handshake_pins[] = {
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1,
};

/* UART1 without RTS/CTS handshake signals */
static unsigned int pcm037_uart1_pins[] = {
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1,
};

static unsigned int pcm037_pins[] = {
	/* I2C */
	MX31_PIN_CSPI2_MOSI__SCL,
	MX31_PIN_CSPI2_MISO__SDA,
	MX31_PIN_CSPI2_SS2__I2C3_SDA,
	MX31_PIN_CSPI2_SCLK__I2C3_SCL,
	/* SDHC1 */
	MX31_PIN_SD1_DATA3__SD1_DATA3,
	MX31_PIN_SD1_DATA2__SD1_DATA2,
	MX31_PIN_SD1_DATA1__SD1_DATA1,
	MX31_PIN_SD1_DATA0__SD1_DATA0,
	MX31_PIN_SD1_CLK__SD1_CLK,
	MX31_PIN_SD1_CMD__SD1_CMD,
	IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
	/* SPI1 */
	MX31_PIN_CSPI1_MOSI__MOSI,
	MX31_PIN_CSPI1_MISO__MISO,
	MX31_PIN_CSPI1_SCLK__SCLK,
	MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
	MX31_PIN_CSPI1_SS0__SS0,
	MX31_PIN_CSPI1_SS1__SS1,
	MX31_PIN_CSPI1_SS2__SS2,
	/* UART2 */
	MX31_PIN_TXD2__TXD2,
	MX31_PIN_RXD2__RXD2,
	MX31_PIN_CTS2__CTS2,
	MX31_PIN_RTS2__RTS2,
	/* UART3 */
	MX31_PIN_CSPI3_MOSI__RXD3,
	MX31_PIN_CSPI3_MISO__TXD3,
	MX31_PIN_CSPI3_SCLK__RTS3,
	MX31_PIN_CSPI3_SPI_RDY__CTS3,
	/* LAN9217 irq pin */
	IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
	/* Onewire */
	MX31_PIN_BATT_LINE__OWIRE,
	/* Framebuffer */
	MX31_PIN_LD0__LD0,
	MX31_PIN_LD1__LD1,
	MX31_PIN_LD2__LD2,
	MX31_PIN_LD3__LD3,
	MX31_PIN_LD4__LD4,
	MX31_PIN_LD5__LD5,
	MX31_PIN_LD6__LD6,
	MX31_PIN_LD7__LD7,
	MX31_PIN_LD8__LD8,
	MX31_PIN_LD9__LD9,
	MX31_PIN_LD10__LD10,
	MX31_PIN_LD11__LD11,
	MX31_PIN_LD12__LD12,
	MX31_PIN_LD13__LD13,
	MX31_PIN_LD14__LD14,
	MX31_PIN_LD15__LD15,
	MX31_PIN_LD16__LD16,
	MX31_PIN_LD17__LD17,
	MX31_PIN_VSYNC3__VSYNC3,
	MX31_PIN_HSYNC__HSYNC,
	MX31_PIN_FPSHIFT__FPSHIFT,
	MX31_PIN_DRDY0__DRDY0,
	MX31_PIN_D3_REV__D3_REV,
	MX31_PIN_CONTRAST__CONTRAST,
	MX31_PIN_D3_SPL__D3_SPL,
	MX31_PIN_D3_CLS__D3_CLS,
	MX31_PIN_LCS0__GPIO3_23,
	/* GPIO */
	IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
	/* OTG */
	MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
	MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
	MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
	MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
	MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
	MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
	MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
	MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
	MX31_PIN_USBOTG_CLK__USBOTG_CLK,
	MX31_PIN_USBOTG_DIR__USBOTG_DIR,
	MX31_PIN_USBOTG_NXT__USBOTG_NXT,
	MX31_PIN_USBOTG_STP__USBOTG_STP,
	/* USB host 2 */
	IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
	IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
	IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
	IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
	IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
	IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
	IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
	IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
	IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
	IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
	IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
	IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
};

static struct physmap_flash_data pcm037_flash_data = {
	.width  = 2,
};

static struct resource pcm037_flash_resource = {
	.start	= 0xa0000000,
	.end	= 0xa1ffffff,
	.flags	= IORESOURCE_MEM,
};

static struct platform_device pcm037_flash = {
	.name	= "physmap-flash",
	.id	= 0,
	.dev	= {
		.platform_data  = &pcm037_flash_data,
	},
	.resource = &pcm037_flash_resource,
	.num_resources = 1,
};

static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static struct resource smsc911x_resources[] = {
	{
		.start		= MX31_CS1_BASE_ADDR + 0x300,
		.end		= MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
		.flags		= IORESOURCE_MEM,
	}, {
		/* irq number is run-time assigned */
		.flags		= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
	},
};

static struct smsc911x_platform_config smsc911x_info = {
	.flags		= SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
			  SMSC911X_SAVE_MAC_ADDRESS,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
};

static struct platform_device pcm037_eth = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc911x_resources),
	.resource	= smsc911x_resources,
	.dev		= {
		.platform_data = &smsc911x_info,
	},
};

static struct platdata_mtd_ram pcm038_sram_data = {
	.bankwidth = 2,
};

static struct resource pcm038_sram_resource = {
	.start = MX31_CS4_BASE_ADDR,
	.end   = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
	.flags = IORESOURCE_MEM,
};

static struct platform_device pcm037_sram_device = {
	.name = "mtd-ram",
	.id = 0,
	.dev = {
		.platform_data = &pcm038_sram_data,
	},
	.num_resources = 1,
	.resource = &pcm038_sram_resource,
};

static const struct mxc_nand_platform_data
pcm037_nand_board_info __initconst = {
	.width = 1,
	.hw_ecc = 1,
};

static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
	.bitrate = 100000,
};

static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
	.bitrate = 20000,
};

static const struct property_entry board_eeprom_properties[] = {
	PROPERTY_ENTRY_U32("pagesize", 32),
	{ }
};

static struct i2c_board_info pcm037_i2c_devices[] = {
	{
		I2C_BOARD_INFO("24c32", 0x52), /* E0=0, E1=1, E2=0 */
		.properties = board_eeprom_properties,
	}, {
		I2C_BOARD_INFO("pcf8563", 0x51),
	}
};

/* Not connected by default */
#ifdef PCM970_SDHC_RW_SWITCH
static int pcm970_sdhc1_get_ro(struct device *dev)
{
	return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
}
#endif

#define SDHC1_GPIO_WP	IOMUX_TO_GPIO(MX31_PIN_SFS6)
#define SDHC1_GPIO_DET	IOMUX_TO_GPIO(MX31_PIN_SCK6)

static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
		void *data)
{
	int ret;

	ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
	if (ret)
		return ret;

	gpio_direction_input(SDHC1_GPIO_DET);

#ifdef PCM970_SDHC_RW_SWITCH
	ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
	if (ret)
		goto err_gpio_free;
	gpio_direction_input(SDHC1_GPIO_WP);
#endif

	ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
			IRQF_TRIGGER_FALLING, "sdhc-detect", data);
	if (ret)
		goto err_gpio_free_2;

	return 0;

err_gpio_free_2:
#ifdef PCM970_SDHC_RW_SWITCH
	gpio_free(SDHC1_GPIO_WP);
err_gpio_free:
#endif
	gpio_free(SDHC1_GPIO_DET);

	return ret;
}

static void pcm970_sdhc1_exit(struct device *dev, void *data)
{
	free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
	gpio_free(SDHC1_GPIO_DET);
	gpio_free(SDHC1_GPIO_WP);
}

static const struct imxmmc_platform_data sdhc_pdata __initconst = {
#ifdef PCM970_SDHC_RW_SWITCH
	.get_ro = pcm970_sdhc1_get_ro,
#endif
	.init = pcm970_sdhc1_init,
	.exit = pcm970_sdhc1_exit,
};

static struct platform_device *devices[] __initdata = {
	&pcm037_flash,
	&pcm037_sram_device,
};

static const struct fb_videomode fb_modedb[] = {
	{
		/* 240x320 @ 60 Hz Sharp */
		.name		= "Sharp-LQ035Q7DH06-QVGA",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 185925,
		.left_margin	= 9,
		.right_margin	= 16,
		.upper_margin	= 7,
		.lower_margin	= 9,
		.hsync_len	= 1,
		.vsync_len	= 1,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
				  FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	}, {
		/* 240x320 @ 60 Hz */
		.name		= "TX090",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 38255,
		.left_margin	= 144,
		.right_margin	= 0,
		.upper_margin	= 7,
		.lower_margin	= 40,
		.hsync_len	= 96,
		.vsync_len	= 1,
		.sync		= FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	}, {
		/* 240x320 @ 60 Hz */
		.name		= "CMEL-OLED",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 185925,
		.left_margin	= 9,
		.right_margin	= 16,
		.upper_margin	= 7,
		.lower_margin	= 9,
		.hsync_len	= 1,
		.vsync_len	= 1,
		.sync		= FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	},
};

static struct mx3fb_platform_data mx3fb_pdata = {
	.name		= "Sharp-LQ035Q7DH06-QVGA",
	.mode		= fb_modedb,
	.num_modes	= ARRAY_SIZE(fb_modedb),
};

static struct resource pcm970_sja1000_resources[] = {
	{
		.start   = MX31_CS5_BASE_ADDR,
		.end     = MX31_CS5_BASE_ADDR + 0x100 - 1,
		.flags   = IORESOURCE_MEM,
	}, {
		/* irq number is run-time assigned */
		.flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
	},
};

struct sja1000_platform_data pcm970_sja1000_platform_data = {
	.osc_freq	= 16000000,
	.ocr		= OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
	.cdr		= CDR_CBP,
};

static struct platform_device pcm970_sja1000 = {
	.name = "sja1000_platform",
	.dev = {
		.platform_data = &pcm970_sja1000_platform_data,
	},
	.resource = pcm970_sja1000_resources,
	.num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
};

static int pcm037_otg_init(struct platform_device *pdev)
{
	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
}

static struct mxc_usbh_platform_data otg_pdata __initdata = {
	.init	= pcm037_otg_init,
	.portsc	= MXC_EHCI_MODE_ULPI,
};

static int pcm037_usbh2_init(struct platform_device *pdev)
{
	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
}

static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
	.init	= pcm037_usbh2_init,
	.portsc	= MXC_EHCI_MODE_ULPI,
};

static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
	.operating_mode = FSL_USB2_DR_DEVICE,
	.phy_mode       = FSL_USB2_PHY_ULPI,
};

static bool otg_mode_host __initdata;

static int __init pcm037_otg_mode(char *options)
{
	if (!strcmp(options, "host"))
		otg_mode_host = true;
	else if (!strcmp(options, "device"))
		otg_mode_host = false;
	else
		pr_info("otg_mode neither \"host\" nor \"device\". "
			"Defaulting to device\n");
	return 1;
}
__setup("otg_mode=", pcm037_otg_mode);

static struct regulator_consumer_supply dummy_supplies[] = {
	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
	REGULATOR_SUPPLY("vddvario", "smsc911x"),
};

/*
 * Board specific initialization.
 */
static void __init pcm037_init(void)
{
	imx31_soc_init();

	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));

	mxc_iomux_set_gpr(MUX_PGP_UH2, 1);

	mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
			"pcm037");

#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
		| PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)

	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
	mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);	/* USBH2_DATA2 */
	mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);	/* USBH2_DATA3 */
	mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);	/* USBH2_DATA4 */
	mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);	/* USBH2_DATA5 */
	mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA6 */
	mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA7 */

	if (pcm037_variant() == PCM037_EET)
		mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
			ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
	else
		mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
			ARRAY_SIZE(pcm037_uart1_handshake_pins),
			"pcm037_uart1");

	platform_add_devices(devices, ARRAY_SIZE(devices));

	imx31_add_imx2_wdt();
	imx31_add_imx_uart0(&uart_pdata);
	/* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
	imx31_add_imx_uart1(&uart_pdata);
	imx31_add_imx_uart2(&uart_pdata);

	imx31_add_mxc_w1();

	/* I2C adapters and devices */
	i2c_register_board_info(1, pcm037_i2c_devices,
			ARRAY_SIZE(pcm037_i2c_devices));

	imx31_add_imx_i2c1(&pcm037_i2c1_data);
	imx31_add_imx_i2c2(&pcm037_i2c2_data);

	imx31_add_mxc_nand(&pcm037_nand_board_info);
	imx31_add_ipu_core();
	imx31_add_mx3_sdc_fb(&mx3fb_pdata);

	if (otg_mode_host) {
		otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
				ULPI_OTG_DRVVBUS_EXT);
		if (otg_pdata.otg)
			imx31_add_mxc_ehci_otg(&otg_pdata);
	}

	usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
			ULPI_OTG_DRVVBUS_EXT);
	if (usbh2_pdata.otg)
		imx31_add_mxc_ehci_hs(2, &usbh2_pdata);

	if (!otg_mode_host)
		imx31_add_fsl_usb2_udc(&otg_device_pdata);
}

static void __init pcm037_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static void __init pcm037_init_late(void)
{
	int ret;

	/* LAN9217 IRQ pin */
	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
	if (!ret) {
		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
		smsc911x_resources[1].start =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
		smsc911x_resources[1].end =
			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
		platform_device_register(&pcm037_eth);
	} else {
		pr_warn("could not get LAN irq gpio\n");
	}

	imx31_add_mxc_mmc(0, &sdhc_pdata);

	pcm970_sja1000_resources[1].start =
			gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
	pcm970_sja1000_resources[1].end =
			gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
	platform_device_register(&pcm970_sja1000);

	pcm037_eet_init_devices();
}

MACHINE_START(PCM037, "Phytec Phycore pcm037")
	/* Maintainer: Pengutronix */
	.atag_offset = 0x100,
	.map_io = mx31_map_io,
	.init_early = imx31_init_early,
	.init_irq = mx31_init_irq,
	.init_time	= pcm037_timer_init,
	.init_machine = pcm037_init,
	.init_late = pcm037_init_late,
	.restart	= mxc_restart,
MACHINE_END
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
ce8ffef0 SH	2	/*
ce8ffef0 SH	3	* Copyright (C) 2008 Sascha Hauer, Pengutronix
ce8ffef0 SH	4	*/
	5
	6	#include <linux/types.h>
	7	#include <linux/init.h>
32c1ad9a	8	#include <linux/dma-mapping.h>
ce8ffef0 SH	9	#include <linux/platform_device.h>
ce8ffef0 SH	10	#include <linux/mtd/physmap.h>
3dad21a9	11	#include <linux/mtd/plat-ram.h>
ce8ffef0	12	#include <linux/memory.h>
ba54b958	13	#include <linux/gpio.h>
4353318e	14	#include <linux/smsc911x.h>
ba54b958	15	#include <linux/interrupt.h>
79206750	16	#include <linux/i2c.h>
3b8b2e1e	17	#include <linux/property.h>
dddd4a49 SH	18	#include <linux/delay.h>
	19	#include <linux/spi/spi.h>
	20	#include <linux/irq.h>
91bf9a25	21	#include <linux/can/platform/sja1000.h>
ee14373c SH	22	#include <linux/usb/otg.h>
ee14373c SH	23	#include <linux/usb/ulpi.h>
5a0e3ad6	24	#include <linux/gfp.h>
7dc3a6a5 SH	25	#include <linux/regulator/machine.h>
7dc3a6a5 SH	26	#include <linux/regulator/fixed.h>
ce8ffef0	27
ce8ffef0 SH	28	#include <asm/mach-types.h>
	29	#include <asm/mach/arch.h>
	30	#include <asm/mach/time.h>
	31	#include <asm/mach/map.h>
ce8ffef0	32
e3372474	33	#include "common.h"
a2ceeef5	34	#include "devices-imx31.h"
641dfe8b	35	#include "ehci.h"
50f2de61	36	#include "hardware.h"
267dd34c	37	#include "iomux-mx3.h"
574ec547	38	#include "pcm037.h"
39ef6340	39	#include "ulpi.h"
574ec547 GL	40
	41	static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
	42
	43	static int __init pcm037_variant_setup(char *str)
	44	{
	45	if (!strcmp("eet", str))
	46	pcm037_instance = PCM037_EET;
	47	else if (strcmp("pcm970", str))
75fd32b8	48	pr_warn("Unknown pcm037 baseboard variant %s\n", str);
574ec547 GL	49
	50	return 1;
	51	}
	52
	53	/* Supported values: "pcm970" (default) and "eet" */
	54	__setup("pcm037_variant=", pcm037_variant_setup);
	55
	56	enum pcm037_board_variant pcm037_variant(void)
	57	{
	58	return pcm037_instance;
	59	}
	60
	61	/* UART1 with RTS/CTS handshake signals */
	62	static unsigned int pcm037_uart1_handshake_pins[] = {
	63	MX31_PIN_CTS1__CTS1,
	64	MX31_PIN_RTS1__RTS1,
	65	MX31_PIN_TXD1__TXD1,
	66	MX31_PIN_RXD1__RXD1,
	67	};
	68
	69	/* UART1 without RTS/CTS handshake signals */
	70	static unsigned int pcm037_uart1_pins[] = {
	71	MX31_PIN_TXD1__TXD1,
	72	MX31_PIN_RXD1__RXD1,
	73	};
5cf09421	74
01ac7d58 SH	75	static unsigned int pcm037_pins[] = {
	76	/* I2C */
	77	MX31_PIN_CSPI2_MOSI__SCL,
	78	MX31_PIN_CSPI2_MISO__SDA,
32c1ad9a GL	79	MX31_PIN_CSPI2_SS2__I2C3_SDA,
32c1ad9a GL	80	MX31_PIN_CSPI2_SCLK__I2C3_SCL,
01ac7d58 SH	81	/* SDHC1 */
	82	MX31_PIN_SD1_DATA3__SD1_DATA3,
	83	MX31_PIN_SD1_DATA2__SD1_DATA2,
	84	MX31_PIN_SD1_DATA1__SD1_DATA1,
	85	MX31_PIN_SD1_DATA0__SD1_DATA0,
	86	MX31_PIN_SD1_CLK__SD1_CLK,
	87	MX31_PIN_SD1_CMD__SD1_CMD,
	88	IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
	89	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
	90	/* SPI1 */
	91	MX31_PIN_CSPI1_MOSI__MOSI,
	92	MX31_PIN_CSPI1_MISO__MISO,
	93	MX31_PIN_CSPI1_SCLK__SCLK,
	94	MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
	95	MX31_PIN_CSPI1_SS0__SS0,
	96	MX31_PIN_CSPI1_SS1__SS1,
	97	MX31_PIN_CSPI1_SS2__SS2,
01ac7d58 SH	98	/* UART2 */
	99	MX31_PIN_TXD2__TXD2,
	100	MX31_PIN_RXD2__RXD2,
	101	MX31_PIN_CTS2__CTS2,
	102	MX31_PIN_RTS2__RTS2,
	103	/* UART3 */
	104	MX31_PIN_CSPI3_MOSI__RXD3,
	105	MX31_PIN_CSPI3_MISO__TXD3,
	106	MX31_PIN_CSPI3_SCLK__RTS3,
	107	MX31_PIN_CSPI3_SPI_RDY__CTS3,
	108	/* LAN9217 irq pin */
	109	IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
	110	/* Onewire */
	111	MX31_PIN_BATT_LINE__OWIRE,
	112	/* Framebuffer */
	113	MX31_PIN_LD0__LD0,
	114	MX31_PIN_LD1__LD1,
	115	MX31_PIN_LD2__LD2,
	116	MX31_PIN_LD3__LD3,
	117	MX31_PIN_LD4__LD4,
	118	MX31_PIN_LD5__LD5,
	119	MX31_PIN_LD6__LD6,
	120	MX31_PIN_LD7__LD7,
	121	MX31_PIN_LD8__LD8,
	122	MX31_PIN_LD9__LD9,
	123	MX31_PIN_LD10__LD10,
	124	MX31_PIN_LD11__LD11,
	125	MX31_PIN_LD12__LD12,
	126	MX31_PIN_LD13__LD13,
	127	MX31_PIN_LD14__LD14,
	128	MX31_PIN_LD15__LD15,
	129	MX31_PIN_LD16__LD16,
	130	MX31_PIN_LD17__LD17,
	131	MX31_PIN_VSYNC3__VSYNC3,
	132	MX31_PIN_HSYNC__HSYNC,
	133	MX31_PIN_FPSHIFT__FPSHIFT,
	134	MX31_PIN_DRDY0__DRDY0,
	135	MX31_PIN_D3_REV__D3_REV,
	136	MX31_PIN_CONTRAST__CONTRAST,
	137	MX31_PIN_D3_SPL__D3_SPL,
	138	MX31_PIN_D3_CLS__D3_CLS,
d7b5ccc9	139	MX31_PIN_LCS0__GPIO3_23,
e0fd4db3 LF	140	/* GPIO */
e0fd4db3 LF	141	IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
ee14373c	142	/* OTG */
eb05bbeb GL	143	MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
	144	MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
	145	MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
	146	MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
	147	MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
	148	MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
	149	MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
	150	MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
	151	MX31_PIN_USBOTG_CLK__USBOTG_CLK,
	152	MX31_PIN_USBOTG_DIR__USBOTG_DIR,
	153	MX31_PIN_USBOTG_NXT__USBOTG_NXT,
	154	MX31_PIN_USBOTG_STP__USBOTG_STP,
ee14373c SH	155	/* USB host 2 */
	156	IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
	157	IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
	158	IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
	159	IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
	160	IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
	161	IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
	162	IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
	163	IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
	164	IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
	165	IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
	166	IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
	167	IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
eb05bbeb GL	168	};
eb05bbeb GL	169
ee14373c SH	170	static struct physmap_flash_data pcm037_flash_data = {
	171	.width = 2,
	172	};
eb05bbeb	173
ee14373c SH	174	static struct resource pcm037_flash_resource = {
	175	.start = 0xa0000000,
	176	.end = 0xa1ffffff,
	177	.flags = IORESOURCE_MEM,
eb05bbeb GL	178	};
eb05bbeb GL	179
ce8ffef0 SH	180	static struct platform_device pcm037_flash = {
	181	.name = "physmap-flash",
	182	.id = 0,
	183	.dev = {
	184	.platform_data = &pcm037_flash_data,
	185	},
	186	.resource = &pcm037_flash_resource,
	187	.num_resources = 1,
	188	};
	189
16cf5c41	190	static const struct imxuart_platform_data uart_pdata __initconst = {
a9b06233	191	.flags = IMXUART_HAVE_RTSCTS,
ce8ffef0 SH	192	};
ce8ffef0 SH	193
4353318e	194	static struct resource smsc911x_resources[] = {
3f4f54b4	195	{
f568dd7f UKK	196	.start = MX31_CS1_BASE_ADDR + 0x300,
f568dd7f UKK	197	.end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
ba54b958	198	.flags = IORESOURCE_MEM,
3f4f54b4	199	}, {
ed175343	200	/* irq number is run-time assigned */
4353318e	201	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_LOWLEVEL,
ba54b958 GL	202	},
	203	};
	204
4353318e SG	205	static struct smsc911x_platform_config smsc911x_info = {
	206	.flags = SMSC911X_USE_32BIT \| SMSC911X_FORCE_INTERNAL_PHY \|
	207	SMSC911X_SAVE_MAC_ADDRESS,
	208	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	209	.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	210	.phy_interface = PHY_INTERFACE_MODE_MII,
ba54b958 GL	211	};
	212
	213	static struct platform_device pcm037_eth = {
4353318e	214	.name = "smsc911x",
ba54b958	215	.id = -1,
4353318e SG	216	.num_resources = ARRAY_SIZE(smsc911x_resources),
4353318e SG	217	.resource = smsc911x_resources,
ba54b958	218	.dev = {
4353318e	219	.platform_data = &smsc911x_info,
ba54b958 GL	220	},
	221	};
	222
3dad21a9 SH	223	static struct platdata_mtd_ram pcm038_sram_data = {
	224	.bankwidth = 2,
	225	};
	226
	227	static struct resource pcm038_sram_resource = {
f568dd7f UKK	228	.start = MX31_CS4_BASE_ADDR,
f568dd7f UKK	229	.end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
3dad21a9 SH	230	.flags = IORESOURCE_MEM,
	231	};
	232
	233	static struct platform_device pcm037_sram_device = {
	234	.name = "mtd-ram",
	235	.id = 0,
	236	.dev = {
	237	.platform_data = &pcm038_sram_data,
	238	},
	239	.num_resources = 1,
	240	.resource = &pcm038_sram_resource,
	241	};
	242
a2ceeef5 UKK	243	static const struct mxc_nand_platform_data
a2ceeef5 UKK	244	pcm037_nand_board_info __initconst = {
3287abbd SH	245	.width = 1,
	246	.hw_ecc = 1,
	247	};
	248
4a9b8b0b	249	static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
79206750	250	.bitrate = 100000,
79206750 SH	251	};
79206750 SH	252
4a9b8b0b	253	static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
32c1ad9a GL	254	.bitrate = 20000,
	255	};
	256
3b8b2e1e BG	257	static const struct property_entry board_eeprom_properties[] = {
	258	PROPERTY_ENTRY_U32("pagesize", 32),
	259	{ }
79206750 SH	260	};
	261
	262	static struct i2c_board_info pcm037_i2c_devices[] = {
32c1ad9a	263	{
3b8b2e1e BG	264	I2C_BOARD_INFO("24c32", 0x52), /* E0=0, E1=1, E2=0 */
3b8b2e1e BG	265	.properties = board_eeprom_properties,
79206750	266	}, {
cf87a6e2	267	I2C_BOARD_INFO("pcf8563", 0x51),
79206750 SH	268	}
79206750 SH	269	};
32c1ad9a	270
dddd4a49 SH	271	/* Not connected by default */
	272	#ifdef PCM970_SDHC_RW_SWITCH
	273	static int pcm970_sdhc1_get_ro(struct device *dev)
f2cb641f	274	{
dddd4a49 SH	275	return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
	276	}
	277	#endif
	278
4f163eb8 SH	279	#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
	280	#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
	281
dddd4a49 SH	282	static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
	283	void *data)
	284	{
	285	int ret;
dddd4a49	286
4f163eb8 SH	287	ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
	288	if (ret)
	289	return ret;
	290
	291	gpio_direction_input(SDHC1_GPIO_DET);
dddd4a49	292
4f163eb8 SH	293	#ifdef PCM970_SDHC_RW_SWITCH
	294	ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
	295	if (ret)
	296	goto err_gpio_free;
	297	gpio_direction_input(SDHC1_GPIO_WP);
	298	#endif
dddd4a49	299
ed175343	300	ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
4c1dd3e5	301	IRQF_TRIGGER_FALLING, "sdhc-detect", data);
4f163eb8 SH	302	if (ret)
	303	goto err_gpio_free_2;
	304
	305	return 0;
	306
	307	err_gpio_free_2:
	308	#ifdef PCM970_SDHC_RW_SWITCH
	309	gpio_free(SDHC1_GPIO_WP);
	310	err_gpio_free:
	311	#endif
	312	gpio_free(SDHC1_GPIO_DET);
	313
dddd4a49	314	return ret;
f2cb641f SH	315	}
	316
	317	static void pcm970_sdhc1_exit(struct device dev, void data)
	318	{
ed175343	319	free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
4f163eb8 SH	320	gpio_free(SDHC1_GPIO_DET);
4f163eb8 SH	321	gpio_free(SDHC1_GPIO_WP);
f2cb641f SH	322	}
f2cb641f SH	323
6a697e3d	324	static const struct imxmmc_platform_data sdhc_pdata __initconst = {
dddd4a49 SH	325	#ifdef PCM970_SDHC_RW_SWITCH
	326	.get_ro = pcm970_sdhc1_get_ro,
	327	#endif
f2cb641f SH	328	.init = pcm970_sdhc1_init,
	329	.exit = pcm970_sdhc1_exit,
	330	};
	331
ce8ffef0 SH	332	static struct platform_device *devices[] __initdata = {
ce8ffef0 SH	333	&pcm037_flash,
3dad21a9	334	&pcm037_sram_device,
ce8ffef0 SH	335	};
ce8ffef0 SH	336
a8df0ee8 GL	337	static const struct fb_videomode fb_modedb[] = {
	338	{
	339	/* 240x320 @ 60 Hz Sharp */
	340	.name = "Sharp-LQ035Q7DH06-QVGA",
	341	.refresh = 60,
	342	.xres = 240,
	343	.yres = 320,
	344	.pixclock = 185925,
	345	.left_margin = 9,
	346	.right_margin = 16,
	347	.upper_margin = 7,
	348	.lower_margin = 9,
	349	.hsync_len = 1,
	350	.vsync_len = 1,
	351	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_SHARP_MODE \|
	352	FB_SYNC_CLK_INVERT \| FB_SYNC_CLK_IDLE_EN,
	353	.vmode = FB_VMODE_NONINTERLACED,
	354	.flag = 0,
	355	}, {
	356	/* 240x320 @ 60 Hz */
	357	.name = "TX090",
	358	.refresh = 60,
	359	.xres = 240,
	360	.yres = 320,
	361	.pixclock = 38255,
	362	.left_margin = 144,
	363	.right_margin = 0,
	364	.upper_margin = 7,
	365	.lower_margin = 40,
	366	.hsync_len = 96,
	367	.vsync_len = 1,
	368	.sync = FB_SYNC_VERT_HIGH_ACT \| FB_SYNC_OE_ACT_HIGH,
	369	.vmode = FB_VMODE_NONINTERLACED,
	370	.flag = 0,
574ec547 GL	371	}, {
	372	/* 240x320 @ 60 Hz */
	373	.name = "CMEL-OLED",
	374	.refresh = 60,
	375	.xres = 240,
	376	.yres = 320,
	377	.pixclock = 185925,
	378	.left_margin = 9,
	379	.right_margin = 16,
	380	.upper_margin = 7,
	381	.lower_margin = 9,
	382	.hsync_len = 1,
	383	.vsync_len = 1,
	384	.sync = FB_SYNC_OE_ACT_HIGH \| FB_SYNC_CLK_INVERT,
	385	.vmode = FB_VMODE_NONINTERLACED,
	386	.flag = 0,
a8df0ee8 GL	387	},
	388	};
	389
	390	static struct mx3fb_platform_data mx3fb_pdata = {
a8df0ee8 GL	391	.name = "Sharp-LQ035Q7DH06-QVGA",
	392	.mode = fb_modedb,
	393	.num_modes = ARRAY_SIZE(fb_modedb),
	394	};
	395
91bf9a25 SH	396	static struct resource pcm970_sja1000_resources[] = {
91bf9a25 SH	397	{
f568dd7f UKK	398	.start = MX31_CS5_BASE_ADDR,
f568dd7f UKK	399	.end = MX31_CS5_BASE_ADDR + 0x100 - 1,
91bf9a25 SH	400	.flags = IORESOURCE_MEM,
91bf9a25 SH	401	}, {
ed175343	402	/* irq number is run-time assigned */
91bf9a25 SH	403	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_LOWEDGE,
	404	},
	405	};
	406
	407	struct sja1000_platform_data pcm970_sja1000_platform_data = {
56e6943b WG	408	.osc_freq = 16000000,
	409	.ocr = OCR_TX1_PULLDOWN \| OCR_TX0_PUSHPULL,
	410	.cdr = CDR_CBP,
91bf9a25 SH	411	};
	412
	413	static struct platform_device pcm970_sja1000 = {
	414	.name = "sja1000_platform",
	415	.dev = {
	416	.platform_data = &pcm970_sja1000_platform_data,
	417	},
	418	.resource = pcm970_sja1000_resources,
	419	.num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
	420	};
	421
4bd597b6 SH	422	static int pcm037_otg_init(struct platform_device *pdev)
	423	{
	424	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
	425	}
	426
2d58de28	427	static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6	428	.init = pcm037_otg_init,
ee14373c	429	.portsc = MXC_EHCI_MODE_ULPI,
ee14373c SH	430	};
ee14373c SH	431
4bd597b6 SH	432	static int pcm037_usbh2_init(struct platform_device *pdev)
	433	{
	434	return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
	435	}
	436
2d58de28	437	static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
4bd597b6	438	.init = pcm037_usbh2_init,
ee14373c	439	.portsc = MXC_EHCI_MODE_ULPI,
ee14373c SH	440	};
ee14373c SH	441
9e1dde33	442	static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
ee14373c SH	443	.operating_mode = FSL_USB2_DR_DEVICE,
	444	.phy_mode = FSL_USB2_PHY_ULPI,
	445	};
	446
33a264dd	447	static bool otg_mode_host __initdata;
ee14373c SH	448
	449	static int __init pcm037_otg_mode(char *options)
	450	{
	451	if (!strcmp(options, "host"))
33a264dd	452	otg_mode_host = true;
ee14373c	453	else if (!strcmp(options, "device"))
33a264dd	454	otg_mode_host = false;
ee14373c SH	455	else
	456	pr_info("otg_mode neither \"host\" nor \"device\". "
	457	"Defaulting to device\n");
33a264dd	458	return 1;
ee14373c SH	459	}
	460	__setup("otg_mode=", pcm037_otg_mode);
	461
7dc3a6a5 SH	462	static struct regulator_consumer_supply dummy_supplies[] = {
	463	REGULATOR_SUPPLY("vdd33a", "smsc911x"),
	464	REGULATOR_SUPPLY("vddvario", "smsc911x"),
	465	};
	466
ce8ffef0 SH	467	/*
	468	* Board specific initialization.
	469	*/
e134fb2b	470	static void __init pcm037_init(void)
ce8ffef0	471	{
b78d8e59 SG	472	imx31_soc_init();
b78d8e59 SG	473
7dc3a6a5 SH	474	regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
7dc3a6a5 SH	475
ee14373c	476	mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
4f163eb8	477
01ac7d58 SH	478	mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
	479	"pcm037");
	480
ee14373c SH	481	#define H2_PAD_CFG (PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS_CMOS \
	482	\| PAD_CTL_ODE_CMOS \| PAD_CTL_100K_PU)
	483
	484	mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
	485	mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
	486	mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
	487	mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
	488	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
	489	mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
	490	mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
	491	mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
	492	mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
	493	mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
	494	mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
	495	mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
	496
574ec547 GL	497	if (pcm037_variant() == PCM037_EET)
	498	mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
	499	ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
	500	else
	501	mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
	502	ARRAY_SIZE(pcm037_uart1_handshake_pins),
	503	"pcm037_uart1");
	504
ce8ffef0 SH	505	platform_add_devices(devices, ARRAY_SIZE(devices));
ce8ffef0 SH	506
bec31a85	507	imx31_add_imx2_wdt();
16cf5c41 UKK	508	imx31_add_imx_uart0(&uart_pdata);
	509	/* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
	510	imx31_add_imx_uart1(&uart_pdata);
	511	imx31_add_imx_uart2(&uart_pdata);
d517cab1	512
bec31a85	513	imx31_add_mxc_w1();
ba54b958	514
32c1ad9a	515	/* I2C adapters and devices */
79206750 SH	516	i2c_register_board_info(1, pcm037_i2c_devices,
	517	ARRAY_SIZE(pcm037_i2c_devices));
	518
4a9b8b0b UKK	519	imx31_add_imx_i2c1(&pcm037_i2c1_data);
4a9b8b0b UKK	520	imx31_add_imx_i2c2(&pcm037_i2c2_data);
32c1ad9a	521
a2ceeef5	522	imx31_add_mxc_nand(&pcm037_nand_board_info);
88289c80	523	imx31_add_ipu_core();
afa77ef3	524	imx31_add_mx3_sdc_fb(&mx3fb_pdata);
32c1ad9a	525
ee14373c	526	if (otg_mode_host) {
48f6b099 SH	527	otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS \|
	528	ULPI_OTG_DRVVBUS_EXT);
	529	if (otg_pdata.otg)
	530	imx31_add_mxc_ehci_otg(&otg_pdata);
ee14373c SH	531	}
ee14373c SH	532
48f6b099 SH	533	usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS \|
	534	ULPI_OTG_DRVVBUS_EXT);
	535	if (usbh2_pdata.otg)
	536	imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
ee14373c	537
ee14373c	538	if (!otg_mode_host)
9e1dde33	539	imx31_add_fsl_usb2_udc(&otg_device_pdata);
ce8ffef0 SH	540	}
ce8ffef0 SH	541
ce8ffef0 SH	542	static void __init pcm037_timer_init(void)
ce8ffef0 SH	543	{
30c730f8	544	mx31_clocks_init(26000000);
ce8ffef0 SH	545	}
ce8ffef0 SH	546
8321b758 SG	547	static void __init pcm037_init_late(void)
8321b758 SG	548	{
347aa6c4 VZ	549	int ret;
	550
	551	/* LAN9217 IRQ pin */
	552	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
	553	if (!ret) {
	554	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
	555	smsc911x_resources[1].start =
	556	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
	557	smsc911x_resources[1].end =
	558	gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
	559	platform_device_register(&pcm037_eth);
	560	} else {
	561	pr_warn("could not get LAN irq gpio\n");
	562	}
	563
	564	imx31_add_mxc_mmc(0, &sdhc_pdata);
	565
347aa6c4 VZ	566	pcm970_sja1000_resources[1].start =
	567	gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
	568	pcm970_sja1000_resources[1].end =
	569	gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
	570	platform_device_register(&pcm970_sja1000);
	571
8321b758 SG	572	pcm037_eet_init_devices();
	573	}
	574
ce8ffef0 SH	575	MACHINE_START(PCM037, "Phytec Phycore pcm037")
ce8ffef0 SH	576	/* Maintainer: Pengutronix */
dc8f1907	577	.atag_offset = 0x100,
97976e22 UKK	578	.map_io = mx31_map_io,
	579	.init_early = imx31_init_early,
	580	.init_irq = mx31_init_irq,
6bb27d73	581	.init_time = pcm037_timer_init,
e134fb2b	582	.init_machine = pcm037_init,
8321b758	583	.init_late = pcm037_init_late,
65ea7884	584	.restart = mxc_restart,
ce8ffef0	585	MACHINE_END