projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 64fdf452 SB |
2 | /* |
| 3 | * (C) Copyright 2007 | |
| 4 | * Sascha Hauer, Pengutronix | |
| 5 | * | |
| 6 | * (C) Copyright 2009 Freescale Semiconductor, Inc. | |
| 64fdf452 SB |
7 | */ |
| 8 | ||
| 9 | #include <common.h> | |
| 9edefc27 | 10 | #include <cpu_func.h> |
| 64fdf452 | 11 | #include <asm/arch/imx-regs.h> |
| e4d34492 | 12 | #include <asm/arch/clock.h> |
| 77f11a99 | 13 | #include <asm/arch/sys_proto.h> |
| 90526e9f | 14 | #include <asm/cache.h> |
| 77f11a99 | 15 | |
| 1221ce45 | 16 | #include <linux/errno.h> |
| 64fdf452 | 17 | #include <asm/io.h> |
| 552a848e | 18 | #include <asm/mach-imx/boot_mode.h> |
| 64fdf452 | 19 | |
| 595f3e56 | 20 | #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53)) |
| ff9f475d JL |
21 | #error "CPU_TYPE not defined" |
| 22 | #endif | |
| 23 | ||
| 64fdf452 SB |
24 | u32 get_cpu_rev(void) |
| 25 | { | |
| 595f3e56 LHR |
26 | #ifdef CONFIG_MX51 |
| 27 | int system_rev = 0x51000; | |
| 28 | #else | |
| 29 | int system_rev = 0x53000; | |
| 30 | #endif | |
| ff9f475d | 31 | int reg = __raw_readl(ROM_SI_REV); |
| 64fdf452 | 32 | |
| 595f3e56 | 33 | #if defined(CONFIG_MX51) |
| 64fdf452 SB |
34 | switch (reg) { |
| 35 | case 0x02: | |
| ff9f475d | 36 | system_rev |= CHIP_REV_1_1; |
| 64fdf452 SB |
37 | break; |
| 38 | case 0x10: | |
| 39 | if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) | |
| ff9f475d | 40 | system_rev |= CHIP_REV_2_5; |
| 64fdf452 | 41 | else |
| ff9f475d | 42 | system_rev |= CHIP_REV_2_0; |
| 64fdf452 SB |
43 | break; |
| 44 | case 0x20: | |
| ff9f475d | 45 | system_rev |= CHIP_REV_3_0; |
| 64fdf452 | 46 | break; |
| 64fdf452 | 47 | default: |
| ff9f475d | 48 | system_rev |= CHIP_REV_1_0; |
| 64fdf452 SB |
49 | break; |
| 50 | } | |
| 595f3e56 | 51 | #else |
| aa1cb689 | 52 | if (reg < 0x20) |
| 595f3e56 | 53 | system_rev |= CHIP_REV_1_0; |
| aa1cb689 FE |
54 | else |
| 55 | system_rev |= reg; | |
| 595f3e56 | 56 | #endif |
| 64fdf452 SB |
57 | return system_rev; |
| 58 | } | |
| 59 | ||
| 11c08d4e FE |
60 | #ifdef CONFIG_REVISION_TAG |
| 61 | u32 __weak get_board_rev(void) | |
| 62 | { | |
| 63 | return get_cpu_rev(); | |
| 64 | } | |
| 65 | #endif | |
| 66 | ||
| 10015025 | 67 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
| 78ff1a6c BT |
68 | void enable_caches(void) |
| 69 | { | |
| 70 | /* Enable D-cache. I-cache is already enabled in start.S */ | |
| 71 | dcache_enable(); | |
| 72 | } | |
| 73 | #endif | |
| 74 | ||
| 565e39c5 | 75 | #if defined(CONFIG_FEC_MXC) |
| 0d8a7499 | 76 | void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) |
| 565e39c5 LHR |
77 | { |
| 78 | int i; | |
| 79 | struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; | |
| 80 | struct fuse_bank *bank = &iim->bank[1]; | |
| 81 | struct fuse_bank1_regs *fuse = | |
| 82 | (struct fuse_bank1_regs *)bank->fuse_regs; | |
| 83 | ||
| 84 | for (i = 0; i < 6; i++) | |
| 85 | mac[i] = readl(&fuse->mac_addr[i]) & 0xff; | |
| 86 | } | |
| 87 | #endif | |
| 88 | ||
| 124a06d7 TK |
89 | #ifdef CONFIG_MX53 |
| 90 | void boot_mode_apply(unsigned cfg_val) | |
| 91 | { | |
| 92 | writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr); | |
| 93 | } | |
| 94 | /* | |
| 95 | * cfg_val will be used for | |
| 96 | * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] | |
| 97 | * | |
| 98 | * If bit 28 of LPGR is set upon watchdog reset, | |
| 99 | * bits[25:0] of LPGR will move to SBMR. | |
| 100 | */ | |
| 101 | const struct boot_mode soc_boot_modes[] = { | |
| 102 | {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, | |
| 103 | /* usb or serial download */ | |
| 104 | {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)}, | |
| 105 | {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)}, | |
| 106 | {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)}, | |
| 107 | {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)}, | |
| 108 | {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)}, | |
| 109 | {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)}, | |
| 110 | /* 4 bit bus width */ | |
| 111 | {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)}, | |
| 112 | {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)}, | |
| 113 | {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)}, | |
| 114 | {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)}, | |
| 115 | {NULL, 0}, | |
| 116 | }; | |
| 117 | #endif |