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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * linux/arch/arm/mach-integrator/integrator_ap.c | |
4 | * | |
5 | * Copyright (C) 2000-2003 Deep Blue Solutions Ltd | |
1da177e4 | 6 | */ |
1da177e4 LT |
7 | #include <linux/kernel.h> |
8 | #include <linux/init.h> | |
b7808056 | 9 | #include <linux/syscore_ops.h> |
a62c80e5 | 10 | #include <linux/amba/bus.h> |
fced80c7 | 11 | #include <linux/io.h> |
44fa72d1 | 12 | #include <linux/irqchip.h> |
4980f9bc LW |
13 | #include <linux/of_irq.h> |
14 | #include <linux/of_address.h> | |
4672cddf | 15 | #include <linux/of_platform.h> |
379df279 | 16 | #include <linux/termios.h> |
94a07de1 LW |
17 | #include <linux/mfd/syscon.h> |
18 | #include <linux/regmap.h> | |
1da177e4 | 19 | |
1da177e4 | 20 | #include <asm/mach/arch.h> |
1da177e4 | 21 | #include <asm/mach/map.h> |
1da177e4 | 22 | |
1b1ef755 | 23 | #include "hardware.h" |
bb4dbefe | 24 | #include "cm.h" |
98c672cf | 25 | #include "common.h" |
c36928ad | 26 | #include "lm.h" |
98c672cf | 27 | |
94a07de1 LW |
28 | /* Regmap to the AP system controller */ |
29 | static struct regmap *ap_syscon_map; | |
83feba51 LW |
30 | |
31 | /* | |
1da177e4 LT |
32 | * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx |
33 | * is the (PA >> 12). | |
34 | * | |
35 | * Setup a VA for the Integrator interrupt controller (for header #0, | |
36 | * just for now). | |
37 | */ | |
c41b16f8 | 38 | #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE) |
1da177e4 LT |
39 | |
40 | /* | |
41 | * Logical Physical | |
1da177e4 LT |
42 | * f1400000 14000000 Interrupt controller |
43 | * f1600000 16000000 UART 0 | |
1da177e4 LT |
44 | */ |
45 | ||
060fd1be | 46 | static struct map_desc ap_io_desc[] __initdata __maybe_unused = { |
c8d27298 | 47 | { |
c8d27298 DS |
48 | .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE), |
49 | .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE), | |
50 | .length = SZ_4K, | |
51 | .type = MT_DEVICE | |
52 | }, { | |
53 | .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE), | |
54 | .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE), | |
55 | .length = SZ_4K, | |
56 | .type = MT_DEVICE | |
c8d27298 | 57 | } |
1da177e4 LT |
58 | }; |
59 | ||
60 | static void __init ap_map_io(void) | |
61 | { | |
62 | iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); | |
63 | } | |
64 | ||
1da177e4 LT |
65 | #ifdef CONFIG_PM |
66 | static unsigned long ic_irq_enable; | |
67 | ||
b7808056 | 68 | static int irq_suspend(void) |
1da177e4 LT |
69 | { |
70 | ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); | |
71 | return 0; | |
72 | } | |
73 | ||
b7808056 | 74 | static void irq_resume(void) |
1da177e4 LT |
75 | { |
76 | /* disable all irq sources */ | |
bb4dbefe | 77 | cm_clear_irqs(); |
1da177e4 LT |
78 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); |
79 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); | |
80 | ||
81 | writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); | |
1da177e4 LT |
82 | } |
83 | #else | |
84 | #define irq_suspend NULL | |
85 | #define irq_resume NULL | |
86 | #endif | |
87 | ||
b7808056 | 88 | static struct syscore_ops irq_syscore_ops = { |
1da177e4 LT |
89 | .suspend = irq_suspend, |
90 | .resume = irq_resume, | |
91 | }; | |
92 | ||
b7808056 | 93 | static int __init irq_syscore_init(void) |
1da177e4 | 94 | { |
b7808056 RW |
95 | register_syscore_ops(&irq_syscore_ops); |
96 | ||
97 | return 0; | |
1da177e4 LT |
98 | } |
99 | ||
b7808056 | 100 | device_initcall(irq_syscore_init); |
1da177e4 | 101 | |
379df279 LW |
102 | /* |
103 | * For the PL010 found in the Integrator/AP some of the UART control is | |
104 | * implemented in the system controller and accessed using a callback | |
105 | * from the driver. | |
106 | */ | |
107 | static void integrator_uart_set_mctrl(struct amba_device *dev, | |
108 | void __iomem *base, unsigned int mctrl) | |
109 | { | |
110 | unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask; | |
111 | u32 phybase = dev->res.start; | |
94a07de1 | 112 | int ret; |
379df279 LW |
113 | |
114 | if (phybase == INTEGRATOR_UART0_BASE) { | |
115 | /* UART0 */ | |
116 | rts_mask = 1 << 4; | |
117 | dtr_mask = 1 << 5; | |
118 | } else { | |
119 | /* UART1 */ | |
120 | rts_mask = 1 << 6; | |
121 | dtr_mask = 1 << 7; | |
122 | } | |
123 | ||
124 | if (mctrl & TIOCM_RTS) | |
125 | ctrlc |= rts_mask; | |
126 | else | |
127 | ctrls |= rts_mask; | |
128 | ||
129 | if (mctrl & TIOCM_DTR) | |
130 | ctrlc |= dtr_mask; | |
131 | else | |
132 | ctrls |= dtr_mask; | |
133 | ||
94a07de1 LW |
134 | ret = regmap_write(ap_syscon_map, |
135 | INTEGRATOR_SC_CTRLS_OFFSET, | |
136 | ctrls); | |
137 | if (ret) | |
138 | pr_err("MODEM: unable to write PL010 UART CTRLS\n"); | |
139 | ||
140 | ret = regmap_write(ap_syscon_map, | |
141 | INTEGRATOR_SC_CTRLC_OFFSET, | |
142 | ctrlc); | |
143 | if (ret) | |
144 | pr_err("MODEM: unable to write PL010 UART CRTLC\n"); | |
379df279 LW |
145 | } |
146 | ||
147 | struct amba_pl010_data ap_uart_data = { | |
148 | .set_mctrl = integrator_uart_set_mctrl, | |
149 | }; | |
150 | ||
a613163d LW |
151 | void __init ap_init_early(void) |
152 | { | |
153 | } | |
154 | ||
4980f9bc LW |
155 | static void __init ap_init_irq_of(void) |
156 | { | |
bb4dbefe | 157 | cm_init(); |
44fa72d1 | 158 | irqchip_init(); |
4980f9bc LW |
159 | } |
160 | ||
4672cddf LW |
161 | /* For the Device Tree, add in the UART callbacks as AUXDATA */ |
162 | static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = { | |
4672cddf | 163 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE, |
379df279 | 164 | "uart0", &ap_uart_data), |
4672cddf | 165 | OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE, |
379df279 | 166 | "uart1", &ap_uart_data), |
4672cddf LW |
167 | { /* sentinel */ }, |
168 | }; | |
169 | ||
df36680f LW |
170 | static const struct of_device_id ap_syscon_match[] = { |
171 | { .compatible = "arm,integrator-ap-syscon"}, | |
172 | { }, | |
173 | }; | |
174 | ||
4672cddf LW |
175 | static void __init ap_init_of(void) |
176 | { | |
94a07de1 | 177 | u32 sc_dec; |
e67ae6be | 178 | struct device_node *syscon; |
94a07de1 | 179 | int ret; |
4672cddf LW |
180 | int i; |
181 | ||
94a07de1 LW |
182 | of_platform_default_populate(NULL, ap_auxdata_lookup, NULL); |
183 | ||
11f9323a | 184 | syscon = of_find_matching_node(NULL, ap_syscon_match); |
e67ae6be LW |
185 | if (!syscon) |
186 | return; | |
94a07de1 LW |
187 | ap_syscon_map = syscon_node_to_regmap(syscon); |
188 | if (IS_ERR(ap_syscon_map)) { | |
189 | pr_crit("could not find Integrator/AP system controller\n"); | |
307b9667 | 190 | return; |
94a07de1 | 191 | } |
e67ae6be | 192 | |
94a07de1 LW |
193 | ret = regmap_read(ap_syscon_map, |
194 | INTEGRATOR_SC_DEC_OFFSET, | |
195 | &sc_dec); | |
196 | if (ret) { | |
197 | pr_crit("could not read from Integrator/AP syscon\n"); | |
307b9667 | 198 | return; |
94a07de1 | 199 | } |
e67ae6be | 200 | |
4672cddf LW |
201 | for (i = 0; i < 4; i++) { |
202 | struct lm_device *lmdev; | |
203 | ||
204 | if ((sc_dec & (16 << i)) == 0) | |
205 | continue; | |
206 | ||
207 | lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); | |
208 | if (!lmdev) | |
209 | continue; | |
210 | ||
211 | lmdev->resource.start = 0xc0000000 + 0x10000000 * i; | |
212 | lmdev->resource.end = lmdev->resource.start + 0x0fffffff; | |
213 | lmdev->resource.flags = IORESOURCE_MEM; | |
a6720258 | 214 | lmdev->irq = irq_of_parse_and_map(syscon, i); |
4672cddf LW |
215 | lmdev->id = i; |
216 | ||
217 | lm_device_register(lmdev); | |
218 | } | |
219 | } | |
220 | ||
4980f9bc LW |
221 | static const char * ap_dt_board_compat[] = { |
222 | "arm,integrator-ap", | |
223 | NULL, | |
224 | }; | |
225 | ||
226 | DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") | |
227 | .reserve = integrator_reserve, | |
228 | .map_io = ap_map_io, | |
4980f9bc LW |
229 | .init_early = ap_init_early, |
230 | .init_irq = ap_init_irq_of, | |
4672cddf | 231 | .init_machine = ap_init_of, |
4980f9bc LW |
232 | .dt_compat = ap_dt_board_compat, |
233 | MACHINE_END |