[thirdparty/kernel/linux.git] / arch / arm / mach-iop13xx / include / mach / time.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _IOP13XX_TIME_H_
#define _IOP13XX_TIME_H_

#include <mach/irqs.h>

#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0

#define IOP_TMR_EN	    0x02
#define IOP_TMR_RELOAD	    0x04
#define IOP_TMR_PRIVILEGED 0x08
#define IOP_TMR_RATIO_1_1  0x00

#define IOP13XX_XSI_FREQ_RATIO_MASK	(3 << 19)
#define IOP13XX_XSI_FREQ_RATIO_2   	(0 << 19)
#define IOP13XX_XSI_FREQ_RATIO_3	(1 << 19)
#define IOP13XX_XSI_FREQ_RATIO_4	(2 << 19)
#define IOP13XX_CORE_FREQ_MASK		(7 << 16)
#define IOP13XX_CORE_FREQ_600		(0 << 16)
#define IOP13XX_CORE_FREQ_667		(1 << 16)
#define IOP13XX_CORE_FREQ_800		(2 << 16)
#define IOP13XX_CORE_FREQ_933		(3 << 16)
#define IOP13XX_CORE_FREQ_1000		(4 << 16)
#define IOP13XX_CORE_FREQ_1200		(5 << 16)

void iop_init_time(unsigned long tickrate);

static inline unsigned long iop13xx_core_freq(void)
{
	unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
	freq &= IOP13XX_CORE_FREQ_MASK;
	switch (freq) {
	case IOP13XX_CORE_FREQ_600:
		return 600000000;
	case IOP13XX_CORE_FREQ_667:
		return 667000000;
	case IOP13XX_CORE_FREQ_800:
		return 800000000;
	case IOP13XX_CORE_FREQ_933:
		return 933000000;
	case IOP13XX_CORE_FREQ_1000:
		return 1000000000;
	case IOP13XX_CORE_FREQ_1200:
		return 1200000000;
	default:
		printk("%s: warning unknown frequency, defaulting to 800MHz\n",
			__func__);
	}

	return 800000000;
}

static inline unsigned long iop13xx_xsi_bus_ratio(void)
{
	unsigned long  ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
	ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
	switch (ratio) {
	case IOP13XX_XSI_FREQ_RATIO_2:
		return 2;
	case IOP13XX_XSI_FREQ_RATIO_3:
		return 3;
	case IOP13XX_XSI_FREQ_RATIO_4:
		return 4;
	default:
		printk("%s: warning unknown ratio, defaulting to 2\n",
			__func__);
	}

	return 2;
}

static inline u32 read_tmr0(void)
{
	u32 val;
	asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val));
	return val;
}

static inline void write_tmr0(u32 val)
{
	asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
}

static inline void write_tmr1(u32 val)
{
	asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
}

static inline u32 read_tcr0(void)
{
	u32 val;
	asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
	return val;
}

static inline void write_tcr0(u32 val)
{
	asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val));
}

static inline u32 read_tcr1(void)
{
	u32 val;
	asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
	return val;
}

static inline void write_tcr1(u32 val)
{
	asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val));
}

static inline void write_trr0(u32 val)
{
	asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
}

static inline void write_trr1(u32 val)
{
	asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
}

static inline void write_tisr(u32 val)
{
	asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
}
#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
3668b45d DW	2	#ifndef _IOP13XX_TIME_H_
3668b45d DW	3	#define _IOP13XX_TIME_H_
37ebbcff TG	4
	5	#include <mach/irqs.h>
	6
3668b45d DW	7	#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
	8
	9	#define IOP_TMR_EN 0x02
	10	#define IOP_TMR_RELOAD 0x04
	11	#define IOP_TMR_PRIVILEGED 0x08
	12	#define IOP_TMR_RATIO_1_1 0x00
	13
84c981ff DW	14	#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19)
	15	#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19)
	16	#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19)
	17	#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19)
	18	#define IOP13XX_CORE_FREQ_MASK (7 << 16)
	19	#define IOP13XX_CORE_FREQ_600 (0 << 16)
	20	#define IOP13XX_CORE_FREQ_667 (1 << 16)
	21	#define IOP13XX_CORE_FREQ_800 (2 << 16)
	22	#define IOP13XX_CORE_FREQ_933 (3 << 16)
	23	#define IOP13XX_CORE_FREQ_1000 (4 << 16)
	24	#define IOP13XX_CORE_FREQ_1200 (5 << 16)
	25
3668b45d	26	void iop_init_time(unsigned long tickrate);
3668b45d	27
84c981ff DW	28	static inline unsigned long iop13xx_core_freq(void)
	29	{
	30	unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
	31	freq &= IOP13XX_CORE_FREQ_MASK;
	32	switch (freq) {
	33	case IOP13XX_CORE_FREQ_600:
	34	return 600000000;
	35	case IOP13XX_CORE_FREQ_667:
	36	return 667000000;
	37	case IOP13XX_CORE_FREQ_800:
	38	return 800000000;
	39	case IOP13XX_CORE_FREQ_933:
	40	return 933000000;
	41	case IOP13XX_CORE_FREQ_1000:
	42	return 1000000000;
	43	case IOP13XX_CORE_FREQ_1200:
	44	return 1200000000;
	45	default:
6a53bc75	46	printk("%s: warning unknown frequency, defaulting to 800MHz\n",
653c0316	47	__func__);
84c981ff DW	48	}
	49
	50	return 800000000;
	51	}
	52
	53	static inline unsigned long iop13xx_xsi_bus_ratio(void)
	54	{
	55	unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
	56	ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
	57	switch (ratio) {
	58	case IOP13XX_XSI_FREQ_RATIO_2:
	59	return 2;
	60	case IOP13XX_XSI_FREQ_RATIO_3:
	61	return 3;
	62	case IOP13XX_XSI_FREQ_RATIO_4:
	63	return 4;
	64	default:
	65	printk("%s: warning unknown ratio, defaulting to 2\n",
653c0316	66	__func__);
84c981ff DW	67	}
	68
	69	return 2;
	70	}
	71
469d3044 MP	72	static inline u32 read_tmr0(void)
	73	{
	74	u32 val;
	75	asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val));
	76	return val;
	77	}
	78
3668b45d DW	79	static inline void write_tmr0(u32 val)
	80	{
	81	asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
	82	}
	83
	84	static inline void write_tmr1(u32 val)
	85	{
	86	asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
	87	}
	88
	89	static inline u32 read_tcr0(void)
	90	{
	91	u32 val;
	92	asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
	93	return val;
	94	}
	95
469d3044 MP	96	static inline void write_tcr0(u32 val)
	97	{
	98	asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val));
	99	}
	100
3668b45d DW	101	static inline u32 read_tcr1(void)
	102	{
	103	u32 val;
	104	asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
	105	return val;
	106	}
	107
a91549a8 MP	108	static inline void write_tcr1(u32 val)
	109	{
	110	asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val));
	111	}
	112
3668b45d DW	113	static inline void write_trr0(u32 val)
	114	{
	115	asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
	116	}
	117
	118	static inline void write_trr1(u32 val)
	119	{
	120	asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
	121	}
	122
	123	static inline void write_tisr(u32 val)
	124	{
	125	asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
	126	}
	127	#endif