projects / people / arne_f / kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 285f5fa7 DW |
1 | /* |
| 2 | * iq81340mc board support | |
| 3 | * Copyright (c) 2005-2006, Intel Corporation. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify it | |
| 6 | * under the terms and conditions of the GNU General Public License, | |
| 7 | * version 2, as published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 12 | * more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License along with | |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
| 16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
| 17 | * | |
| 18 | */ | |
| 19 | #include <linux/pci.h> | |
| 20 | ||
| a09e64fb | 21 | #include <mach/hardware.h> |
| 285f5fa7 DW |
22 | #include <asm/irq.h> |
| 23 | #include <asm/mach/pci.h> | |
| 24 | #include <asm/mach-types.h> | |
| 25 | #include <asm/mach/arch.h> | |
| a09e64fb | 26 | #include <mach/pci.h> |
| 285f5fa7 | 27 | #include <asm/mach/time.h> |
| a09e64fb | 28 | #include <mach/time.h> |
| 285f5fa7 DW |
29 | |
| 30 | extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */ | |
| 31 | ||
| 32 | static int __init | |
| d5341942 | 33 | iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) |
| 285f5fa7 DW |
34 | { |
| 35 | switch (idsel) { | |
| 36 | case 1: | |
| 37 | switch (pin) { | |
| 38 | case 1: return ATUX_INTB; | |
| 39 | case 2: return ATUX_INTC; | |
| 40 | case 3: return ATUX_INTD; | |
| 41 | case 4: return ATUX_INTA; | |
| 42 | default: return -1; | |
| 43 | } | |
| 44 | case 2: | |
| 45 | switch (pin) { | |
| 46 | case 1: return ATUX_INTC; | |
| 47 | case 2: return ATUX_INTD; | |
| 48 | case 3: return ATUX_INTC; | |
| 49 | case 4: return ATUX_INTD; | |
| 50 | default: return -1; | |
| 51 | } | |
| 52 | default: return -1; | |
| 53 | } | |
| 54 | } | |
| 55 | ||
| 56 | static struct hw_pci iq81340mc_pci __initdata = { | |
| 285f5fa7 DW |
57 | .nr_controllers = 0, |
| 58 | .setup = iop13xx_pci_setup, | |
| 59 | .map_irq = iq81340mc_pcix_map_irq, | |
| 60 | .scan = iop13xx_scan_bus, | |
| 61 | .preinit = iop13xx_pci_init, | |
| 62 | }; | |
| 63 | ||
| 64 | static int __init iq81340mc_pci_init(void) | |
| 65 | { | |
| 66 | iop13xx_atu_select(&iq81340mc_pci); | |
| 67 | pci_common_init(&iq81340mc_pci); | |
| 68 | iop13xx_map_pci_memory(); | |
| 69 | ||
| 70 | return 0; | |
| 71 | } | |
| 72 | ||
| 73 | static void __init iq81340mc_init(void) | |
| 74 | { | |
| 75 | iop13xx_platform_init(); | |
| 76 | iq81340mc_pci_init(); | |
| d2dd8b1f | 77 | iop13xx_add_tpmi_devices(); |
| 285f5fa7 DW |
78 | } |
| 79 | ||
| 80 | static void __init iq81340mc_timer_init(void) | |
| 81 | { | |
| 84c981ff | 82 | unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio(); |
| 8e86f427 | 83 | printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq); |
| 84c981ff | 84 | iop_init_time(bus_freq); |
| 285f5fa7 DW |
85 | } |
| 86 | ||
| 285f5fa7 DW |
87 | MACHINE_START(IQ81340MC, "Intel IQ81340MC") |
| 88 | /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ | |
| d304c54e | 89 | .atag_offset = 0x100, |
| 1dfe34ae | 90 | .init_early = iop13xx_init_early, |
| 285f5fa7 DW |
91 | .map_io = iop13xx_map_io, |
| 92 | .init_irq = iop13xx_init_irq, | |
| 6bb27d73 | 93 | .init_time = iq81340mc_timer_init, |
| 285f5fa7 | 94 | .init_machine = iq81340mc_init, |
| 00aa78ee | 95 | .restart = iop13xx_restart, |
| 285f5fa7 | 96 | MACHINE_END |