projects / people / arne_f / kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 285f5fa7 DW |
1 | /* |
| 2 | * iq81340sc board support | |
| 3 | * Copyright (c) 2005-2006, Intel Corporation. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify it | |
| 6 | * under the terms and conditions of the GNU General Public License, | |
| 7 | * version 2, as published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 12 | * more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License along with | |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
| 16 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
| 17 | * | |
| 18 | */ | |
| 19 | #include <linux/pci.h> | |
| 20 | ||
| a09e64fb | 21 | #include <mach/hardware.h> |
| 285f5fa7 DW |
22 | #include <asm/irq.h> |
| 23 | #include <asm/mach/pci.h> | |
| 24 | #include <asm/mach-types.h> | |
| 25 | #include <asm/mach/arch.h> | |
| a09e64fb | 26 | #include <mach/pci.h> |
| 285f5fa7 | 27 | #include <asm/mach/time.h> |
| a09e64fb | 28 | #include <mach/time.h> |
| 285f5fa7 DW |
29 | |
| 30 | extern int init_atu; | |
| 31 | ||
| 32 | static int __init | |
| 58cbdbe0 | 33 | iq81340sc_atux_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) |
| 285f5fa7 DW |
34 | { |
| 35 | WARN_ON(idsel < 1 || idsel > 2); | |
| 36 | ||
| 37 | switch (idsel) { | |
| 38 | case 1: | |
| 39 | switch (pin) { | |
| 40 | case 1: return ATUX_INTB; | |
| 41 | case 2: return ATUX_INTC; | |
| 42 | case 3: return ATUX_INTD; | |
| 43 | case 4: return ATUX_INTA; | |
| 44 | default: return -1; | |
| 45 | } | |
| 46 | case 2: | |
| 47 | switch (pin) { | |
| 48 | case 1: return ATUX_INTC; | |
| 49 | case 2: return ATUX_INTC; | |
| 50 | case 3: return ATUX_INTC; | |
| 51 | case 4: return ATUX_INTC; | |
| 52 | default: return -1; | |
| 53 | } | |
| 54 | default: return -1; | |
| 55 | } | |
| 56 | } | |
| 57 | ||
| 58 | static struct hw_pci iq81340sc_pci __initdata = { | |
| 285f5fa7 DW |
59 | .nr_controllers = 0, |
| 60 | .setup = iop13xx_pci_setup, | |
| 61 | .scan = iop13xx_scan_bus, | |
| 62 | .map_irq = iq81340sc_atux_map_irq, | |
| 63 | .preinit = iop13xx_pci_init | |
| 64 | }; | |
| 65 | ||
| 66 | static int __init iq81340sc_pci_init(void) | |
| 67 | { | |
| 68 | iop13xx_atu_select(&iq81340sc_pci); | |
| 69 | pci_common_init(&iq81340sc_pci); | |
| 70 | iop13xx_map_pci_memory(); | |
| 71 | ||
| 72 | return 0; | |
| 73 | } | |
| 74 | ||
| 75 | static void __init iq81340sc_init(void) | |
| 76 | { | |
| 77 | iop13xx_platform_init(); | |
| 78 | iq81340sc_pci_init(); | |
| d2dd8b1f | 79 | iop13xx_add_tpmi_devices(); |
| 285f5fa7 DW |
80 | } |
| 81 | ||
| 82 | static void __init iq81340sc_timer_init(void) | |
| 83 | { | |
| 84c981ff | 84 | unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio(); |
| 8e86f427 | 85 | printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq); |
| 84c981ff | 86 | iop_init_time(bus_freq); |
| 285f5fa7 DW |
87 | } |
| 88 | ||
| 285f5fa7 DW |
89 | MACHINE_START(IQ81340SC, "Intel IQ81340SC") |
| 90 | /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ | |
| d304c54e | 91 | .atag_offset = 0x100, |
| 1dfe34ae | 92 | .init_early = iop13xx_init_early, |
| 285f5fa7 DW |
93 | .map_io = iop13xx_map_io, |
| 94 | .init_irq = iop13xx_init_irq, | |
| 6bb27d73 | 95 | .init_time = iq81340sc_timer_init, |
| 285f5fa7 | 96 | .init_machine = iq81340sc_init, |
| 00aa78ee | 97 | .restart = iop13xx_restart, |
| 285f5fa7 | 98 | MACHINE_END |