[thirdparty/kernel/stable.git] / arch / arm / mach-iop13xx / setup.c

/*
 * iop13xx platform Initialization
 * Copyright (c) 2005-2006, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
 * Place - Suite 330, Boston, MA 02111-1307 USA.
 *
 */

#include <linux/serial_8250.h>
#ifdef CONFIG_MTD_PHYSMAP
#include <linux/mtd/physmap.h>
#endif
#include <asm/mach/map.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/io.h>

#define IOP13XX_UART_XTAL 33334000
#define IOP13XX_SETUP_DEBUG 0
#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))

/* Standard IO mapping for all IOP13XX based systems
 */
static struct map_desc iop13xx_std_desc[] __initdata = {
	{    /* mem mapped registers */
		.virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
		.pfn 	 = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
		.length  = IOP13XX_PMMR_SIZE,
		.type	 = MT_DEVICE,
	}, { /* PCIE IO space */
		.virtual = IOP13XX_PCIE_LOWER_IO_VA,
		.pfn 	 = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
		.length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
		.type	 = MT_DEVICE,
	}, { /* PCIX IO space */
		.virtual = IOP13XX_PCIX_LOWER_IO_VA,
		.pfn 	 = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
		.length  = IOP13XX_PCIX_IO_WINDOW_SIZE,
		.type	 = MT_DEVICE,
	},
};

static struct resource iop13xx_uart0_resources[] = {
	[0] = {
		.start = IOP13XX_UART0_PHYS,
		.end = IOP13XX_UART0_PHYS + 0x3f,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = IRQ_IOP13XX_UART0,
		.end = IRQ_IOP13XX_UART0,
		.flags = IORESOURCE_IRQ
	}
};

static struct resource iop13xx_uart1_resources[] = {
	[0] = {
		.start = IOP13XX_UART1_PHYS,
		.end = IOP13XX_UART1_PHYS + 0x3f,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = IRQ_IOP13XX_UART1,
		.end = IRQ_IOP13XX_UART1,
		.flags = IORESOURCE_IRQ
	}
};

static struct plat_serial8250_port iop13xx_uart0_data[] = {
	{
       .membase     = (char*)(IOP13XX_UART0_VIRT),
       .mapbase     = (IOP13XX_UART0_PHYS),
       .irq         = IRQ_IOP13XX_UART0,
       .uartclk     = IOP13XX_UART_XTAL,
       .regshift    = 2,
       .iotype      = UPIO_MEM,
       .flags       = UPF_SKIP_TEST,
	},
	{  },
};

static struct plat_serial8250_port iop13xx_uart1_data[] = {
	{
       .membase     = (char*)(IOP13XX_UART1_VIRT),
       .mapbase     = (IOP13XX_UART1_PHYS),
       .irq         = IRQ_IOP13XX_UART1,
       .uartclk     = IOP13XX_UART_XTAL,
       .regshift    = 2,
       .iotype      = UPIO_MEM,
       .flags       = UPF_SKIP_TEST,
	},
	{  },
};

/* The ids are fixed up later in iop13xx_platform_init */
static struct platform_device iop13xx_uart0 = {
       .name = "serial8250",
       .id = 0,
       .dev.platform_data = iop13xx_uart0_data,
       .num_resources = 2,
       .resource = iop13xx_uart0_resources,
};

static struct platform_device iop13xx_uart1 = {
       .name = "serial8250",
       .id = 0,
       .dev.platform_data = iop13xx_uart1_data,
       .num_resources = 2,
       .resource = iop13xx_uart1_resources
};

static struct resource iop13xx_i2c_0_resources[] = {
	[0] = {
		.start = IOP13XX_I2C0_PHYS,
		.end = IOP13XX_I2C0_PHYS + 0x18,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = IRQ_IOP13XX_I2C_0,
		.end = IRQ_IOP13XX_I2C_0,
		.flags = IORESOURCE_IRQ
	}
};

static struct resource iop13xx_i2c_1_resources[] = {
	[0] = {
		.start = IOP13XX_I2C1_PHYS,
		.end = IOP13XX_I2C1_PHYS + 0x18,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = IRQ_IOP13XX_I2C_1,
		.end = IRQ_IOP13XX_I2C_1,
		.flags = IORESOURCE_IRQ
	}
};

static struct resource iop13xx_i2c_2_resources[] = {
	[0] = {
		.start = IOP13XX_I2C2_PHYS,
		.end = IOP13XX_I2C2_PHYS + 0x18,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = IRQ_IOP13XX_I2C_2,
		.end = IRQ_IOP13XX_I2C_2,
		.flags = IORESOURCE_IRQ
	}
};

/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
 * we just use the same device name.
 */

/* The ids are fixed up later in iop13xx_platform_init */
static struct platform_device iop13xx_i2c_0_controller = {
	.name = "IOP3xx-I2C",
	.id = 0,
	.num_resources = 2,
	.resource = iop13xx_i2c_0_resources
};

static struct platform_device iop13xx_i2c_1_controller = {
	.name = "IOP3xx-I2C",
	.id = 0,
	.num_resources = 2,
	.resource = iop13xx_i2c_1_resources
};

static struct platform_device iop13xx_i2c_2_controller = {
	.name = "IOP3xx-I2C",
	.id = 0,
	.num_resources = 2,
	.resource = iop13xx_i2c_2_resources
};

#ifdef CONFIG_MTD_PHYSMAP
/* PBI Flash Device
 */
static struct physmap_flash_data iq8134x_flash_data = {
	.width = 2,
};

static struct resource iq8134x_flash_resource = {
	.start = IQ81340_FLASHBASE,
	.end   = 0,
	.flags = IORESOURCE_MEM,
};

static struct platform_device iq8134x_flash = {
	.name           = "physmap-flash",
	.id             = 0,
	.dev            = { .platform_data  = &iq8134x_flash_data, },
	.num_resources  = 1,
	.resource       = &iq8134x_flash_resource,
};

static unsigned long iq8134x_probe_flash_size(void)
{
	uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
	int i;
	char query[3];
	unsigned long size = 0;
	int width = iq8134x_flash_data.width;

	if (flash_addr) {
		/* send CFI 'query' command */
		writew(0x98, flash_addr);

		/* check for CFI compliance */
		for (i = 0; i < 3 * width; i += width)
			query[i / width] = readb(flash_addr + (0x10 * width) + i);

		/* read the size */
		if (memcmp(query, "QRY", 3) == 0)
			size = 1 << readb(flash_addr + (0x27 * width));

		/* send CFI 'read array' command */
		writew(0xff, flash_addr);

		iounmap(flash_addr);
	}

	return size;
}
#endif

void __init iop13xx_map_io(void)
{
	/* Initialize the Static Page Table maps */
	iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
}

static int init_uart = 0;
static int init_i2c = 0;

void __init iop13xx_platform_init(void)
{
	int i;
	u32 uart_idx, i2c_idx, plat_idx;
	struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];

	/* set the bases so we can read the device id */
	iop13xx_set_atu_mmr_bases();

	memset(iop13xx_devices, 0, sizeof(iop13xx_devices));

	if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
		switch (iop13xx_dev_id()) {
		/* enable both uarts on iop341 and iop342 */
		case 0x3380:
		case 0x3384:
		case 0x3388:
		case 0x338c:
		case 0x3382:
		case 0x3386:
		case 0x338a:
		case 0x338e:
			init_uart |= IOP13XX_INIT_UART_0;
			init_uart |= IOP13XX_INIT_UART_1;
			break;
		/* only enable uart 1 */
		default:
			init_uart |= IOP13XX_INIT_UART_1;
		}
	}

	if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
		switch (iop13xx_dev_id()) {
		/* enable all i2c units on iop341 and iop342 */
		case 0x3380:
		case 0x3384:
		case 0x3388:
		case 0x338c:
		case 0x3382:
		case 0x3386:
		case 0x338a:
		case 0x338e:
			init_i2c |= IOP13XX_INIT_I2C_0;
			init_i2c |= IOP13XX_INIT_I2C_1;
			init_i2c |= IOP13XX_INIT_I2C_2;
			break;
		/* only enable i2c 1 and 2 */
		default:
			init_i2c |= IOP13XX_INIT_I2C_1;
			init_i2c |= IOP13XX_INIT_I2C_2;
		}
	}

	plat_idx = 0;
	uart_idx = 0;
	i2c_idx = 0;

	/* uart 1 (if enabled) is ttyS0 */
	if (init_uart & IOP13XX_INIT_UART_1) {
		PRINTK("Adding uart1 to platform device list\n");
		iop13xx_uart1.id = uart_idx++;
		iop13xx_devices[plat_idx++] = &iop13xx_uart1;
	}
	if (init_uart & IOP13XX_INIT_UART_0) {
		PRINTK("Adding uart0 to platform device list\n");
		iop13xx_uart0.id = uart_idx++;
		iop13xx_devices[plat_idx++] = &iop13xx_uart0;
	}

	for(i = 0; i < IQ81340_NUM_I2C; i++) {
		if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
			printk("Adding i2c%d to platform device list\n", i);
		switch(init_i2c & (1 << i)) {
		case IOP13XX_INIT_I2C_0:
			iop13xx_i2c_0_controller.id = i2c_idx++;
			iop13xx_devices[plat_idx++] =
				&iop13xx_i2c_0_controller;
			break;
		case IOP13XX_INIT_I2C_1:
			iop13xx_i2c_1_controller.id = i2c_idx++;
			iop13xx_devices[plat_idx++] =
				&iop13xx_i2c_1_controller;
			break;
		case IOP13XX_INIT_I2C_2:
			iop13xx_i2c_2_controller.id = i2c_idx++;
			iop13xx_devices[plat_idx++] =
				&iop13xx_i2c_2_controller;
			break;
		}
	}

#ifdef CONFIG_MTD_PHYSMAP
	iq8134x_flash_resource.end = iq8134x_flash_resource.start +
				iq8134x_probe_flash_size() - 1;
	if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
		iop13xx_devices[plat_idx++] = &iq8134x_flash;
	else
		printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
#endif

	platform_add_devices(iop13xx_devices, plat_idx);
}

static int __init iop13xx_init_uart_setup(char *str)
{
	if (str) {
		while (*str != '\0') {
			switch(*str) {
			case '0':
				init_uart |= IOP13XX_INIT_UART_0;
				break;
			case '1':
				init_uart |= IOP13XX_INIT_UART_1;
				break;
			case ',':
			case '=':
				break;
			default:
				PRINTK("\"iop13xx_init_uart\" malformed"
					    " at character: \'%c\'", *str);
				*(str + 1) = '\0';
				init_uart = IOP13XX_INIT_UART_DEFAULT;
			}
			str++;
		}
	}
	return 1;
}

static int __init iop13xx_init_i2c_setup(char *str)
{
	if (str) {
		while (*str != '\0') {
			switch(*str) {
			case '0':
				init_i2c |= IOP13XX_INIT_I2C_0;
				break;
			case '1':
				init_i2c |= IOP13XX_INIT_I2C_1;
				break;
			case '2':
				init_i2c |= IOP13XX_INIT_I2C_2;
				break;
			case ',':
			case '=':
				break;
			default:
				PRINTK("\"iop13xx_init_i2c\" malformed"
					    " at character: \'%c\'", *str);
				*(str + 1) = '\0';
				init_i2c = IOP13XX_INIT_I2C_DEFAULT;
			}
			str++;
		}
	}
	return 1;
}

__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
Commit	Line	Data
285f5fa7 DW	1	/*
	2	* iop13xx platform Initialization
	3	* Copyright (c) 2005-2006, Intel Corporation.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
	16	* Place - Suite 330, Boston, MA 02111-1307 USA.
	17	*
	18	*/
	19
	20	#include <linux/serial_8250.h>
	21	#ifdef CONFIG_MTD_PHYSMAP
	22	#include <linux/mtd/physmap.h>
	23	#endif
	24	#include <asm/mach/map.h>
	25	#include <asm/hardware.h>
	26	#include <asm/irq.h>
6a32b935	27	#include <asm/io.h>
285f5fa7 DW	28
	29	#define IOP13XX_UART_XTAL 33334000
	30	#define IOP13XX_SETUP_DEBUG 0
	31	#define PRINTK(x...) ((void)(IOP13XX_SETUP_DEBUG && printk(x)))
	32
	33	/* Standard IO mapping for all IOP13XX based systems
	34	*/
	35	static struct map_desc iop13xx_std_desc[] __initdata = {
	36	{ /* mem mapped registers */
	37	.virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
	38	.pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
	39	.length = IOP13XX_PMMR_SIZE,
	40	.type = MT_DEVICE,
	41	}, { /* PCIE IO space */
	42	.virtual = IOP13XX_PCIE_LOWER_IO_VA,
	43	.pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
	44	.length = IOP13XX_PCIX_IO_WINDOW_SIZE,
	45	.type = MT_DEVICE,
	46	}, { /* PCIX IO space */
	47	.virtual = IOP13XX_PCIX_LOWER_IO_VA,
	48	.pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
	49	.length = IOP13XX_PCIX_IO_WINDOW_SIZE,
	50	.type = MT_DEVICE,
	51	},
	52	};
	53
	54	static struct resource iop13xx_uart0_resources[] = {
	55	[0] = {
	56	.start = IOP13XX_UART0_PHYS,
	57	.end = IOP13XX_UART0_PHYS + 0x3f,
	58	.flags = IORESOURCE_MEM,
	59	},
	60	[1] = {
	61	.start = IRQ_IOP13XX_UART0,
	62	.end = IRQ_IOP13XX_UART0,
	63	.flags = IORESOURCE_IRQ
	64	}
	65	};
	66
	67	static struct resource iop13xx_uart1_resources[] = {
	68	[0] = {
	69	.start = IOP13XX_UART1_PHYS,
	70	.end = IOP13XX_UART1_PHYS + 0x3f,
	71	.flags = IORESOURCE_MEM,
	72	},
	73	[1] = {
	74	.start = IRQ_IOP13XX_UART1,
	75	.end = IRQ_IOP13XX_UART1,
	76	.flags = IORESOURCE_IRQ
	77	}
	78	};
	79
	80	static struct plat_serial8250_port iop13xx_uart0_data[] = {
	81	{
	82	.membase = (char*)(IOP13XX_UART0_VIRT),
	83	.mapbase = (IOP13XX_UART0_PHYS),
	84	.irq = IRQ_IOP13XX_UART0,
	85	.uartclk = IOP13XX_UART_XTAL,
	86	.regshift = 2,
	87	.iotype = UPIO_MEM,
	88	.flags = UPF_SKIP_TEST,
	89	},
	90	{ },
	91	};
92
93	static struct plat_serial8250_port iop13xx_uart1_data[] = {
94	{
95	.membase = (char*)(IOP13XX_UART1_VIRT),
96	.mapbase = (IOP13XX_UART1_PHYS),
97	.irq = IRQ_IOP13XX_UART1,
98	.uartclk = IOP13XX_UART_XTAL,
99	.regshift = 2,
100	.iotype = UPIO_MEM,
101	.flags = UPF_SKIP_TEST,
102	},
103	{ },
104	};
105
106	/* The ids are fixed up later in iop13xx_platform_init */
107	static struct platform_device iop13xx_uart0 = {
108	.name = "serial8250",
109	.id = 0,
110	.dev.platform_data = iop13xx_uart0_data,
111	.num_resources = 2,
112	.resource = iop13xx_uart0_resources,
113	};
114
115	static struct platform_device iop13xx_uart1 = {
116	.name = "serial8250",
117	.id = 0,
118	.dev.platform_data = iop13xx_uart1_data,
119	.num_resources = 2,
120	.resource = iop13xx_uart1_resources
121	};
122
123	static struct resource iop13xx_i2c_0_resources[] = {
124	[0] = {
125	.start = IOP13XX_I2C0_PHYS,
126	.end = IOP13XX_I2C0_PHYS + 0x18,
127	.flags = IORESOURCE_MEM,
128	},
129	[1] = {
130	.start = IRQ_IOP13XX_I2C_0,
131	.end = IRQ_IOP13XX_I2C_0,
132	.flags = IORESOURCE_IRQ
133	}
134	};
135
136	static struct resource iop13xx_i2c_1_resources[] = {
137	[0] = {
138	.start = IOP13XX_I2C1_PHYS,
139	.end = IOP13XX_I2C1_PHYS + 0x18,
140	.flags = IORESOURCE_MEM,
141	},
142	[1] = {
143	.start = IRQ_IOP13XX_I2C_1,
144	.end = IRQ_IOP13XX_I2C_1,
145	.flags = IORESOURCE_IRQ
146	}
147	};
148
149	static struct resource iop13xx_i2c_2_resources[] = {
150	[0] = {
151	.start = IOP13XX_I2C2_PHYS,
152	.end = IOP13XX_I2C2_PHYS + 0x18,
153	.flags = IORESOURCE_MEM,
154	},
155	[1] = {
156	.start = IRQ_IOP13XX_I2C_2,
157	.end = IRQ_IOP13XX_I2C_2,
158	.flags = IORESOURCE_IRQ
159	}
160	};
161
162	/* I2C controllers. The IOP13XX uses the same block as the IOP3xx, so
163	* we just use the same device name.
164	*/
165
166	/* The ids are fixed up later in iop13xx_platform_init */
167	static struct platform_device iop13xx_i2c_0_controller = {
168	.name = "IOP3xx-I2C",
169	.id = 0,
170	.num_resources = 2,
171	.resource = iop13xx_i2c_0_resources
172	};
173
174	static struct platform_device iop13xx_i2c_1_controller = {
175	.name = "IOP3xx-I2C",
176	.id = 0,
177	.num_resources = 2,
178	.resource = iop13xx_i2c_1_resources
179	};
180
181	static struct platform_device iop13xx_i2c_2_controller = {
182	.name = "IOP3xx-I2C",
183	.id = 0,
184	.num_resources = 2,
185	.resource = iop13xx_i2c_2_resources
186	};
187
188	#ifdef CONFIG_MTD_PHYSMAP
189	/* PBI Flash Device
190	*/
191	static struct physmap_flash_data iq8134x_flash_data = {
192	.width = 2,
193	};
194
195	static struct resource iq8134x_flash_resource = {
196	.start = IQ81340_FLASHBASE,
197	.end = 0,
198	.flags = IORESOURCE_MEM,
199	};
200
201	static struct platform_device iq8134x_flash = {
202	.name = "physmap-flash",
203	.id = 0,
204	.dev = { .platform_data = &iq8134x_flash_data, },
205	.num_resources = 1,
206	.resource = &iq8134x_flash_resource,
207	};
208
209	static unsigned long iq8134x_probe_flash_size(void)
210	{
211	uint8_t __iomem *flash_addr = ioremap(IQ81340_FLASHBASE, PAGE_SIZE);
212	int i;
213	char query[3];
214	unsigned long size = 0;
215	int width = iq8134x_flash_data.width;
216
217	if (flash_addr) {
218	/* send CFI 'query' command */
219	writew(0x98, flash_addr);
220
221	/* check for CFI compliance */
222	for (i = 0; i < 3 * width; i += width)
223	query[i / width] = readb(flash_addr + (0x10 * width) + i);
224
225	/* read the size */
226	if (memcmp(query, "QRY", 3) == 0)
227	size = 1 << readb(flash_addr + (0x27 * width));
228
229	/* send CFI 'read array' command */
230	writew(0xff, flash_addr);
231
232	iounmap(flash_addr);
233	}
234
235	return size;
236	}
237	#endif
238
239	void __init iop13xx_map_io(void)
240	{
241	/* Initialize the Static Page Table maps */
242	iotable_init(iop13xx_std_desc, ARRAY_SIZE(iop13xx_std_desc));
243	}
244
245	static int init_uart = 0;
246	static int init_i2c = 0;
247
248	void __init iop13xx_platform_init(void)
249	{
250	int i;
251	u32 uart_idx, i2c_idx, plat_idx;
252	struct platform_device *iop13xx_devices[IQ81340_MAX_PLAT_DEVICES];
253
254	/* set the bases so we can read the device id */
255	iop13xx_set_atu_mmr_bases();
256
257	memset(iop13xx_devices, 0, sizeof(iop13xx_devices));
258
259	if (init_uart == IOP13XX_INIT_UART_DEFAULT) {
260	switch (iop13xx_dev_id()) {
261	/* enable both uarts on iop341 and iop342 */
262	case 0x3380:
263	case 0x3384:
264	case 0x3388:
265	case 0x338c:
266	case 0x3382:
267	case 0x3386:
268	case 0x338a:
269	case 0x338e:
270	init_uart \|= IOP13XX_INIT_UART_0;
271	init_uart \|= IOP13XX_INIT_UART_1;
272	break;
273	/* only enable uart 1 */
274	default:
275	init_uart \|= IOP13XX_INIT_UART_1;
276	}
277	}
278
279	if (init_i2c == IOP13XX_INIT_I2C_DEFAULT) {
280	switch (iop13xx_dev_id()) {
281	/* enable all i2c units on iop341 and iop342 */
282	case 0x3380:
283	case 0x3384:
284	case 0x3388:
285	case 0x338c:
286	case 0x3382:
287	case 0x3386:
288	case 0x338a:
289	case 0x338e:
290	init_i2c \|= IOP13XX_INIT_I2C_0;
291	init_i2c \|= IOP13XX_INIT_I2C_1;
292	init_i2c \|= IOP13XX_INIT_I2C_2;
293	break;
294	/* only enable i2c 1 and 2 */
295	default:
296	init_i2c \|= IOP13XX_INIT_I2C_1;
297	init_i2c \|= IOP13XX_INIT_I2C_2;
298	}
299	}
300
301	plat_idx = 0;
302	uart_idx = 0;
303	i2c_idx = 0;
304
305	/* uart 1 (if enabled) is ttyS0 */
306	if (init_uart & IOP13XX_INIT_UART_1) {
307	PRINTK("Adding uart1 to platform device list\n");
308	iop13xx_uart1.id = uart_idx++;
309	iop13xx_devices[plat_idx++] = &iop13xx_uart1;
310	}
311	if (init_uart & IOP13XX_INIT_UART_0) {
312	PRINTK("Adding uart0 to platform device list\n");
313	iop13xx_uart0.id = uart_idx++;
314	iop13xx_devices[plat_idx++] = &iop13xx_uart0;
315	}
316
317	for(i = 0; i < IQ81340_NUM_I2C; i++) {
318	if ((init_i2c & (1 << i)) && IOP13XX_SETUP_DEBUG)
319	printk("Adding i2c%d to platform device list\n", i);
320	switch(init_i2c & (1 << i)) {
321	case IOP13XX_INIT_I2C_0:
322	iop13xx_i2c_0_controller.id = i2c_idx++;
323	iop13xx_devices[plat_idx++] =
324	&iop13xx_i2c_0_controller;
325	break;
326	case IOP13XX_INIT_I2C_1:
327	iop13xx_i2c_1_controller.id = i2c_idx++;
328	iop13xx_devices[plat_idx++] =
329	&iop13xx_i2c_1_controller;
330	break;
331	case IOP13XX_INIT_I2C_2:
332	iop13xx_i2c_2_controller.id = i2c_idx++;
333	iop13xx_devices[plat_idx++] =
334	&iop13xx_i2c_2_controller;
335	break;
336	}
337	}
338
339	#ifdef CONFIG_MTD_PHYSMAP
340	iq8134x_flash_resource.end = iq8134x_flash_resource.start +
ab9d90db	341	iq8134x_probe_flash_size() - 1;
285f5fa7 DW	342	if (iq8134x_flash_resource.end > iq8134x_flash_resource.start)
	343	iop13xx_devices[plat_idx++] = &iq8134x_flash;
	344	else
	345	printk(KERN_ERR "%s: Failed to probe flash size\n", __FUNCTION__);
	346	#endif
	347
	348	platform_add_devices(iop13xx_devices, plat_idx);
	349	}
	350
	351	static int __init iop13xx_init_uart_setup(char *str)
	352	{
	353	if (str) {
	354	while (*str != '\0') {
	355	switch(*str) {
	356	case '0':
	357	init_uart \|= IOP13XX_INIT_UART_0;
	358	break;
	359	case '1':
	360	init_uart \|= IOP13XX_INIT_UART_1;
	361	break;
	362	case ',':
	363	case '=':
	364	break;
	365	default:
	366	PRINTK("\"iop13xx_init_uart\" malformed"
	367	" at character: \'%c\'", *str);
	368	*(str + 1) = '\0';
	369	init_uart = IOP13XX_INIT_UART_DEFAULT;
	370	}
	371	str++;
	372	}
	373	}
	374	return 1;
	375	}
	376
	377	static int __init iop13xx_init_i2c_setup(char *str)
	378	{
	379	if (str) {
	380	while (*str != '\0') {
	381	switch(*str) {
	382	case '0':
	383	init_i2c \|= IOP13XX_INIT_I2C_0;
	384	break;
	385	case '1':
	386	init_i2c \|= IOP13XX_INIT_I2C_1;
	387	break;
	388	case '2':
	389	init_i2c \|= IOP13XX_INIT_I2C_2;
	390	break;
	391	case ',':
	392	case '=':
	393	break;
	394	default:
	395	PRINTK("\"iop13xx_init_i2c\" malformed"
	396	" at character: \'%c\'", *str);
	397	*(str + 1) = '\0';
	398	init_i2c = IOP13XX_INIT_I2C_DEFAULT;
	399	}
	400	str++;
	401	}
	402	}
	403	return 1;
	404	}
	405
406	__setup("iop13xx_init_uart", iop13xx_init_uart_setup);
407	__setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);