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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
11c79740 KH |
2 | /* |
3 | * Goramo MultiLink router platform code | |
4 | * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl> | |
5 | */ | |
6 | ||
7 | #include <linux/delay.h> | |
e1a4018f | 8 | #include <linux/gpio.h> |
11c79740 KH |
9 | #include <linux/hdlc.h> |
10 | #include <linux/i2c-gpio.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/irq.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/serial_8250.h> | |
16 | #include <asm/mach-types.h> | |
11c79740 KH |
17 | #include <asm/mach/arch.h> |
18 | #include <asm/mach/flash.h> | |
19 | #include <asm/mach/pci.h> | |
3043c5c8 | 20 | #include <asm/system_info.h> |
11c79740 | 21 | |
11c79740 KH |
22 | #define SLOT_ETHA 0x0B /* IDSEL = AD21 */ |
23 | #define SLOT_ETHB 0x0C /* IDSEL = AD20 */ | |
24 | #define SLOT_MPCI 0x0D /* IDSEL = AD19 */ | |
25 | #define SLOT_NEC 0x0E /* IDSEL = AD18 */ | |
26 | ||
11c79740 KH |
27 | /* GPIO lines */ |
28 | #define GPIO_SCL 0 | |
29 | #define GPIO_SDA 1 | |
30 | #define GPIO_STR 2 | |
8d3fdf31 KH |
31 | #define GPIO_IRQ_NEC 3 |
32 | #define GPIO_IRQ_ETHA 4 | |
33 | #define GPIO_IRQ_ETHB 5 | |
11c79740 KH |
34 | #define GPIO_HSS0_DCD_N 6 |
35 | #define GPIO_HSS1_DCD_N 7 | |
8d3fdf31 KH |
36 | #define GPIO_UART0_DCD 8 |
37 | #define GPIO_UART1_DCD 9 | |
11c79740 KH |
38 | #define GPIO_HSS0_CTS_N 10 |
39 | #define GPIO_HSS1_CTS_N 11 | |
8d3fdf31 | 40 | #define GPIO_IRQ_MPCI 12 |
11c79740 KH |
41 | #define GPIO_HSS1_RTS_N 13 |
42 | #define GPIO_HSS0_RTS_N 14 | |
8d3fdf31 | 43 | /* GPIO15 is not connected */ |
11c79740 KH |
44 | |
45 | /* Control outputs from 74HC4094 */ | |
46 | #define CONTROL_HSS0_CLK_INT 0 | |
47 | #define CONTROL_HSS1_CLK_INT 1 | |
48 | #define CONTROL_HSS0_DTR_N 2 | |
49 | #define CONTROL_HSS1_DTR_N 3 | |
50 | #define CONTROL_EXT 4 | |
51 | #define CONTROL_AUTO_RESET 5 | |
52 | #define CONTROL_PCI_RESET_N 6 | |
53 | #define CONTROL_EEPROM_WC_N 7 | |
54 | ||
55 | /* offsets from start of flash ROM = 0x50000000 */ | |
56 | #define CFG_ETH0_ADDRESS 0x40 /* 6 bytes */ | |
57 | #define CFG_ETH1_ADDRESS 0x46 /* 6 bytes */ | |
58 | #define CFG_REV 0x4C /* u32 */ | |
59 | #define CFG_SDRAM_SIZE 0x50 /* u32 */ | |
60 | #define CFG_SDRAM_CONF 0x54 /* u32 */ | |
61 | #define CFG_SDRAM_MODE 0x58 /* u32 */ | |
62 | #define CFG_SDRAM_REFRESH 0x5C /* u32 */ | |
63 | ||
64 | #define CFG_HW_BITS 0x60 /* u32 */ | |
65 | #define CFG_HW_USB_PORTS 0x00000007 /* 0 = no NEC chip, 1-5 = ports # */ | |
66 | #define CFG_HW_HAS_PCI_SLOT 0x00000008 | |
67 | #define CFG_HW_HAS_ETH0 0x00000010 | |
68 | #define CFG_HW_HAS_ETH1 0x00000020 | |
69 | #define CFG_HW_HAS_HSS0 0x00000040 | |
70 | #define CFG_HW_HAS_HSS1 0x00000080 | |
71 | #define CFG_HW_HAS_UART0 0x00000100 | |
72 | #define CFG_HW_HAS_UART1 0x00000200 | |
73 | #define CFG_HW_HAS_EEPROM 0x00000400 | |
74 | ||
75 | #define FLASH_CMD_READ_ARRAY 0xFF | |
76 | #define FLASH_CMD_READ_ID 0x90 | |
77 | #define FLASH_SER_OFF 0x102 /* 0x81 in 16-bit mode */ | |
78 | ||
79 | static u32 hw_bits = 0xFFFFFFFD; /* assume all hardware present */; | |
80 | static u8 control_value; | |
81 | ||
82 | static void set_scl(u8 value) | |
83 | { | |
e1a4018f | 84 | gpio_set_value(GPIO_SCL, !!value); |
11c79740 KH |
85 | udelay(3); |
86 | } | |
87 | ||
88 | static void set_sda(u8 value) | |
89 | { | |
e1a4018f | 90 | gpio_set_value(GPIO_SDA, !!value); |
11c79740 KH |
91 | udelay(3); |
92 | } | |
93 | ||
94 | static void set_str(u8 value) | |
95 | { | |
e1a4018f | 96 | gpio_set_value(GPIO_STR, !!value); |
11c79740 KH |
97 | udelay(3); |
98 | } | |
99 | ||
100 | static inline void set_control(int line, int value) | |
101 | { | |
102 | if (value) | |
103 | control_value |= (1 << line); | |
104 | else | |
105 | control_value &= ~(1 << line); | |
106 | } | |
107 | ||
108 | ||
109 | static void output_control(void) | |
110 | { | |
111 | int i; | |
112 | ||
e1a4018f KH |
113 | gpio_direction_output(GPIO_SCL, 1); |
114 | gpio_direction_output(GPIO_SDA, 1); | |
11c79740 KH |
115 | |
116 | for (i = 0; i < 8; i++) { | |
117 | set_scl(0); | |
118 | set_sda(control_value & (0x80 >> i)); /* MSB first */ | |
119 | set_scl(1); /* active edge */ | |
120 | } | |
121 | ||
122 | set_str(1); | |
123 | set_str(0); | |
124 | ||
125 | set_scl(0); | |
126 | set_sda(1); /* Be ready for START */ | |
127 | set_scl(1); | |
128 | } | |
129 | ||
130 | ||
131 | static void (*set_carrier_cb_tab[2])(void *pdev, int carrier); | |
132 | ||
133 | static int hss_set_clock(int port, unsigned int clock_type) | |
134 | { | |
135 | int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT; | |
136 | ||
137 | switch (clock_type) { | |
138 | case CLOCK_DEFAULT: | |
139 | case CLOCK_EXT: | |
140 | set_control(ctrl_int, 0); | |
141 | output_control(); | |
142 | return CLOCK_EXT; | |
143 | ||
144 | case CLOCK_INT: | |
145 | set_control(ctrl_int, 1); | |
146 | output_control(); | |
147 | return CLOCK_INT; | |
148 | ||
149 | default: | |
150 | return -EINVAL; | |
151 | } | |
152 | } | |
153 | ||
154 | static irqreturn_t hss_dcd_irq(int irq, void *pdev) | |
155 | { | |
e1a4018f KH |
156 | int port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N)); |
157 | int i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N); | |
11c79740 KH |
158 | set_carrier_cb_tab[port](pdev, !i); |
159 | return IRQ_HANDLED; | |
160 | } | |
161 | ||
162 | ||
163 | static int hss_open(int port, void *pdev, | |
164 | void (*set_carrier_cb)(void *pdev, int carrier)) | |
165 | { | |
166 | int i, irq; | |
167 | ||
168 | if (!port) | |
8d3fdf31 | 169 | irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N); |
11c79740 | 170 | else |
8d3fdf31 | 171 | irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N); |
11c79740 | 172 | |
e1a4018f | 173 | i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N); |
11c79740 KH |
174 | set_carrier_cb(pdev, !i); |
175 | ||
176 | set_carrier_cb_tab[!!port] = set_carrier_cb; | |
177 | ||
178 | if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) { | |
179 | printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n", | |
180 | irq, i); | |
181 | return i; | |
182 | } | |
183 | ||
184 | set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0); | |
185 | output_control(); | |
e1a4018f | 186 | gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0); |
11c79740 KH |
187 | return 0; |
188 | } | |
189 | ||
190 | static void hss_close(int port, void *pdev) | |
191 | { | |
8d3fdf31 KH |
192 | free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) : |
193 | IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev); | |
11c79740 KH |
194 | set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ |
195 | ||
196 | set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); | |
197 | output_control(); | |
e1a4018f | 198 | gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1); |
11c79740 KH |
199 | } |
200 | ||
201 | ||
202 | /* Flash memory */ | |
203 | static struct flash_platform_data flash_data = { | |
204 | .map_name = "cfi_probe", | |
205 | .width = 2, | |
206 | }; | |
207 | ||
208 | static struct resource flash_resource = { | |
209 | .flags = IORESOURCE_MEM, | |
210 | }; | |
211 | ||
212 | static struct platform_device device_flash = { | |
213 | .name = "IXP4XX-Flash", | |
214 | .id = 0, | |
215 | .dev = { .platform_data = &flash_data }, | |
216 | .num_resources = 1, | |
217 | .resource = &flash_resource, | |
218 | }; | |
219 | ||
220 | ||
221 | /* I^2C interface */ | |
222 | static struct i2c_gpio_platform_data i2c_data = { | |
223 | .sda_pin = GPIO_SDA, | |
224 | .scl_pin = GPIO_SCL, | |
225 | }; | |
226 | ||
227 | static struct platform_device device_i2c = { | |
228 | .name = "i2c-gpio", | |
229 | .id = 0, | |
230 | .dev = { .platform_data = &i2c_data }, | |
231 | }; | |
232 | ||
233 | ||
234 | /* IXP425 2 UART ports */ | |
235 | static struct resource uart_resources[] = { | |
236 | { | |
237 | .start = IXP4XX_UART1_BASE_PHYS, | |
238 | .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, | |
239 | .flags = IORESOURCE_MEM, | |
240 | }, | |
241 | { | |
242 | .start = IXP4XX_UART2_BASE_PHYS, | |
243 | .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, | |
244 | .flags = IORESOURCE_MEM, | |
245 | } | |
246 | }; | |
247 | ||
248 | static struct plat_serial8250_port uart_data[] = { | |
249 | { | |
250 | .mapbase = IXP4XX_UART1_BASE_PHYS, | |
251 | .membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT + | |
252 | REG_OFFSET, | |
253 | .irq = IRQ_IXP4XX_UART1, | |
254 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | |
255 | .iotype = UPIO_MEM, | |
256 | .regshift = 2, | |
257 | .uartclk = IXP4XX_UART_XTAL, | |
258 | }, | |
259 | { | |
260 | .mapbase = IXP4XX_UART2_BASE_PHYS, | |
261 | .membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT + | |
262 | REG_OFFSET, | |
263 | .irq = IRQ_IXP4XX_UART2, | |
264 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, | |
265 | .iotype = UPIO_MEM, | |
266 | .regshift = 2, | |
267 | .uartclk = IXP4XX_UART_XTAL, | |
268 | }, | |
269 | { }, | |
270 | }; | |
271 | ||
272 | static struct platform_device device_uarts = { | |
273 | .name = "serial8250", | |
274 | .id = PLAT8250_DEV_PLATFORM, | |
275 | .dev.platform_data = uart_data, | |
276 | .num_resources = 2, | |
277 | .resource = uart_resources, | |
278 | }; | |
279 | ||
280 | ||
281 | /* Built-in 10/100 Ethernet MAC interfaces */ | |
282 | static struct eth_plat_info eth_plat[] = { | |
283 | { | |
284 | .phy = 0, | |
285 | .rxq = 3, | |
286 | .txreadyq = 32, | |
287 | }, { | |
288 | .phy = 1, | |
289 | .rxq = 4, | |
290 | .txreadyq = 33, | |
291 | } | |
292 | }; | |
293 | ||
294 | static struct platform_device device_eth_tab[] = { | |
295 | { | |
296 | .name = "ixp4xx_eth", | |
297 | .id = IXP4XX_ETH_NPEB, | |
298 | .dev.platform_data = eth_plat, | |
299 | }, { | |
300 | .name = "ixp4xx_eth", | |
301 | .id = IXP4XX_ETH_NPEC, | |
302 | .dev.platform_data = eth_plat + 1, | |
303 | } | |
304 | }; | |
305 | ||
306 | ||
307 | /* IXP425 2 synchronous serial ports */ | |
308 | static struct hss_plat_info hss_plat[] = { | |
309 | { | |
310 | .set_clock = hss_set_clock, | |
311 | .open = hss_open, | |
312 | .close = hss_close, | |
313 | .txreadyq = 34, | |
314 | }, { | |
315 | .set_clock = hss_set_clock, | |
316 | .open = hss_open, | |
317 | .close = hss_close, | |
318 | .txreadyq = 35, | |
319 | } | |
320 | }; | |
321 | ||
322 | static struct platform_device device_hss_tab[] = { | |
323 | { | |
324 | .name = "ixp4xx_hss", | |
325 | .id = 0, | |
326 | .dev.platform_data = hss_plat, | |
327 | }, { | |
328 | .name = "ixp4xx_hss", | |
329 | .id = 1, | |
330 | .dev.platform_data = hss_plat + 1, | |
331 | } | |
332 | }; | |
333 | ||
334 | ||
87ba5c6a | 335 | static struct platform_device *device_tab[7] __initdata = { |
11c79740 KH |
336 | &device_flash, /* index 0 */ |
337 | }; | |
338 | ||
339 | static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr) | |
340 | { | |
341 | #ifdef __ARMEB__ | |
342 | return __raw_readb(flash + addr); | |
343 | #else | |
344 | return __raw_readb(flash + (addr ^ 3)); | |
345 | #endif | |
346 | } | |
347 | ||
348 | static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr) | |
349 | { | |
350 | #ifdef __ARMEB__ | |
351 | return __raw_readw(flash + addr); | |
352 | #else | |
353 | return __raw_readw(flash + (addr ^ 2)); | |
354 | #endif | |
355 | } | |
356 | ||
357 | static void __init gmlr_init(void) | |
358 | { | |
359 | u8 __iomem *flash; | |
360 | int i, devices = 1; /* flash */ | |
361 | ||
362 | ixp4xx_sys_init(); | |
363 | ||
364 | if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL) | |
365 | printk(KERN_ERR "goramo-mlr: unable to access system" | |
366 | " configuration data\n"); | |
367 | else { | |
368 | system_rev = __raw_readl(flash + CFG_REV); | |
369 | hw_bits = __raw_readl(flash + CFG_HW_BITS); | |
370 | ||
371 | for (i = 0; i < ETH_ALEN; i++) { | |
372 | eth_plat[0].hwaddr[i] = | |
373 | flash_readb(flash, CFG_ETH0_ADDRESS + i); | |
374 | eth_plat[1].hwaddr[i] = | |
375 | flash_readb(flash, CFG_ETH1_ADDRESS + i); | |
376 | } | |
377 | ||
378 | __raw_writew(FLASH_CMD_READ_ID, flash); | |
379 | system_serial_high = flash_readw(flash, FLASH_SER_OFF); | |
380 | system_serial_high <<= 16; | |
381 | system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2); | |
382 | system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4); | |
383 | system_serial_low <<= 16; | |
384 | system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6); | |
385 | __raw_writew(FLASH_CMD_READ_ARRAY, flash); | |
386 | ||
387 | iounmap(flash); | |
388 | } | |
389 | ||
390 | switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) { | |
391 | case CFG_HW_HAS_UART0: | |
392 | memset(&uart_data[1], 0, sizeof(uart_data[1])); | |
393 | device_uarts.num_resources = 1; | |
394 | break; | |
395 | ||
396 | case CFG_HW_HAS_UART1: | |
397 | device_uarts.dev.platform_data = &uart_data[1]; | |
398 | device_uarts.resource = &uart_resources[1]; | |
399 | device_uarts.num_resources = 1; | |
400 | break; | |
401 | } | |
402 | if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) | |
403 | device_tab[devices++] = &device_uarts; /* max index 1 */ | |
404 | ||
405 | if (hw_bits & CFG_HW_HAS_ETH0) | |
406 | device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */ | |
407 | if (hw_bits & CFG_HW_HAS_ETH1) | |
408 | device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */ | |
409 | ||
410 | if (hw_bits & CFG_HW_HAS_HSS0) | |
411 | device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */ | |
412 | if (hw_bits & CFG_HW_HAS_HSS1) | |
413 | device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */ | |
414 | ||
415 | if (hw_bits & CFG_HW_HAS_EEPROM) | |
416 | device_tab[devices++] = &device_i2c; /* max index 6 */ | |
417 | ||
e1a4018f KH |
418 | gpio_request(GPIO_SCL, "SCL/clock"); |
419 | gpio_request(GPIO_SDA, "SDA/data"); | |
420 | gpio_request(GPIO_STR, "strobe"); | |
421 | gpio_request(GPIO_HSS0_RTS_N, "HSS0 RTS"); | |
422 | gpio_request(GPIO_HSS1_RTS_N, "HSS1 RTS"); | |
423 | gpio_request(GPIO_HSS0_DCD_N, "HSS0 DCD"); | |
424 | gpio_request(GPIO_HSS1_DCD_N, "HSS1 DCD"); | |
425 | ||
426 | gpio_direction_output(GPIO_SCL, 1); | |
427 | gpio_direction_output(GPIO_SDA, 1); | |
428 | gpio_direction_output(GPIO_STR, 0); | |
429 | gpio_direction_output(GPIO_HSS0_RTS_N, 1); | |
430 | gpio_direction_output(GPIO_HSS1_RTS_N, 1); | |
431 | gpio_direction_input(GPIO_HSS0_DCD_N); | |
432 | gpio_direction_input(GPIO_HSS1_DCD_N); | |
6845664a TG |
433 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); |
434 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); | |
11c79740 KH |
435 | |
436 | set_control(CONTROL_HSS0_DTR_N, 1); | |
437 | set_control(CONTROL_HSS1_DTR_N, 1); | |
438 | set_control(CONTROL_EEPROM_WC_N, 1); | |
439 | set_control(CONTROL_PCI_RESET_N, 1); | |
440 | output_control(); | |
441 | ||
442 | msleep(1); /* Wait for PCI devices to initialize */ | |
443 | ||
444 | flash_resource.start = IXP4XX_EXP_BUS_BASE(0); | |
445 | flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; | |
446 | ||
447 | platform_add_devices(device_tab, devices); | |
448 | } | |
449 | ||
450 | ||
451 | #ifdef CONFIG_PCI | |
452 | static void __init gmlr_pci_preinit(void) | |
453 | { | |
6845664a TG |
454 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); |
455 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); | |
456 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); | |
457 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); | |
11c79740 KH |
458 | ixp4xx_pci_preinit(); |
459 | } | |
460 | ||
461 | static void __init gmlr_pci_postinit(void) | |
462 | { | |
463 | if ((hw_bits & CFG_HW_USB_PORTS) >= 2 && | |
464 | (hw_bits & CFG_HW_USB_PORTS) < 5) { | |
465 | /* need to adjust number of USB ports on NEC chip */ | |
466 | u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0; | |
467 | if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) { | |
468 | value &= ~7; | |
469 | value |= (hw_bits & CFG_HW_USB_PORTS); | |
470 | ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value); | |
471 | } | |
472 | } | |
473 | } | |
474 | ||
d5341942 | 475 | static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
11c79740 KH |
476 | { |
477 | switch(slot) { | |
8d3fdf31 KH |
478 | case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA); |
479 | case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB); | |
480 | case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC); | |
481 | default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI); | |
11c79740 KH |
482 | } |
483 | } | |
484 | ||
485 | static struct hw_pci gmlr_hw_pci __initdata = { | |
486 | .nr_controllers = 1, | |
c23bfc38 | 487 | .ops = &ixp4xx_ops, |
11c79740 KH |
488 | .preinit = gmlr_pci_preinit, |
489 | .postinit = gmlr_pci_postinit, | |
11c79740 | 490 | .setup = ixp4xx_setup, |
11c79740 KH |
491 | .map_irq = gmlr_map_irq, |
492 | }; | |
493 | ||
494 | static int __init gmlr_pci_init(void) | |
495 | { | |
496 | if (machine_is_goramo_mlr() && | |
497 | (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT))) | |
498 | pci_common_init(&gmlr_hw_pci); | |
499 | return 0; | |
500 | } | |
501 | ||
502 | subsys_initcall(gmlr_pci_init); | |
503 | #endif /* CONFIG_PCI */ | |
504 | ||
505 | ||
506 | MACHINE_START(GORAMO_MLR, "MultiLink") | |
507 | /* Maintainer: Krzysztof Halasa */ | |
11c79740 | 508 | .map_io = ixp4xx_map_io, |
f449588c | 509 | .init_early = ixp4xx_init_early, |
11c79740 | 510 | .init_irq = ixp4xx_init_irq, |
6bb27d73 | 511 | .init_time = ixp4xx_timer_init, |
e022c729 | 512 | .atag_offset = 0x100, |
11c79740 | 513 | .init_machine = gmlr_init, |
7553ee77 NP |
514 | #if defined(CONFIG_PCI) |
515 | .dma_zone_size = SZ_64M, | |
516 | #endif | |
d1b860fb | 517 | .restart = ixp4xx_restart, |
11c79740 | 518 | MACHINE_END |