[thirdparty/u-boot.git] / arch / arm / mach-keystone / include / mach / hardware-k2hk.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * K2HK: SoC definitions
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 */

#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H

#define KS2_ARM_PLL_EN			BIT(13)

/* PA SS Registers */
#define KS2_PASS_BASE			0x02000000

/* Power and Sleep Controller (PSC) Domains */
#define KS2_LPSC_MOD			0
#define KS2_LPSC_DUMMY1			1
#define KS2_LPSC_USB			2
#define KS2_LPSC_EMIF25_SPI		3
#define KS2_LPSC_TSIP			4
#define KS2_LPSC_DEBUGSS_TRC		5
#define KS2_LPSC_TETB_TRC		6
#define KS2_LPSC_PKTPROC		7
#define KS2_LPSC_PA			KS2_LPSC_PKTPROC
#define KS2_LPSC_SGMII			8
#define KS2_LPSC_CPGMAC			KS2_LPSC_SGMII
#define KS2_LPSC_CRYPTO			9
#define KS2_LPSC_PCIE			10
#define KS2_LPSC_SRIO			11
#define KS2_LPSC_VUSR0			12
#define KS2_LPSC_CHIP_SRSS		13
#define KS2_LPSC_MSMC			14
#define KS2_LPSC_GEM_1			16
#define KS2_LPSC_GEM_2			17
#define KS2_LPSC_GEM_3			18
#define KS2_LPSC_GEM_4			19
#define KS2_LPSC_GEM_5			20
#define KS2_LPSC_GEM_6			21
#define KS2_LPSC_GEM_7			22
#define KS2_LPSC_EMIF4F_DDR3A		23
#define KS2_LPSC_EMIF4F_DDR3B		24
#define KS2_LPSC_TAC			25
#define KS2_LPSC_RAC			26
#define KS2_LPSC_RAC_1			27
#define KS2_LPSC_FFTC_A			28
#define KS2_LPSC_FFTC_B			29
#define KS2_LPSC_FFTC_C			30
#define KS2_LPSC_FFTC_D			31
#define KS2_LPSC_FFTC_E			32
#define KS2_LPSC_FFTC_F			33
#define KS2_LPSC_AI2			34
#define KS2_LPSC_TCP3D_0		35
#define KS2_LPSC_TCP3D_1		36
#define KS2_LPSC_TCP3D_2		37
#define KS2_LPSC_TCP3D_3		38
#define KS2_LPSC_VCP2X4_A		39
#define KS2_LPSC_CP2X4_B		40
#define KS2_LPSC_VCP2X4_C		41
#define KS2_LPSC_VCP2X4_D		42
#define KS2_LPSC_VCP2X4_E		43
#define KS2_LPSC_VCP2X4_F		44
#define KS2_LPSC_VCP2X4_G		45
#define KS2_LPSC_VCP2X4_H		46
#define KS2_LPSC_BCP			47
#define KS2_LPSC_DXB			48
#define KS2_LPSC_VUSR1			49
#define KS2_LPSC_XGE			50
#define KS2_LPSC_ARM_SREFLEX		51

/* DDR3B definitions */
#define KS2_DDR3B_EMIF_CTRL_BASE	0x21020000
#define KS2_DDR3B_EMIF_DATA_BASE	0x60000000
#define KS2_DDR3B_DDRPHYC		0x02328000

#define KS2_CIC2_DDR3_ECC_IRQ_NUM	0x0D3 /* DDR3 ECC system irq number */
#define KS2_CIC2_DDR3_ECC_CHAN_NUM	0x01D /* DDR3 ECC int mapped to CIC2
						 channel 29 */

/* SGMII SerDes */
#define KS2_LANES_PER_SGMII_SERDES	4

/* Number of DSP cores */
#define KS2_NUM_DSPS			8

/* NETCP pktdma */
#define KS2_NETCP_PDMA_CTRL_BASE	0x02004000
#define KS2_NETCP_PDMA_TX_BASE		0x02004400
#define KS2_NETCP_PDMA_TX_CH_NUM	9
#define KS2_NETCP_PDMA_RX_BASE		0x02004800
#define KS2_NETCP_PDMA_RX_CH_NUM	26
#define KS2_NETCP_PDMA_SCHED_BASE	0x02004c00
#define KS2_NETCP_PDMA_RX_FLOW_BASE	0x02005000
#define KS2_NETCP_PDMA_RX_FLOW_NUM	32
#define KS2_NETCP_PDMA_TX_SND_QUEUE	648

/* NETCP */
#define KS2_NETCP_BASE			0x02000000

#endif /* __ASM_ARCH_HARDWARE_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
ef509b90 VA	2	/*
	3	* K2HK: SoC definitions
	4	*
	5	* (C) Copyright 2012-2014
	6	* Texas Instruments Incorporated, <www.ti.com>
ef509b90	7	*/
3d315386	8
ef509b90 VA	9	#ifndef __ASM_ARCH_HARDWARE_K2HK_H
	10	#define __ASM_ARCH_HARDWARE_K2HK_H
	11
3d315386	12	#define KS2_ARM_PLL_EN BIT(13)
ef509b90	13
ef509b90	14	/* PA SS Registers */
3d315386	15	#define KS2_PASS_BASE 0x02000000
ef509b90	16
ef509b90	17	/* Power and Sleep Controller (PSC) Domains */
3d315386 KI	18	#define KS2_LPSC_MOD 0
	19	#define KS2_LPSC_DUMMY1 1
	20	#define KS2_LPSC_USB 2
	21	#define KS2_LPSC_EMIF25_SPI 3
	22	#define KS2_LPSC_TSIP 4
	23	#define KS2_LPSC_DEBUGSS_TRC 5
	24	#define KS2_LPSC_TETB_TRC 6
	25	#define KS2_LPSC_PKTPROC 7
	26	#define KS2_LPSC_PA KS2_LPSC_PKTPROC
	27	#define KS2_LPSC_SGMII 8
	28	#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
	29	#define KS2_LPSC_CRYPTO 9
	30	#define KS2_LPSC_PCIE 10
	31	#define KS2_LPSC_SRIO 11
	32	#define KS2_LPSC_VUSR0 12
	33	#define KS2_LPSC_CHIP_SRSS 13
	34	#define KS2_LPSC_MSMC 14
	35	#define KS2_LPSC_GEM_1 16
	36	#define KS2_LPSC_GEM_2 17
	37	#define KS2_LPSC_GEM_3 18
	38	#define KS2_LPSC_GEM_4 19
	39	#define KS2_LPSC_GEM_5 20
	40	#define KS2_LPSC_GEM_6 21
	41	#define KS2_LPSC_GEM_7 22
	42	#define KS2_LPSC_EMIF4F_DDR3A 23
	43	#define KS2_LPSC_EMIF4F_DDR3B 24
	44	#define KS2_LPSC_TAC 25
	45	#define KS2_LPSC_RAC 26
	46	#define KS2_LPSC_RAC_1 27
	47	#define KS2_LPSC_FFTC_A 28
	48	#define KS2_LPSC_FFTC_B 29
	49	#define KS2_LPSC_FFTC_C 30
	50	#define KS2_LPSC_FFTC_D 31
	51	#define KS2_LPSC_FFTC_E 32
	52	#define KS2_LPSC_FFTC_F 33
	53	#define KS2_LPSC_AI2 34
	54	#define KS2_LPSC_TCP3D_0 35
	55	#define KS2_LPSC_TCP3D_1 36
	56	#define KS2_LPSC_TCP3D_2 37
	57	#define KS2_LPSC_TCP3D_3 38
	58	#define KS2_LPSC_VCP2X4_A 39
	59	#define KS2_LPSC_CP2X4_B 40
	60	#define KS2_LPSC_VCP2X4_C 41
	61	#define KS2_LPSC_VCP2X4_D 42
	62	#define KS2_LPSC_VCP2X4_E 43
	63	#define KS2_LPSC_VCP2X4_F 44
	64	#define KS2_LPSC_VCP2X4_G 45
	65	#define KS2_LPSC_VCP2X4_H 46
	66	#define KS2_LPSC_BCP 47
	67	#define KS2_LPSC_DXB 48
	68	#define KS2_LPSC_VUSR1 49
	69	#define KS2_LPSC_XGE 50
	70	#define KS2_LPSC_ARM_SREFLEX 51
ef509b90	71
ef509b90	72	/* DDR3B definitions */
3d315386 KI	73	#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
	74	#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
	75	#define KS2_DDR3B_DDRPHYC 0x02328000
ef509b90	76
89f44bb0 VA	77	#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */
	78	#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2
	79	channel 29 */
	80
95f74dad HZ	81	/* SGMII SerDes */
	82	#define KS2_LANES_PER_SGMII_SERDES 4
	83
7b26c1f6 HZ	84	/* Number of DSP cores */
	85	#define KS2_NUM_DSPS 8
	86
ed948e29 KI	87	/* NETCP pktdma */
	88	#define KS2_NETCP_PDMA_CTRL_BASE 0x02004000
	89	#define KS2_NETCP_PDMA_TX_BASE 0x02004400
	90	#define KS2_NETCP_PDMA_TX_CH_NUM 9
	91	#define KS2_NETCP_PDMA_RX_BASE 0x02004800
	92	#define KS2_NETCP_PDMA_RX_CH_NUM 26
	93	#define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00
	94	#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000
	95	#define KS2_NETCP_PDMA_RX_FLOW_NUM 32
ed948e29 KI	96	#define KS2_NETCP_PDMA_TX_SND_QUEUE 648
ed948e29 KI	97
0935cac6 KI	98	/* NETCP */
0935cac6 KI	99	#define KS2_NETCP_BASE 0x02000000
e3114c9a	100
ef509b90	101	#endif /* __ASM_ARCH_HARDWARE_H */