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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
4efb77d4 PW |
2 | /* |
3 | * (C) Copyright 2009 | |
4 | * Marvell Semiconductor <www.marvell.com> | |
5 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
4efb77d4 PW |
6 | */ |
7 | ||
8 | #include <common.h> | |
288b29e4 | 9 | #include <command.h> |
9a3b4ceb | 10 | #include <cpu_func.h> |
7b51b576 | 11 | #include <env.h> |
90526e9f | 12 | #include <net.h> |
4efb77d4 PW |
13 | #include <netdev.h> |
14 | #include <asm/cache.h> | |
a7efd719 LW |
15 | #include <asm/io.h> |
16 | #include <asm/arch/cpu.h> | |
3dc23f78 | 17 | #include <asm/arch/soc.h> |
3fe3b4fb | 18 | #include <mvebu_mmc.h> |
4efb77d4 | 19 | |
4efb77d4 PW |
20 | void reset_cpu(unsigned long ignored) |
21 | { | |
22 | struct kwcpu_registers *cpureg = | |
23 | (struct kwcpu_registers *)KW_CPU_REG_BASE; | |
24 | ||
25 | writel(readl(&cpureg->rstoutn_mask) | (1 << 2), | |
26 | &cpureg->rstoutn_mask); | |
27 | writel(readl(&cpureg->sys_soft_rst) | 1, | |
28 | &cpureg->sys_soft_rst); | |
29 | while (1) ; | |
30 | } | |
31 | ||
4efb77d4 PW |
32 | /* |
33 | * Window Size | |
34 | * Used with the Base register to set the address window size and location. | |
35 | * Must be programmed from LSB to MSB as sequence of ones followed by | |
36 | * sequence of zeros. The number of ones specifies the size of the window in | |
37 | * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). | |
38 | * NOTE: A value of 0x0 specifies 64-KByte size. | |
39 | */ | |
78eabb90 | 40 | unsigned int kw_winctrl_calcsize(unsigned int sizeval) |
4efb77d4 PW |
41 | { |
42 | int i; | |
43 | unsigned int j = 0; | |
44 | u32 val = sizeval >> 1; | |
45 | ||
f1060560 | 46 | for (i = 0; val >= 0x10000; i++) { |
4efb77d4 PW |
47 | j |= (1 << i); |
48 | val = val >> 1; | |
49 | } | |
50 | return (0x0000ffff & j); | |
51 | } | |
52 | ||
8ef078b4 CP |
53 | static struct mbus_win windows[] = { |
54 | /* Window 0: PCIE MEM address space */ | |
55 | { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256, | |
56 | KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM }, | |
57 | ||
58 | /* Window 1: PCIE IO address space */ | |
59 | { KW_DEFADR_PCI_IO, 1024 * 64, | |
60 | KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO }, | |
61 | ||
62 | /* Window 2: NAND Flash address space */ | |
63 | { KW_DEFADR_NANDF, 1024 * 1024 * 128, | |
64 | KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH }, | |
65 | ||
66 | /* Window 3: SPI Flash address space */ | |
67 | { KW_DEFADR_SPIF, 1024 * 1024 * 128, | |
68 | KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH }, | |
69 | ||
70 | /* Window 4: BOOT Memory address space */ | |
71 | { KW_DEFADR_BOOTROM, 1024 * 1024 * 128, | |
72 | KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM }, | |
73 | ||
74 | /* Window 5: Security SRAM address space */ | |
75 | { KW_DEFADR_SASRAM, 1024 * 64, | |
76 | KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM }, | |
77 | }; | |
78 | ||
49d2cb4d PW |
79 | /* |
80 | * SYSRSTn Duration Counter Support | |
81 | * | |
82 | * Kirkwood SoC implements a hardware-based SYSRSTn duration counter. | |
83 | * When SYSRSTn is asserted low, a SYSRSTn duration counter is running. | |
84 | * The SYSRSTn duration counter is useful for implementing a manufacturer | |
85 | * or factory reset. Upon a long reset assertion that is greater than a | |
86 | * pre-configured environment variable value for sysrstdelay, | |
87 | * The counter value is stored in the SYSRSTn Length Counter Register | |
88 | * The counter is based on the 25-MHz reference clock (40ns) | |
89 | * It is a 29-bit counter, yielding a maximum counting duration of | |
90 | * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value, | |
91 | * it remains at this value until counter reset is triggered by setting | |
92 | * bit 31 of KW_REG_SYSRST_CNT | |
93 | */ | |
94 | static void kw_sysrst_action(void) | |
95 | { | |
96 | int ret; | |
00caae6d | 97 | char *s = env_get("sysrstcmd"); |
49d2cb4d PW |
98 | |
99 | if (!s) { | |
100 | debug("Error.. %s failed, check sysrstcmd\n", | |
101 | __FUNCTION__); | |
102 | return; | |
103 | } | |
104 | ||
105 | debug("Starting %s process...\n", __FUNCTION__); | |
53071532 | 106 | ret = run_command(s, 0); |
73671dad | 107 | if (ret != 0) |
49d2cb4d PW |
108 | debug("Error.. %s failed\n", __FUNCTION__); |
109 | else | |
110 | debug("%s process finished\n", __FUNCTION__); | |
111 | } | |
112 | ||
113 | static void kw_sysrst_check(void) | |
114 | { | |
115 | u32 sysrst_cnt, sysrst_dly; | |
116 | char *s; | |
117 | ||
118 | /* | |
119 | * no action if sysrstdelay environment variable is not defined | |
120 | */ | |
00caae6d | 121 | s = env_get("sysrstdelay"); |
49d2cb4d PW |
122 | if (s == NULL) |
123 | return; | |
124 | ||
125 | /* read sysrstdelay value */ | |
126 | sysrst_dly = (u32) simple_strtoul(s, NULL, 10); | |
127 | ||
128 | /* read SysRst Length counter register (bits 28:0) */ | |
129 | sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT)); | |
130 | debug("H/w Rst hold time: %d.%d secs\n", | |
131 | sysrst_cnt / SYSRST_CNT_1SEC_VAL, | |
132 | sysrst_cnt % SYSRST_CNT_1SEC_VAL); | |
133 | ||
134 | /* clear the counter for next valid read*/ | |
135 | writel(1 << 31, KW_REG_SYSRST_CNT); | |
136 | ||
137 | /* | |
138 | * sysrst_action: | |
139 | * if H/w Reset key is pressed and hold for time | |
140 | * more than sysrst_dly in seconds | |
141 | */ | |
142 | if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly) | |
143 | kw_sysrst_action(); | |
144 | } | |
145 | ||
4efb77d4 PW |
146 | #if defined(CONFIG_DISPLAY_CPUINFO) |
147 | int print_cpuinfo(void) | |
148 | { | |
62d1e990 | 149 | char *rev = "??"; |
c0cd0207 PW |
150 | u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff; |
151 | u8 revid = readl(KW_REG_PCIE_REVID) & 0xff; | |
4efb77d4 | 152 | |
c0cd0207 PW |
153 | if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) { |
154 | printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid); | |
155 | return -1; | |
156 | } | |
157 | ||
158 | switch (revid) { | |
159 | case 0: | |
62d1e990 LP |
160 | if (devid == 0x6281) |
161 | rev = "Z0"; | |
162 | else if (devid == 0x6282) | |
163 | rev = "A0"; | |
164 | break; | |
165 | case 1: | |
166 | rev = "A1"; | |
4efb77d4 PW |
167 | break; |
168 | case 2: | |
c0cd0207 PW |
169 | rev = "A0"; |
170 | break; | |
171 | case 3: | |
172 | rev = "A1"; | |
4efb77d4 PW |
173 | break; |
174 | default: | |
c0cd0207 | 175 | break; |
4efb77d4 | 176 | } |
c0cd0207 PW |
177 | |
178 | printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev); | |
4efb77d4 PW |
179 | return 0; |
180 | } | |
181 | #endif /* CONFIG_DISPLAY_CPUINFO */ | |
182 | ||
183 | #ifdef CONFIG_ARCH_CPU_INIT | |
184 | int arch_cpu_init(void) | |
185 | { | |
186 | u32 reg; | |
187 | struct kwcpu_registers *cpureg = | |
188 | (struct kwcpu_registers *)KW_CPU_REG_BASE; | |
189 | ||
8ef078b4 | 190 | /* Linux expects the internal registers to be at 0xf1000000 */ |
4efb77d4 PW |
191 | writel(KW_REGS_PHY_BASE, KW_OFFSET_REG); |
192 | ||
193 | /* Enable and invalidate L2 cache in write through mode */ | |
194 | writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg); | |
195 | invalidate_l2_cache(); | |
196 | ||
4efb77d4 PW |
197 | #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8 |
198 | /* | |
199 | * Configures the I/O voltage of the pads connected to Egigabit | |
200 | * Ethernet interface to 1.8V | |
1bce2aeb | 201 | * By default it is set to 3.3V |
4efb77d4 PW |
202 | */ |
203 | reg = readl(KW_REG_MPP_OUT_DRV_REG); | |
204 | reg |= (1 << 7); | |
205 | writel(reg, KW_REG_MPP_OUT_DRV_REG); | |
206 | #endif | |
207 | #ifdef CONFIG_KIRKWOOD_EGIGA_INIT | |
208 | /* | |
209 | * Set egiga port0/1 in normal functional mode | |
210 | * This is required becasue on kirkwood by default ports are in reset mode | |
211 | * OS egiga driver may not have provision to set them in normal mode | |
212 | * and if u-boot is build without network support, network may fail at OS level | |
213 | */ | |
214 | reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0)); | |
215 | reg &= ~(1 << 4); /* Clear PortReset Bit */ | |
216 | writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0))); | |
217 | reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1)); | |
218 | reg &= ~(1 << 4); /* Clear PortReset Bit */ | |
219 | writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1))); | |
220 | #endif | |
221 | #ifdef CONFIG_KIRKWOOD_PCIE_INIT | |
222 | /* | |
223 | * Enable PCI Express Port0 | |
224 | */ | |
225 | reg = readl(&cpureg->ctrl_stat); | |
226 | reg |= (1 << 0); /* Set PEX0En Bit */ | |
227 | writel(reg, &cpureg->ctrl_stat); | |
228 | #endif | |
229 | return 0; | |
230 | } | |
231 | #endif /* CONFIG_ARCH_CPU_INIT */ | |
232 | ||
233 | /* | |
234 | * SOC specific misc init | |
235 | */ | |
236 | #if defined(CONFIG_ARCH_MISC_INIT) | |
237 | int arch_misc_init(void) | |
238 | { | |
239 | volatile u32 temp; | |
240 | ||
241 | /*CPU streaming & write allocate */ | |
242 | temp = readfr_extra_feature_reg(); | |
243 | temp &= ~(1 << 28); /* disable wr alloc */ | |
244 | writefr_extra_feature_reg(temp); | |
245 | ||
246 | temp = readfr_extra_feature_reg(); | |
247 | temp &= ~(1 << 29); /* streaming disabled */ | |
248 | writefr_extra_feature_reg(temp); | |
249 | ||
250 | /* L2Cache settings */ | |
251 | temp = readfr_extra_feature_reg(); | |
252 | /* Disable L2C pre fetch - Set bit 24 */ | |
253 | temp |= (1 << 24); | |
254 | /* enable L2C - Set bit 22 */ | |
255 | temp |= (1 << 22); | |
256 | writefr_extra_feature_reg(temp); | |
257 | ||
4efb77d4 PW |
258 | /* Change reset vector to address 0x0 */ |
259 | temp = get_cr(); | |
260 | set_cr(temp & ~CR_V); | |
261 | ||
8ef078b4 CP |
262 | /* Configure mbus windows */ |
263 | mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); | |
264 | ||
49d2cb4d PW |
265 | /* checks and execute resset to factory event */ |
266 | kw_sysrst_check(); | |
267 | ||
4efb77d4 PW |
268 | return 0; |
269 | } | |
270 | #endif /* CONFIG_ARCH_MISC_INIT */ | |
271 | ||
d44265ad | 272 | #ifdef CONFIG_MVGBE |
4efb77d4 PW |
273 | int cpu_eth_init(bd_t *bis) |
274 | { | |
d44265ad | 275 | mvgbe_initialize(bis); |
4efb77d4 PW |
276 | return 0; |
277 | } | |
278 | #endif | |
3fe3b4fb D |
279 | |
280 | #ifdef CONFIG_MVEBU_MMC | |
281 | int board_mmc_init(bd_t *bis) | |
282 | { | |
283 | mvebu_mmc_init(bis); | |
284 | return 0; | |
285 | } | |
286 | #endif /* CONFIG_MVEBU_MMC */ |