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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[people/arne_f/kernel.git] / arch / arm / mach-msm / io.c
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3042102a
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1/* arch/arm/mach-msm/io.c
2 *
cf62ffae 3 * MSM7K, QSD io support
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4 *
5 * Copyright (C) 2007 Google, Inc.
8c27e6f3 6 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
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7 * Author: Brian Swetland <swetland@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
ebea60be 21#include <linux/bug.h>
3042102a 22#include <linux/init.h>
fced80c7 23#include <linux/io.h>
dc28094b 24#include <linux/export.h>
3042102a 25
a09e64fb 26#include <mach/hardware.h>
3042102a 27#include <asm/page.h>
a09e64fb 28#include <mach/msm_iomap.h>
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29#include <asm/mach/map.h>
30
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31#include "common.h"
32
90eb385f 33#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \
bcc0f6af 34 .virtual = (unsigned long) MSM_##name##_BASE, \
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35 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
36 .length = chip##_##name##_SIZE, \
90eb385f 37 .type = mem_type, \
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38 }
39
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40#define MSM_DEVICE_TYPE(name, mem_type) \
41 MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
42#define MSM_CHIP_DEVICE(name, chip) \
43 MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
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44#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
45
e63770ac 46#if defined(CONFIG_ARCH_MSM7X00A)
3042102a 47static struct map_desc msm_io_desc[] __initdata = {
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48 MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
49 MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
50 MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
51 MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
52 MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
53 MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
3042102a 54 {
bcc0f6af 55 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
cf62ffae 56 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
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57 .length = MSM_SHARED_RAM_SIZE,
58 .type = MT_DEVICE,
59 },
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60#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
61 defined(CONFIG_DEBUG_MSM_UART3)
62 {
63 /* Must be last: virtual and pfn filled in by debug_ll_addr() */
64 .length = SZ_4K,
65 .type = MT_DEVICE_NONSHARED,
66 }
67#endif
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68};
69
70void __init msm_map_common_io(void)
71{
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72 size_t size = ARRAY_SIZE(msm_io_desc);
73
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74 /* Make sure the peripheral register window is closed, since
75 * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
76 * pages are peripheral interface or not.
77 */
78 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
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79#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
80 defined(CONFIG_DEBUG_MSM_UART3)
81 debug_ll_addr(&msm_io_desc[size - 1].pfn,
82 &msm_io_desc[size - 1].virtual);
83 msm_io_desc[size - 1].pfn = __phys_to_pfn(msm_io_desc[size - 1].pfn);
84#endif
85 iotable_init(msm_io_desc, size);
3042102a 86}
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87#endif
88
89#ifdef CONFIG_ARCH_QSD8X50
90static struct map_desc qsd8x50_io_desc[] __initdata = {
91 MSM_DEVICE(VIC),
8c27e6f3 92 MSM_CHIP_DEVICE(CSR, QSD8X50),
cf62ffae 93 MSM_DEVICE(DMOV),
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94 MSM_CHIP_DEVICE(GPIO1, QSD8X50),
95 MSM_CHIP_DEVICE(GPIO2, QSD8X50),
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96 MSM_DEVICE(CLK_CTL),
97 MSM_DEVICE(SIRC),
98 MSM_DEVICE(SCPLL),
99 MSM_DEVICE(AD5),
100 MSM_DEVICE(MDC),
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101 {
102 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
103 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
104 .length = MSM_SHARED_RAM_SIZE,
105 .type = MT_DEVICE,
106 },
107};
108
109void __init msm_map_qsd8x50_io(void)
110{
6d07917e 111 debug_ll_io_init();
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112 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
113}
114#endif /* CONFIG_ARCH_QSD8X50 */
3042102a 115
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116#ifdef CONFIG_ARCH_MSM7X30
117static struct map_desc msm7x30_io_desc[] __initdata = {
118 MSM_DEVICE(VIC),
8c27e6f3 119 MSM_CHIP_DEVICE(CSR, MSM7X30),
c83b2bf6 120 MSM_DEVICE(DMOV),
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121 MSM_CHIP_DEVICE(GPIO1, MSM7X30),
122 MSM_CHIP_DEVICE(GPIO2, MSM7X30),
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123 MSM_DEVICE(CLK_CTL),
124 MSM_DEVICE(CLK_CTL_SH2),
125 MSM_DEVICE(AD5),
126 MSM_DEVICE(MDC),
127 MSM_DEVICE(ACC),
128 MSM_DEVICE(SAW),
129 MSM_DEVICE(GCC),
130 MSM_DEVICE(TCSR),
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131 {
132 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
133 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
134 .length = MSM_SHARED_RAM_SIZE,
135 .type = MT_DEVICE,
136 },
137};
138
139void __init msm_map_msm7x30_io(void)
140{
6d07917e 141 debug_ll_io_init();
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142 iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
143}
144#endif /* CONFIG_ARCH_MSM7X30 */
145
0c211c29 146#ifdef CONFIG_ARCH_MSM7X00A
9b97173e 147void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
b12e9ba5 148 unsigned int mtype, void *caller)
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149{
150 if (mtype == MT_DEVICE) {
151 /* The peripherals in the 88000000 - D0000000 range
b595076a 152 * are only accessible by type MT_DEVICE_NONSHARED.
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153 * Adjust mtype as necessary to make this "just work."
154 */
155 if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
156 mtype = MT_DEVICE_NONSHARED;
157 }
158
b12e9ba5 159 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
3042102a 160}
0c211c29 161#endif