[thirdparty/u-boot.git] / arch / arm / mach-mvebu / arm64-common.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
 */

#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <init.h>
#include <asm/cache.h>
#include <linux/libfdt.h>
#include <linux/sizes.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * Not all memory is mapped in the MMU. So we need to restrict the
 * memory size so that U-Boot does not try to access it. Also, the
 * internal registers are located at 0xf000.0000 - 0xffff.ffff.
 * Currently only 2GiB are mapped for system memory. This is what
 * we pass to the U-Boot subsystem here.
 */
#define USABLE_RAM_SIZE		0x80000000

ulong board_get_usable_ram_top(ulong total_size)
{
	if (gd->ram_size > USABLE_RAM_SIZE)
		return USABLE_RAM_SIZE;

	return gd->ram_size;
}

/*
 * On ARMv8, MBus is not configured in U-Boot. To enable compilation
 * of the already implemented drivers, lets add a dummy version of
 * this function so that linking does not fail.
 */
const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
{
	return NULL;
}

__weak int dram_init_banksize(void)
{
	if (CONFIG_IS_ENABLED(ARMADA_8K))
		return a8k_dram_init_banksize();
	else if (CONFIG_IS_ENABLED(ARMADA_3700))
		return a3700_dram_init_banksize();
	else
		return fdtdec_setup_memory_banksize();
}

__weak int dram_init(void)
{
	if (CONFIG_IS_ENABLED(ARMADA_8K)) {
		gd->ram_size = a8k_dram_scan_ap_sz();
		if (gd->ram_size != 0)
			return 0;
	}

	if (CONFIG_IS_ENABLED(ARMADA_3700))
		return a3700_dram_init();

	if (fdtdec_setup_mem_size_base() != 0)
		return -EINVAL;

	return 0;
}

int arch_cpu_init(void)
{
	/* Nothing to do (yet) */
	return 0;
}

int arch_early_init_r(void)
{
	struct udevice *dev;
	int ret;
	int i;

	/*
	 * Loop over all MISC uclass drivers to call the comphy code
	 * and init all CP110 devices enabled in the DT
	 */
	i = 0;
	while (1) {
		/* Call the comphy code via the MISC uclass driver */
		ret = uclass_get_device(UCLASS_MISC, i++, &dev);

		/* We're done, once no further CP110 device is found */
		if (ret)
			break;
	}

	/* Cause the SATA device to do its early init */
	uclass_first_device(UCLASS_AHCI, &dev);

#ifdef CONFIG_DM_PCI
	/* Trigger PCIe devices detection */
	pci_init();
#endif

	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
21b29fc6 SR	2	/*
21b29fc6 SR	3	* Copyright (C) 2016 Stefan Roese <sr@denx.de>
21b29fc6 SR	4	*/
	5
	6	#include <common.h>
	7	#include <dm.h>
	8	#include <fdtdec.h>
67c4e9f8	9	#include <init.h>
90526e9f	10	#include <asm/cache.h>
b08c8c48	11	#include <linux/libfdt.h>
2b4d9647	12	#include <linux/sizes.h>
f4f194e8	13	#include <pci.h>
21b29fc6 SR	14	#include <asm/io.h>
	15	#include <asm/system.h>
	16	#include <asm/arch/cpu.h>
	17	#include <asm/arch/soc.h>
	18	#include <asm/armv8/mmu.h>
	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
059f75d5 SR	22	/*
	23	* Not all memory is mapped in the MMU. So we need to restrict the
	24	* memory size so that U-Boot does not try to access it. Also, the
	25	* internal registers are located at 0xf000.0000 - 0xffff.ffff.
	26	* Currently only 2GiB are mapped for system memory. This is what
	27	* we pass to the U-Boot subsystem here.
	28	*/
	29	#define USABLE_RAM_SIZE 0x80000000
	30
	31	ulong board_get_usable_ram_top(ulong total_size)
	32	{
	33	if (gd->ram_size > USABLE_RAM_SIZE)
	34	return USABLE_RAM_SIZE;
	35
	36	return gd->ram_size;
	37	}
	38
21b29fc6 SR	39	/*
	40	* On ARMv8, MBus is not configured in U-Boot. To enable compilation
	41	* of the already implemented drivers, lets add a dummy version of
	42	* this function so that linking does not fail.
	43	*/
	44	const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
	45	{
	46	return NULL;
	47	}
	48
3b281aca	49	__weak int dram_init_banksize(void)
21b29fc6	50	{
2b4d9647	51	if (CONFIG_IS_ENABLED(ARMADA_8K))
f075b425	52	return a8k_dram_init_banksize();
a129f64f MB	53	else if (CONFIG_IS_ENABLED(ARMADA_3700))
a129f64f MB	54	return a3700_dram_init_banksize();
2b4d9647	55	else
f075b425	56	return fdtdec_setup_memory_banksize();
21b29fc6 SR	57	}
21b29fc6 SR	58
3b281aca	59	__weak int dram_init(void)
21b29fc6	60	{
2b4d9647 BS	61	if (CONFIG_IS_ENABLED(ARMADA_8K)) {
	62	gd->ram_size = a8k_dram_scan_ap_sz();
	63	if (gd->ram_size != 0)
	64	return 0;
	65	}
	66
a129f64f MB	67	if (CONFIG_IS_ENABLED(ARMADA_3700))
	68	return a3700_dram_init();
	69
12308b12	70	if (fdtdec_setup_mem_size_base() != 0)
21b29fc6 SR	71	return -EINVAL;
21b29fc6 SR	72
76b00aca	73	return 0;
21b29fc6 SR	74	}
	75
	76	int arch_cpu_init(void)
	77	{
	78	/* Nothing to do (yet) */
	79	return 0;
	80	}
	81
	82	int arch_early_init_r(void)
	83	{
	84	struct udevice *dev;
	85	int ret;
d7dd358f SR	86	int i;
	87
	88	/*
	89	* Loop over all MISC uclass drivers to call the comphy code
	90	* and init all CP110 devices enabled in the DT
	91	*/
	92	i = 0;
	93	while (1) {
	94	/* Call the comphy code via the MISC uclass driver */
	95	ret = uclass_get_device(UCLASS_MISC, i++, &dev);
	96
	97	/* We're done, once no further CP110 device is found */
	98	if (ret)
	99	break;
21b29fc6 SR	100	}
	101
	102	/* Cause the SATA device to do its early init */
	103	uclass_first_device(UCLASS_AHCI, &dev);
	104
f4f194e8 KP	105	#ifdef CONFIG_DM_PCI
	106	/* Trigger PCIe devices detection */
	107	pci_init();
	108	#endif
	109
21b29fc6 SR	110	return 0;
21b29fc6 SR	111	}