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1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Marvell Semiconductor <www.marvell.com> | |
4 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
5 | * | |
6 | * Header file for the Marvell's Feroceon CPU core. | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
250eea74 SR |
11 | #ifndef _MVEBU_SOC_H |
12 | #define _MVEBU_SOC_H | |
41e5ee54 SR |
13 | |
14 | #define SOC_MV78460_ID 0x7846 | |
9c6d3b7b SR |
15 | #define SOC_88F6810_ID 0x6810 |
16 | #define SOC_88F6820_ID 0x6820 | |
17 | #define SOC_88F6828_ID 0x6828 | |
18 | ||
19 | /* A38x revisions */ | |
20 | #define MV_88F68XX_Z1_ID 0x0 | |
21 | #define MV_88F68XX_A0_ID 0x4 | |
41e5ee54 SR |
22 | |
23 | /* TCLK Core Clock definition */ | |
24 | #ifndef CONFIG_SYS_TCLK | |
25 | #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ | |
26 | #endif | |
27 | ||
28 | /* SOC specific definations */ | |
29 | #define INTREG_BASE 0xd0000000 | |
30 | #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) | |
31 | #define SOC_REGS_PHY_BASE 0xf1000000 | |
32 | #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x) | |
33 | ||
34 | #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) | |
9c6d3b7b SR |
35 | #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) |
36 | #define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE | |
41e5ee54 SR |
37 | #define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600)) |
38 | #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) | |
39 | #define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000)) | |
40 | #define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100)) | |
41 | #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) | |
42 | #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) | |
43 | #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) | |
44 | #define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180)) | |
45 | #define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200)) | |
46 | #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) | |
47 | #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) | |
48 | #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) | |
49 | #define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000)) | |
50 | #define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000)) | |
51 | #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) | |
fe11ae24 | 52 | #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) |
41e5ee54 SR |
53 | #define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) |
54 | #define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) | |
4d991cb3 | 55 | #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) |
7f1adcd7 | 56 | #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) |
41e5ee54 SR |
57 | |
58 | #define SDRAM_MAX_CS 4 | |
59 | #define SDRAM_ADDR_MASK 0xFF000000 | |
60 | ||
250eea74 | 61 | /* MVEBU CPU memory windows */ |
41e5ee54 SR |
62 | #define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA |
63 | #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE | |
64 | #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE | |
65 | ||
250eea74 | 66 | #endif /* _MVEBU_SOC_H */ |