[thirdparty/u-boot.git] / arch / arm / mach-omap2 / am33xx / ddr.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * DDR Configuration for AM33xx devices.
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 */

#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>

/**
 * Base address for EMIF instances
 */
static struct emif_reg_struct *emif_reg[2] = {
				(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
				(struct emif_reg_struct *)EMIF4_1_CFG_BASE};

/**
 * Base addresses for DDR PHY cmd/data regs
 */
static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};

static struct ddr_data_regs *ddr_data_reg[2] = {
				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};

/**
 * Base address for ddr io control instances
 */
static struct ddr_cmdtctrl *ioctrl_reg = {
			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};

static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
{
	u32 mr;

	mr_addr |= cs << EMIF_REG_CS_SHIFT;
	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);

	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
	debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
	if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
	    ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
	    ((mr & 0xff000000) >> 24) == (mr & 0xff))
		return mr & 0xff;
	else
		return mr;
}

static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
{
	mr_addr |= cs << EMIF_REG_CS_SHIFT;
	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
}

static void configure_mr(int nr, u32 cs)
{
	u32 mr_addr;

	while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
		;
	set_mr(nr, cs, LPDDR2_MR10, 0x56);

	set_mr(nr, cs, LPDDR2_MR1, 0x43);
	set_mr(nr, cs, LPDDR2_MR2, 0x2);

	mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
	set_mr(nr, cs, mr_addr, 0x2);
}

/*
 * Configure EMIF4D5 registers and MR registers For details about these magic
 * values please see the EMIF registers section of the TRM.
 */
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
#ifdef CONFIG_AM43XX
	struct prm_device_inst *prm_device =
			(struct prm_device_inst *)PRM_DEVICE_INST;
#endif

	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);

	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
	writel(regs->emif_rd_wr_lvl_rmp_win,
	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
	writel(regs->emif_rd_wr_lvl_rmp_ctl,
	       &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
	writel(regs->emif_rd_wr_exec_thresh,
	       &emif_reg[nr]->emif_rd_wr_exec_thresh);

	/*
	 * for most SOCs these registers won't need to be changed so only
	 * write to these registers if someone explicitly has set the
	 * register's value.
	 */
	if(regs->emif_cos_config) {
		writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
		writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
		writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
		writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
	}

	/*
	 * Sequence to ensure that the PHY is in a known state prior to
	 * startting hardware leveling.  Also acts as to latch some state from
	 * the EMIF into the PHY.
	 */
	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);

	clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
			EMIF_REG_INITREF_DIS_MASK);

	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);

	/* Wait 1ms because of L3 timeout error */
	udelay(1000);

	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);

#ifdef CONFIG_AM43XX
	/*
	 * Disable EMIF_DEVOFF
	 * -> Cold Boot: This is just rewriting the default register value.
	 * -> RTC Resume: Must disable DEVOFF before leveling.
	 */
	writel(0, &prm_device->emif_ctrl);
#endif

	/* Perform hardware leveling for DDR3 */
	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
		writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
		       0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);

		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);

		/* Enable read leveling */
		writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);

		/* Wait 1ms because of L3 timeout error */
		udelay(1000);

		/*
		 * Enable full read and write leveling.  Wait for read and write
		 * leveling bit to clear RDWRLVLFULL_START bit 31
		 */
		while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
		      != 0)
			;

		/* Check the timeout register to see if leveling is complete */
		if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
			puts("DDR3 H/W leveling incomplete with errors\n");

	} else {
		/* DDR2 */
		configure_mr(nr, 0);
		configure_mr(nr, 1);
	}
}

/**
 * Configure SDRAM
 */
void config_sdram(const struct emif_regs *regs, int nr)
{
#ifdef CONFIG_TI816X
	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
	writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* initially a large refresh period */
	writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl);   /* trigger initialization           */
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
#else
	if (regs->zq_config) {
		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
		writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);

		/* Trigger initialization */
		writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
		/* Wait 1ms because of L3 timeout error */
		udelay(1000);

		/* Write proper sdram_ref_cref_ctrl value */
		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	}
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);

	/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
	if (regs->ocp_config)
		writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
#endif
}

/**
 * Set SDRAM timings
 */
void set_sdram_timings(const struct emif_regs *regs, int nr)
{
	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
}

/*
 * Configure EXT PHY registers for software leveling
 */
static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
{
	u32 *ext_phy_ctrl_base = 0;
	u32 *emif_ext_phy_ctrl_base = 0;
	__maybe_unused const u32 *ext_phy_ctrl_const_regs;
	u32 i = 0;
	__maybe_unused u32 size;

	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
	emif_ext_phy_ctrl_base =
			(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);

	/* Configure external phy control timing registers */
	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
		/* Update shadow registers */
		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
	}

#ifdef CONFIG_AM43XX
	/*
	 * External phy 6-24 registers do not change with ddr frequency.
	 * These only need to be set on DDR2 on AM43xx.
	 */
	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);

	if (!size)
		return;

	for (i = 0; i < size; i++) {
		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
		/* Update shadow registers */
		writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
	}
#endif
}

/*
 * Configure EXT PHY registers for hardware leveling
 */
static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
{
	/*
	 * Enable hardware leveling on the EMIF.  For details about these
	 * magic values please see the EMIF registers section of the TRM.
	 */
	if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
		/* PHY_INVERT_CLKOUT = 1 */
		writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
		writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
	} else {
		/* PHY_INVERT_CLKOUT = 0 */
		writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
		writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
	}

	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
	writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
	writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);

	/*
	 * Sequence to ensure that the PHY is again in a known state after
	 * hardware leveling.
	 */
	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
}

/**
 * Configure DDR PHY
 */
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
	/*
	 * Disable initialization and refreshes for now until we finish
	 * programming EMIF regs and set time between rising edge of
	 * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
	 * We currently hardcode a value based on a max expected frequency
	 * of 400MHz.
	 */
	writel(EMIF_REG_INITREF_DIS_MASK | 0x3100,
		&emif_reg[nr]->emif_sdram_ref_ctrl);

	writel(regs->emif_ddr_phy_ctlr_1,
		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
	writel(regs->emif_ddr_phy_ctlr_1,
		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);

	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
		if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
			ext_phy_settings_hwlvl(regs, nr);
		else
			ext_phy_settings_swlvl(regs, nr);
	}
}

/**
 * Configure DDR CMD control registers
 */
void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
{
	if (!cmd)
		return;

	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);

	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);

	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
}

/**
 * Configure DDR DATA registers
 */
void config_ddr_data(const struct ddr_data *data, int nr)
{
	int i;

	if (!data)
		return;

	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
		writel(data->datardsratio0,
			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
		writel(data->datawdsratio0,
			&(ddr_data_reg[nr]+i)->dt0wdsratio0);
		writel(data->datawiratio0,
			&(ddr_data_reg[nr]+i)->dt0wiratio0);
		writel(data->datagiratio0,
			&(ddr_data_reg[nr]+i)->dt0giratio0);
		writel(data->datafwsratio0,
			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
		writel(data->datawrsratio0,
			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
	}
}

void config_io_ctrl(const struct ctrl_ioregs *ioregs)
{
	if (!ioregs)
		return;

	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
#ifdef CONFIG_AM43XX
	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
	writel(ioregs->emif_sdram_config_ext,
	       &ioctrl_reg->emif_sdram_config_ext);
#endif
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
62d7fe7c CN	2	/*
	3	* DDR Configuration for AM33xx devices.
	4	*
1a459660	5	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
62d7fe7c CN	6	*/
62d7fe7c CN	7
c3dc39a2	8	#include <common.h>
62d7fe7c CN	9	#include <asm/arch/cpu.h>
62d7fe7c CN	10	#include <asm/arch/ddr_defs.h>
6995a289	11	#include <asm/arch/sys_proto.h>
62d7fe7c	12	#include <asm/io.h>
7d5eb349	13	#include <asm/emif.h>
62d7fe7c CN	14
	15	/**
	16	* Base address for EMIF instances
	17	*/
3ba65f97 MP	18	static struct emif_reg_struct *emif_reg[2] = {
	19	(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
	20	(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
62d7fe7c CN	21
62d7fe7c CN	22	/**
3ba65f97	23	* Base addresses for DDR PHY cmd/data regs
62d7fe7c	24	*/
3ba65f97 MP	25	static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
	26	(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
	27	(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
	28
	29	static struct ddr_data_regs *ddr_data_reg[2] = {
	30	(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
	31	(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
62d7fe7c CN	32
	33	/**
	34	* Base address for ddr io control instances
	35	*/
	36	static struct ddr_cmdtctrl *ioctrl_reg = {
	37	(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
	38
d3daba10 LV	39	static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
	40	{
	41	u32 mr;
	42
	43	mr_addr \|= cs << EMIF_REG_CS_SHIFT;
	44	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
	45
	46	mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
	47	debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
	48	if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
	49	((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
	50	((mr & 0xff000000) >> 24) == (mr & 0xff))
	51	return mr & 0xff;
	52	else
	53	return mr;
	54	}
	55
	56	static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
	57	{
	58	mr_addr \|= cs << EMIF_REG_CS_SHIFT;
	59	writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
	60	writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
	61	}
	62
	63	static void configure_mr(int nr, u32 cs)
	64	{
	65	u32 mr_addr;
	66
	67	while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
	68	;
	69	set_mr(nr, cs, LPDDR2_MR10, 0x56);
	70
	71	set_mr(nr, cs, LPDDR2_MR1, 0x43);
	72	set_mr(nr, cs, LPDDR2_MR2, 0x2);
	73
	74	mr_addr = LPDDR2_MR2 \| EMIF_REG_REFRESH_EN_MASK;
	75	set_mr(nr, cs, mr_addr, 0x2);
	76	}
	77
	78	/*
fc46bae2 JD	79	* Configure EMIF4D5 registers and MR registers For details about these magic
fc46bae2 JD	80	* values please see the EMIF registers section of the TRM.
d3daba10 LV	81	*/
	82	void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
	83	{
7b5774e4 BG	84	#ifdef CONFIG_AM43XX
	85	struct prm_device_inst *prm_device =
	86	(struct prm_device_inst *)PRM_DEVICE_INST;
	87	#endif
	88
4800be4a DG	89	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
4800be4a DG	90	writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
d3daba10 LV	91	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
	92
	93	writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
	94	writel(regs->emif_rd_wr_lvl_rmp_win,
	95	&emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
	96	writel(regs->emif_rd_wr_lvl_rmp_ctl,
	97	&emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
	98	writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
	99	writel(regs->emif_rd_wr_exec_thresh,
	100	&emif_reg[nr]->emif_rd_wr_exec_thresh);
	101
8038b497 CJF	102	/*
	103	* for most SOCs these registers won't need to be changed so only
	104	* write to these registers if someone explicitly has set the
	105	* register's value.
	106	*/
	107	if(regs->emif_cos_config) {
	108	writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
	109	writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
	110	writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
	111	writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
	112	}
	113
fc46bae2 JD	114	/*
	115	* Sequence to ensure that the PHY is in a known state prior to
	116	* startting hardware leveling. Also acts as to latch some state from
	117	* the EMIF into the PHY.
	118	*/
	119	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
	120	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
	121	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
	122
	123	clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
	124	EMIF_REG_INITREF_DIS_MASK);
	125
d3daba10	126	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
f84880f0	127	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
3325b065 RD	128
	129	/* Wait 1ms because of L3 timeout error */
	130	udelay(1000);
	131
fc46bae2 JD	132	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	133	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	134
7b5774e4 BG	135	#ifdef CONFIG_AM43XX
	136	/*
	137	* Disable EMIF_DEVOFF
	138	* -> Cold Boot: This is just rewriting the default register value.
	139	* -> RTC Resume: Must disable DEVOFF before leveling.
	140	*/
	141	writel(0, &prm_device->emif_ctrl);
	142	#endif
	143
7c352cd3 TR	144	/* Perform hardware leveling for DDR3 */
7c352cd3 TR	145	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
7c352cd3 TR	146	writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) \|
	147	0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
	148	writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) \|
	149	0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
	150
	151	writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
	152
	153	/* Enable read leveling */
	154	writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
	155
84cf295f BG	156	/* Wait 1ms because of L3 timeout error */
	157	udelay(1000);
	158
7c352cd3 TR	159	/*
	160	* Enable full read and write leveling. Wait for read and write
	161	* leveling bit to clear RDWRLVLFULL_START bit 31
	162	*/
	163	while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
	164	!= 0)
	165	;
	166
	167	/* Check the timeout register to see if leveling is complete */
	168	if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
	169	puts("DDR3 H/W leveling incomplete with errors\n");
	170
	171	} else {
	172	/* DDR2 */
b5e01eec LV	173	configure_mr(nr, 0);
	174	configure_mr(nr, 1);
	175	}
d3daba10 LV	176	}
d3daba10 LV	177
62d7fe7c CN	178	/**
	179	* Configure SDRAM
	180	*/
3ba65f97	181	void config_sdram(const struct emif_regs *regs, int nr)
62d7fe7c	182	{
86277339 TR	183	#ifdef CONFIG_TI816X
	184	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
	185	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1);
	186	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
	187	writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* initially a large refresh period */
	188	writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* trigger initialization */
	189	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	190	#else
1c382ead	191	if (regs->zq_config) {
3ba65f97	192	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
6995a289	193	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
3ba65f97	194	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
69b918b6 ES	195
	196	/* Trigger initialization */
	197	writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
	198	/* Wait 1ms because of L3 timeout error */
	199	udelay(1000);
	200
	201	/* Write proper sdram_ref_cref_ctrl value */
3ba65f97 MP	202	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
3ba65f97 MP	203	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
6995a289	204	}
3ba65f97 MP	205	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
3ba65f97 MP	206	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
e049b772	207	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
8c17cbdf JS	208
	209	/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
	210	if (regs->ocp_config)
	211	writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
86277339	212	#endif
62d7fe7c CN	213	}
	214
	215	/**
	216	* Set SDRAM timings
	217	*/
3ba65f97	218	void set_sdram_timings(const struct emif_regs *regs, int nr)
62d7fe7c	219	{
3ba65f97 MP	220	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
	221	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
	222	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
	223	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
	224	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
	225	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
62d7fe7c CN	226	}
62d7fe7c CN	227
7c352cd3 TR	228	/*
	229	* Configure EXT PHY registers for software leveling
	230	*/
	231	static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
	232	{
	233	u32 *ext_phy_ctrl_base = 0;
	234	u32 *emif_ext_phy_ctrl_base = 0;
	235	__maybe_unused const u32 *ext_phy_ctrl_const_regs;
	236	u32 i = 0;
	237	__maybe_unused u32 size;
	238
	239	ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
	240	emif_ext_phy_ctrl_base =
	241	(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
	242
	243	/* Configure external phy control timing registers */
	244	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
	245	writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
	246	/* Update shadow registers */
	247	writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
	248	}
	249
	250	#ifdef CONFIG_AM43XX
	251	/*
	252	* External phy 6-24 registers do not change with ddr frequency.
	253	* These only need to be set on DDR2 on AM43xx.
	254	*/
	255	emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
	256
	257	if (!size)
	258	return;
	259
	260	for (i = 0; i < size; i++) {
	261	writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
	262	/* Update shadow registers */
	263	writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
	264	}
	265	#endif
	266	}
	267
d3daba10	268	/*
fc46bae2	269	* Configure EXT PHY registers for hardware leveling
d3daba10	270	*/
7c352cd3	271	static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
d3daba10	272	{
d3daba10	273	/*
fc46bae2 JD	274	* Enable hardware leveling on the EMIF. For details about these
fc46bae2 JD	275	* magic values please see the EMIF registers section of the TRM.
d3daba10	276	*/
82195797 BG	277	if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) {
	278	/* PHY_INVERT_CLKOUT = 1 */
	279	writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
	280	writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
	281	} else {
	282	/* PHY_INVERT_CLKOUT = 0 */
	283	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
	284	writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
	285	}
	286
fc46bae2 JD	287	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
	288	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
	289	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
	290	writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
	291	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
	292	writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
	293	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
	294	writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
	295	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
	296	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
	297	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
	298	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
	299	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
	300	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
	301	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
	302	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
	303	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
	304	writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
	305	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
	306	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
	307	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
	308	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
	309	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
	310	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
	311	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
	312	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
	313	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
	314	writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
1dbd9a7b BG	315	writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
1dbd9a7b BG	316	writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
d3daba10	317
fc46bae2 JD	318	/*
	319	* Sequence to ensure that the PHY is again in a known state after
	320	* hardware leveling.
	321	*/
	322	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
	323	writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
	324	writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
d3daba10 LV	325	}
d3daba10 LV	326
62d7fe7c CN	327	/**
	328	* Configure DDR PHY
	329	*/
3ba65f97	330	void config_ddr_phy(const struct emif_regs *regs, int nr)
62d7fe7c	331	{
d3daba10	332	/*
335b4e53 RD	333	* Disable initialization and refreshes for now until we finish
	334	* programming EMIF regs and set time between rising edge of
	335	* DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec.
	336	* We currently hardcode a value based on a max expected frequency
	337	* of 400MHz.
d3daba10	338	*/
335b4e53 RD	339	writel(EMIF_REG_INITREF_DIS_MASK \| 0x3100,
335b4e53 RD	340	&emif_reg[nr]->emif_sdram_ref_ctrl);
d3daba10	341
3ba65f97 MP	342	writel(regs->emif_ddr_phy_ctlr_1,
	343	&emif_reg[nr]->emif_ddr_phy_ctrl_1);
	344	writel(regs->emif_ddr_phy_ctlr_1,
	345	&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
d3daba10	346
7c352cd3 TR	347	if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
	348	if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
	349	ext_phy_settings_hwlvl(regs, nr);
	350	else
	351	ext_phy_settings_swlvl(regs, nr);
	352	}
62d7fe7c CN	353	}
	354
	355	/**
	356	* Configure DDR CMD control registers
	357	*/
3ba65f97	358	void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
62d7fe7c	359	{
965de8b9 LV	360	if (!cmd)
	361	return;
	362
3ba65f97	363	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
3ba65f97	364	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
62d7fe7c	365
3ba65f97	366	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
3ba65f97	367	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
62d7fe7c	368
3ba65f97	369	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
3ba65f97	370	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
62d7fe7c CN	371	}
	372
	373	/**
	374	* Configure DDR DATA registers
	375	*/
3ba65f97	376	void config_ddr_data(const struct ddr_data *data, int nr)
62d7fe7c	377	{
3ba65f97 MP	378	int i;
3ba65f97 MP	379
965de8b9 LV	380	if (!data)
	381	return;
	382
3ba65f97 MP	383	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
	384	writel(data->datardsratio0,
	385	&(ddr_data_reg[nr]+i)->dt0rdsratio0);
	386	writel(data->datawdsratio0,
	387	&(ddr_data_reg[nr]+i)->dt0wdsratio0);
	388	writel(data->datawiratio0,
	389	&(ddr_data_reg[nr]+i)->dt0wiratio0);
	390	writel(data->datagiratio0,
	391	&(ddr_data_reg[nr]+i)->dt0giratio0);
	392	writel(data->datafwsratio0,
	393	&(ddr_data_reg[nr]+i)->dt0fwsratio0);
	394	writel(data->datawrsratio0,
	395	&(ddr_data_reg[nr]+i)->dt0wrsratio0);
3ba65f97	396	}
62d7fe7c CN	397	}
62d7fe7c CN	398
965de8b9	399	void config_io_ctrl(const struct ctrl_ioregs *ioregs)
62d7fe7c	400	{
965de8b9 LV	401	if (!ioregs)
	402	return;
	403
	404	writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
	405	writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
	406	writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
	407	writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
	408	writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
	409	#ifdef CONFIG_AM43XX
	410	writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
	411	writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
	412	writel(ioregs->emif_sdram_config_ext,
	413	&ioctrl_reg->emif_sdram_config_ext);
	414	#endif
62d7fe7c	415	}