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63138812 KV |
1 | /* |
2 | * linux/arch/arm/mach-omap2/board-n8x0.c | |
3 | * | |
4 | * Copyright (C) 2005-2009 Nokia Corporation | |
5 | * Author: Juha Yrjola <juha.yrjola@nokia.com> | |
6 | * | |
7 | * Modified from mach-omap2/board-generic.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/gpio.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/io.h> | |
0857ba3c | 19 | #include <linux/irq.h> |
63138812 | 20 | #include <linux/stddef.h> |
9418c65f | 21 | #include <linux/i2c.h> |
63138812 KV |
22 | #include <linux/spi/spi.h> |
23 | #include <linux/usb/musb.h> | |
0857ba3c | 24 | #include <linux/platform_data/i2c-cbus-gpio.h> |
2203747c AB |
25 | #include <linux/platform_data/spi-omap2-mcspi.h> |
26 | #include <linux/platform_data/mtd-onenand-omap2.h> | |
7bd3b618 | 27 | #include <linux/mfd/menelaus.h> |
366498d4 | 28 | #include <sound/tlv320aic3x.h> |
63138812 KV |
29 | |
30 | #include <asm/mach/arch.h> | |
31 | #include <asm/mach-types.h> | |
32 | ||
4e65331c | 33 | #include "common.h" |
68f39e74 | 34 | #include "mmc.h" |
63138812 | 35 | |
bd8f0fc9 | 36 | #include "mux.h" |
b6ab13e7 | 37 | #include "gpmc-onenand.h" |
bd8f0fc9 | 38 | |
97b9ad16 FA |
39 | #define TUSB6010_ASYNC_CS 1 |
40 | #define TUSB6010_SYNC_CS 4 | |
41 | #define TUSB6010_GPIO_INT 58 | |
42 | #define TUSB6010_GPIO_ENABLE 0 | |
43 | #define TUSB6010_DMACHAN 0x3f | |
44 | ||
0857ba3c AK |
45 | #if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE) |
46 | static struct i2c_cbus_platform_data n8x0_cbus_data = { | |
47 | .clk_gpio = 66, | |
48 | .dat_gpio = 65, | |
49 | .sel_gpio = 64, | |
50 | }; | |
51 | ||
52 | static struct platform_device n8x0_cbus_device = { | |
53 | .name = "i2c-cbus-gpio", | |
54 | .id = 3, | |
55 | .dev = { | |
56 | .platform_data = &n8x0_cbus_data, | |
57 | }, | |
58 | }; | |
59 | ||
60 | static struct i2c_board_info n8x0_i2c_board_info_3[] __initdata = { | |
61 | { | |
62 | I2C_BOARD_INFO("retu-mfd", 0x01), | |
63 | }, | |
64 | }; | |
65 | ||
66 | static void __init n8x0_cbus_init(void) | |
67 | { | |
68 | const int retu_irq_gpio = 108; | |
69 | ||
70 | if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ")) | |
71 | return; | |
72 | irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING); | |
73 | n8x0_i2c_board_info_3[0].irq = gpio_to_irq(retu_irq_gpio); | |
74 | i2c_register_board_info(3, n8x0_i2c_board_info_3, | |
75 | ARRAY_SIZE(n8x0_i2c_board_info_3)); | |
76 | platform_device_register(&n8x0_cbus_device); | |
77 | } | |
78 | #else /* CONFIG_I2C_CBUS_GPIO */ | |
79 | static void __init n8x0_cbus_init(void) | |
80 | { | |
81 | } | |
82 | #endif /* CONFIG_I2C_CBUS_GPIO */ | |
83 | ||
9a35f876 | 84 | #if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) |
97b9ad16 FA |
85 | /* |
86 | * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and | |
87 | * 1.5 V voltage regulators of PM companion chip. Companion chip will then | |
88 | * provide then PGOOD signal to TUSB6010 which will release it from reset. | |
89 | */ | |
90 | static int tusb_set_power(int state) | |
91 | { | |
92 | int i, retval = 0; | |
93 | ||
94 | if (state) { | |
95 | gpio_set_value(TUSB6010_GPIO_ENABLE, 1); | |
96 | msleep(1); | |
97 | ||
98 | /* Wait until TUSB6010 pulls INT pin down */ | |
99 | i = 100; | |
100 | while (i && gpio_get_value(TUSB6010_GPIO_INT)) { | |
101 | msleep(1); | |
102 | i--; | |
103 | } | |
104 | ||
105 | if (!i) { | |
106 | printk(KERN_ERR "tusb: powerup failed\n"); | |
107 | retval = -ENODEV; | |
108 | } | |
109 | } else { | |
110 | gpio_set_value(TUSB6010_GPIO_ENABLE, 0); | |
111 | msleep(10); | |
112 | } | |
113 | ||
114 | return retval; | |
115 | } | |
116 | ||
117 | static struct musb_hdrc_config musb_config = { | |
118 | .multipoint = 1, | |
119 | .dyn_fifo = 1, | |
120 | .num_eps = 16, | |
121 | .ram_bits = 12, | |
122 | }; | |
123 | ||
124 | static struct musb_hdrc_platform_data tusb_data = { | |
310018d5 | 125 | #ifdef CONFIG_USB_GADGET_MUSB_HDRC |
97b9ad16 | 126 | .mode = MUSB_OTG, |
310018d5 | 127 | #else |
97b9ad16 FA |
128 | .mode = MUSB_HOST, |
129 | #endif | |
130 | .set_power = tusb_set_power, | |
131 | .min_power = 25, /* x2 = 50 mA drawn from VBUS as peripheral */ | |
132 | .power = 100, /* Max 100 mA VBUS for host mode */ | |
133 | .config = &musb_config, | |
134 | }; | |
135 | ||
136 | static void __init n8x0_usb_init(void) | |
137 | { | |
138 | int ret = 0; | |
139 | static char announce[] __initdata = KERN_INFO "TUSB 6010\n"; | |
140 | ||
141 | /* PM companion chip power control pin */ | |
bc593f5d IG |
142 | ret = gpio_request_one(TUSB6010_GPIO_ENABLE, GPIOF_OUT_INIT_LOW, |
143 | "TUSB6010 enable"); | |
97b9ad16 FA |
144 | if (ret != 0) { |
145 | printk(KERN_ERR "Could not get TUSB power GPIO%i\n", | |
146 | TUSB6010_GPIO_ENABLE); | |
147 | return; | |
148 | } | |
97b9ad16 FA |
149 | tusb_set_power(0); |
150 | ||
151 | ret = tusb6010_setup_interface(&tusb_data, TUSB6010_REFCLK_19, 2, | |
152 | TUSB6010_ASYNC_CS, TUSB6010_SYNC_CS, | |
153 | TUSB6010_GPIO_INT, TUSB6010_DMACHAN); | |
154 | if (ret != 0) | |
155 | goto err; | |
156 | ||
157 | printk(announce); | |
158 | ||
159 | return; | |
160 | ||
161 | err: | |
162 | gpio_free(TUSB6010_GPIO_ENABLE); | |
163 | } | |
164 | #else | |
165 | ||
166 | static void __init n8x0_usb_init(void) {} | |
167 | ||
7c925546 | 168 | #endif /*CONFIG_USB_MUSB_TUSB6010 */ |
97b9ad16 FA |
169 | |
170 | ||
63138812 KV |
171 | static struct omap2_mcspi_device_config p54spi_mcspi_config = { |
172 | .turbo_mode = 0, | |
63138812 KV |
173 | }; |
174 | ||
175 | static struct spi_board_info n800_spi_board_info[] __initdata = { | |
176 | { | |
177 | .modalias = "p54spi", | |
178 | .bus_num = 2, | |
179 | .chip_select = 0, | |
180 | .max_speed_hz = 48000000, | |
181 | .controller_data = &p54spi_mcspi_config, | |
182 | }, | |
183 | }; | |
184 | ||
185 | #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ | |
186 | defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) | |
187 | ||
188 | static struct mtd_partition onenand_partitions[] = { | |
189 | { | |
190 | .name = "bootloader", | |
191 | .offset = 0, | |
192 | .size = 0x20000, | |
193 | .mask_flags = MTD_WRITEABLE, /* Force read-only */ | |
194 | }, | |
195 | { | |
196 | .name = "config", | |
197 | .offset = MTDPART_OFS_APPEND, | |
198 | .size = 0x60000, | |
199 | }, | |
200 | { | |
201 | .name = "kernel", | |
202 | .offset = MTDPART_OFS_APPEND, | |
203 | .size = 0x200000, | |
204 | }, | |
205 | { | |
206 | .name = "initfs", | |
207 | .offset = MTDPART_OFS_APPEND, | |
208 | .size = 0x400000, | |
209 | }, | |
210 | { | |
211 | .name = "rootfs", | |
212 | .offset = MTDPART_OFS_APPEND, | |
213 | .size = MTDPART_SIZ_FULL, | |
214 | }, | |
215 | }; | |
216 | ||
a1a92e6f AK |
217 | static struct omap_onenand_platform_data board_onenand_data[] = { |
218 | { | |
219 | .cs = 0, | |
220 | .gpio_irq = 26, | |
221 | .parts = onenand_partitions, | |
222 | .nr_parts = ARRAY_SIZE(onenand_partitions), | |
223 | .flags = ONENAND_SYNC_READ, | |
224 | } | |
63138812 | 225 | }; |
63138812 KV |
226 | #endif |
227 | ||
9418c65f TL |
228 | #if defined(CONFIG_MENELAUS) && \ |
229 | (defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)) | |
230 | ||
231 | /* | |
232 | * On both N800 and N810, only the first of the two MMC controllers is in use. | |
233 | * The two MMC slots are multiplexed via Menelaus companion chip over I2C. | |
234 | * On N800, both slots are powered via Menelaus. On N810, only one of the | |
235 | * slots is powered via Menelaus. The N810 EMMC is powered via GPIO. | |
236 | * | |
237 | * VMMC slot 1 on both N800 and N810 | |
238 | * VDCDC3_APE and VMCS2_APE slot 2 on N800 | |
239 | * GPIO23 and GPIO9 slot 2 EMMC on N810 | |
240 | * | |
241 | */ | |
242 | #define N8X0_SLOT_SWITCH_GPIO 96 | |
243 | #define N810_EMMC_VSD_GPIO 23 | |
1dea5c6b | 244 | #define N810_EMMC_VIO_GPIO 9 |
9418c65f | 245 | |
49b87c6d TL |
246 | static int slot1_cover_open; |
247 | static int slot2_cover_open; | |
248 | static struct device *mmc_device; | |
249 | ||
9418c65f TL |
250 | static int n8x0_mmc_switch_slot(struct device *dev, int slot) |
251 | { | |
252 | #ifdef CONFIG_MMC_DEBUG | |
253 | dev_dbg(dev, "Choose slot %d\n", slot + 1); | |
254 | #endif | |
255 | gpio_set_value(N8X0_SLOT_SWITCH_GPIO, slot); | |
256 | return 0; | |
257 | } | |
258 | ||
259 | static int n8x0_mmc_set_power_menelaus(struct device *dev, int slot, | |
260 | int power_on, int vdd) | |
261 | { | |
262 | int mV; | |
263 | ||
264 | #ifdef CONFIG_MMC_DEBUG | |
265 | dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1, | |
266 | power_on ? "on" : "off", vdd); | |
267 | #endif | |
268 | if (slot == 0) { | |
269 | if (!power_on) | |
270 | return menelaus_set_vmmc(0); | |
271 | switch (1 << vdd) { | |
272 | case MMC_VDD_33_34: | |
273 | case MMC_VDD_32_33: | |
274 | case MMC_VDD_31_32: | |
275 | mV = 3100; | |
276 | break; | |
277 | case MMC_VDD_30_31: | |
278 | mV = 3000; | |
279 | break; | |
280 | case MMC_VDD_28_29: | |
281 | mV = 2800; | |
282 | break; | |
283 | case MMC_VDD_165_195: | |
284 | mV = 1850; | |
285 | break; | |
286 | default: | |
287 | BUG(); | |
288 | } | |
289 | return menelaus_set_vmmc(mV); | |
290 | } else { | |
291 | if (!power_on) | |
292 | return menelaus_set_vdcdc(3, 0); | |
293 | switch (1 << vdd) { | |
294 | case MMC_VDD_33_34: | |
295 | case MMC_VDD_32_33: | |
296 | mV = 3300; | |
297 | break; | |
298 | case MMC_VDD_30_31: | |
299 | case MMC_VDD_29_30: | |
300 | mV = 3000; | |
301 | break; | |
302 | case MMC_VDD_28_29: | |
303 | case MMC_VDD_27_28: | |
304 | mV = 2800; | |
305 | break; | |
306 | case MMC_VDD_24_25: | |
307 | case MMC_VDD_23_24: | |
308 | mV = 2400; | |
309 | break; | |
310 | case MMC_VDD_22_23: | |
311 | case MMC_VDD_21_22: | |
312 | mV = 2200; | |
313 | break; | |
314 | case MMC_VDD_20_21: | |
315 | mV = 2000; | |
316 | break; | |
317 | case MMC_VDD_165_195: | |
318 | mV = 1800; | |
319 | break; | |
320 | default: | |
321 | BUG(); | |
322 | } | |
323 | return menelaus_set_vdcdc(3, mV); | |
324 | } | |
325 | return 0; | |
326 | } | |
327 | ||
328 | static void n810_set_power_emmc(struct device *dev, | |
329 | int power_on) | |
330 | { | |
331 | dev_dbg(dev, "Set EMMC power %s\n", power_on ? "on" : "off"); | |
332 | ||
333 | if (power_on) { | |
334 | gpio_set_value(N810_EMMC_VSD_GPIO, 1); | |
335 | msleep(1); | |
1dea5c6b | 336 | gpio_set_value(N810_EMMC_VIO_GPIO, 1); |
9418c65f TL |
337 | msleep(1); |
338 | } else { | |
1dea5c6b | 339 | gpio_set_value(N810_EMMC_VIO_GPIO, 0); |
9418c65f TL |
340 | msleep(50); |
341 | gpio_set_value(N810_EMMC_VSD_GPIO, 0); | |
342 | msleep(50); | |
343 | } | |
344 | } | |
345 | ||
346 | static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on, | |
347 | int vdd) | |
348 | { | |
349 | if (machine_is_nokia_n800() || slot == 0) | |
350 | return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd); | |
351 | ||
352 | n810_set_power_emmc(dev, power_on); | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | static int n8x0_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode) | |
358 | { | |
359 | int r; | |
360 | ||
361 | dev_dbg(dev, "Set slot %d bus mode %s\n", slot + 1, | |
362 | bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull"); | |
363 | BUG_ON(slot != 0 && slot != 1); | |
364 | slot++; | |
365 | switch (bus_mode) { | |
366 | case MMC_BUSMODE_OPENDRAIN: | |
367 | r = menelaus_set_mmc_opendrain(slot, 1); | |
368 | break; | |
369 | case MMC_BUSMODE_PUSHPULL: | |
370 | r = menelaus_set_mmc_opendrain(slot, 0); | |
371 | break; | |
372 | default: | |
373 | BUG(); | |
374 | } | |
375 | if (r != 0 && printk_ratelimit()) | |
376 | dev_err(dev, "MMC: unable to set bus mode for slot %d\n", | |
377 | slot); | |
378 | return r; | |
379 | } | |
380 | ||
381 | static int n8x0_mmc_get_cover_state(struct device *dev, int slot) | |
382 | { | |
383 | slot++; | |
384 | BUG_ON(slot != 1 && slot != 2); | |
385 | if (slot == 1) | |
386 | return slot1_cover_open; | |
387 | else | |
388 | return slot2_cover_open; | |
389 | } | |
390 | ||
391 | static void n8x0_mmc_callback(void *data, u8 card_mask) | |
392 | { | |
393 | int bit, *openp, index; | |
394 | ||
395 | if (machine_is_nokia_n800()) { | |
396 | bit = 1 << 1; | |
397 | openp = &slot2_cover_open; | |
398 | index = 1; | |
399 | } else { | |
400 | bit = 1; | |
401 | openp = &slot1_cover_open; | |
402 | index = 0; | |
403 | } | |
404 | ||
405 | if (card_mask & bit) | |
406 | *openp = 1; | |
407 | else | |
408 | *openp = 0; | |
409 | ||
d5171102 | 410 | #ifdef CONFIG_MMC_OMAP |
9418c65f | 411 | omap_mmc_notify_cover_event(mmc_device, index, *openp); |
d5171102 TL |
412 | #else |
413 | pr_warn("MMC: notify cover event not available\n"); | |
414 | #endif | |
9418c65f TL |
415 | } |
416 | ||
9418c65f TL |
417 | static int n8x0_mmc_late_init(struct device *dev) |
418 | { | |
419 | int r, bit, *openp; | |
420 | int vs2sel; | |
421 | ||
422 | mmc_device = dev; | |
423 | ||
424 | r = menelaus_set_slot_sel(1); | |
425 | if (r < 0) | |
426 | return r; | |
427 | ||
428 | if (machine_is_nokia_n800()) | |
429 | vs2sel = 0; | |
430 | else | |
431 | vs2sel = 2; | |
432 | ||
433 | r = menelaus_set_mmc_slot(2, 0, vs2sel, 1); | |
434 | if (r < 0) | |
435 | return r; | |
436 | ||
437 | n8x0_mmc_set_power(dev, 0, MMC_POWER_ON, 16); /* MMC_VDD_28_29 */ | |
438 | n8x0_mmc_set_power(dev, 1, MMC_POWER_ON, 16); | |
439 | ||
440 | r = menelaus_set_mmc_slot(1, 1, 0, 1); | |
441 | if (r < 0) | |
442 | return r; | |
443 | r = menelaus_set_mmc_slot(2, 1, vs2sel, 1); | |
444 | if (r < 0) | |
445 | return r; | |
446 | ||
447 | r = menelaus_get_slot_pin_states(); | |
448 | if (r < 0) | |
449 | return r; | |
450 | ||
451 | if (machine_is_nokia_n800()) { | |
452 | bit = 1 << 1; | |
453 | openp = &slot2_cover_open; | |
454 | } else { | |
455 | bit = 1; | |
456 | openp = &slot1_cover_open; | |
457 | slot2_cover_open = 0; | |
458 | } | |
459 | ||
460 | /* All slot pin bits seem to be inversed until first switch change */ | |
461 | if (r == 0xf || r == (0xf & ~bit)) | |
462 | r = ~r; | |
463 | ||
464 | if (r & bit) | |
465 | *openp = 1; | |
466 | else | |
467 | *openp = 0; | |
468 | ||
469 | r = menelaus_register_mmc_callback(n8x0_mmc_callback, NULL); | |
470 | ||
471 | return r; | |
472 | } | |
473 | ||
474 | static void n8x0_mmc_shutdown(struct device *dev) | |
475 | { | |
476 | int vs2sel; | |
477 | ||
478 | if (machine_is_nokia_n800()) | |
479 | vs2sel = 0; | |
480 | else | |
481 | vs2sel = 2; | |
482 | ||
483 | menelaus_set_mmc_slot(1, 0, 0, 0); | |
484 | menelaus_set_mmc_slot(2, 0, vs2sel, 0); | |
485 | } | |
486 | ||
487 | static void n8x0_mmc_cleanup(struct device *dev) | |
488 | { | |
489 | menelaus_unregister_mmc_callback(); | |
490 | ||
491 | gpio_free(N8X0_SLOT_SWITCH_GPIO); | |
492 | ||
493 | if (machine_is_nokia_n810()) { | |
494 | gpio_free(N810_EMMC_VSD_GPIO); | |
1dea5c6b | 495 | gpio_free(N810_EMMC_VIO_GPIO); |
9418c65f TL |
496 | } |
497 | } | |
498 | ||
499 | /* | |
500 | * MMC controller1 has two slots that are multiplexed via I2C. | |
501 | * MMC controller2 is not in use. | |
502 | */ | |
503 | static struct omap_mmc_platform_data mmc1_data = { | |
504 | .nr_slots = 2, | |
505 | .switch_slot = n8x0_mmc_switch_slot, | |
506 | .init = n8x0_mmc_late_init, | |
507 | .cleanup = n8x0_mmc_cleanup, | |
508 | .shutdown = n8x0_mmc_shutdown, | |
509 | .max_freq = 24000000, | |
9418c65f TL |
510 | .slots[0] = { |
511 | .wires = 4, | |
512 | .set_power = n8x0_mmc_set_power, | |
513 | .set_bus_mode = n8x0_mmc_set_bus_mode, | |
514 | .get_cover_state = n8x0_mmc_get_cover_state, | |
515 | .ocr_mask = MMC_VDD_165_195 | MMC_VDD_30_31 | | |
516 | MMC_VDD_32_33 | MMC_VDD_33_34, | |
517 | .name = "internal", | |
518 | }, | |
519 | .slots[1] = { | |
520 | .set_power = n8x0_mmc_set_power, | |
521 | .set_bus_mode = n8x0_mmc_set_bus_mode, | |
522 | .get_cover_state = n8x0_mmc_get_cover_state, | |
523 | .ocr_mask = MMC_VDD_165_195 | MMC_VDD_20_21 | | |
524 | MMC_VDD_21_22 | MMC_VDD_22_23 | | |
525 | MMC_VDD_23_24 | MMC_VDD_24_25 | | |
526 | MMC_VDD_27_28 | MMC_VDD_28_29 | | |
527 | MMC_VDD_29_30 | MMC_VDD_30_31 | | |
528 | MMC_VDD_32_33 | MMC_VDD_33_34, | |
529 | .name = "external", | |
530 | }, | |
531 | }; | |
532 | ||
533 | static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC]; | |
534 | ||
bc593f5d IG |
535 | static struct gpio n810_emmc_gpios[] __initdata = { |
536 | { N810_EMMC_VSD_GPIO, GPIOF_OUT_INIT_LOW, "MMC slot 2 Vddf" }, | |
537 | { N810_EMMC_VIO_GPIO, GPIOF_OUT_INIT_LOW, "MMC slot 2 Vdd" }, | |
538 | }; | |
9418c65f | 539 | |
bc593f5d | 540 | static void __init n8x0_mmc_init(void) |
9418c65f TL |
541 | { |
542 | int err; | |
543 | ||
544 | if (machine_is_nokia_n810()) { | |
545 | mmc1_data.slots[0].name = "external"; | |
546 | ||
547 | /* | |
548 | * Some Samsung Movinand chips do not like open-ended | |
549 | * multi-block reads and fall to braind-dead state | |
550 | * while doing so. Reducing the number of blocks in | |
551 | * the transfer or delays in clock disable do not help | |
552 | */ | |
553 | mmc1_data.slots[1].name = "internal"; | |
554 | mmc1_data.slots[1].ban_openended = 1; | |
555 | } | |
556 | ||
bc593f5d IG |
557 | err = gpio_request_one(N8X0_SLOT_SWITCH_GPIO, GPIOF_OUT_INIT_LOW, |
558 | "MMC slot switch"); | |
9418c65f | 559 | if (err) |
1dea5c6b | 560 | return; |
9418c65f | 561 | |
9418c65f | 562 | if (machine_is_nokia_n810()) { |
bc593f5d IG |
563 | err = gpio_request_array(n810_emmc_gpios, |
564 | ARRAY_SIZE(n810_emmc_gpios)); | |
9418c65f TL |
565 | if (err) { |
566 | gpio_free(N8X0_SLOT_SWITCH_GPIO); | |
1dea5c6b | 567 | return; |
9418c65f | 568 | } |
9418c65f TL |
569 | } |
570 | ||
571 | mmc_data[0] = &mmc1_data; | |
e08016d0 | 572 | omap242x_init_mmc(mmc_data); |
9418c65f TL |
573 | } |
574 | #else | |
575 | ||
576 | void __init n8x0_mmc_init(void) | |
577 | { | |
578 | } | |
9418c65f TL |
579 | #endif /* CONFIG_MMC_OMAP */ |
580 | ||
581 | #ifdef CONFIG_MENELAUS | |
582 | ||
583 | static int n8x0_auto_sleep_regulators(void) | |
584 | { | |
585 | u32 val; | |
586 | int ret; | |
587 | ||
588 | val = EN_VPLL_SLEEP | EN_VMMC_SLEEP \ | |
589 | | EN_VAUX_SLEEP | EN_VIO_SLEEP \ | |
590 | | EN_VMEM_SLEEP | EN_DC3_SLEEP \ | |
591 | | EN_VC_SLEEP | EN_DC2_SLEEP; | |
592 | ||
593 | ret = menelaus_set_regulator_sleep(1, val); | |
594 | if (ret < 0) { | |
7852ec05 PW |
595 | pr_err("Could not set regulators to sleep on menelaus: %u\n", |
596 | ret); | |
9418c65f TL |
597 | return ret; |
598 | } | |
599 | return 0; | |
600 | } | |
601 | ||
602 | static int n8x0_auto_voltage_scale(void) | |
603 | { | |
604 | int ret; | |
605 | ||
606 | ret = menelaus_set_vcore_hw(1400, 1050); | |
607 | if (ret < 0) { | |
7852ec05 | 608 | pr_err("Could not set VCORE voltage on menelaus: %u\n", ret); |
9418c65f TL |
609 | return ret; |
610 | } | |
611 | return 0; | |
612 | } | |
613 | ||
614 | static int n8x0_menelaus_late_init(struct device *dev) | |
615 | { | |
616 | int ret; | |
617 | ||
618 | ret = n8x0_auto_voltage_scale(); | |
619 | if (ret < 0) | |
620 | return ret; | |
621 | ret = n8x0_auto_sleep_regulators(); | |
622 | if (ret < 0) | |
623 | return ret; | |
624 | return 0; | |
625 | } | |
626 | ||
a7f97d25 JN |
627 | #else |
628 | static int n8x0_menelaus_late_init(struct device *dev) | |
629 | { | |
630 | return 0; | |
631 | } | |
632 | #endif | |
633 | ||
634 | static struct menelaus_platform_data n8x0_menelaus_platform_data __initdata = { | |
635 | .late_init = n8x0_menelaus_late_init, | |
636 | }; | |
637 | ||
638 | static struct i2c_board_info __initdata n8x0_i2c_board_info_1[] __initdata = { | |
9418c65f TL |
639 | { |
640 | I2C_BOARD_INFO("menelaus", 0x72), | |
7d7e1eba | 641 | .irq = 7 + OMAP_INTC_START, |
a7f97d25 | 642 | .platform_data = &n8x0_menelaus_platform_data, |
9418c65f TL |
643 | }, |
644 | }; | |
645 | ||
366498d4 JN |
646 | static struct aic3x_pdata n810_aic33_data __initdata = { |
647 | .gpio_reset = 118, | |
9418c65f TL |
648 | }; |
649 | ||
366498d4 JN |
650 | static struct i2c_board_info n810_i2c_board_info_2[] __initdata = { |
651 | { | |
652 | I2C_BOARD_INFO("tlv320aic3x", 0x18), | |
653 | .platform_data = &n810_aic33_data, | |
654 | }, | |
655 | }; | |
9418c65f | 656 | |
bd8f0fc9 TL |
657 | #ifdef CONFIG_OMAP_MUX |
658 | static struct omap_board_mux board_mux[] __initdata = { | |
04be1e9b JN |
659 | /* I2S codec port pins for McBSP block */ |
660 | OMAP2420_MUX(EAC_AC_SCLK, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
661 | OMAP2420_MUX(EAC_AC_FS, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
662 | OMAP2420_MUX(EAC_AC_DIN, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
663 | OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
bd8f0fc9 TL |
664 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
665 | }; | |
0b50c691 TL |
666 | |
667 | static struct omap_device_pad serial2_pads[] __initdata = { | |
668 | { | |
669 | .name = "uart3_rx_irrx.uart3_rx_irrx", | |
670 | .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, | |
671 | .enable = OMAP_MUX_MODE0, | |
672 | .idle = OMAP_MUX_MODE3 /* Mux as GPIO for idle */ | |
673 | }, | |
674 | }; | |
675 | ||
676 | static inline void board_serial_init(void) | |
677 | { | |
678 | struct omap_board_data bdata; | |
679 | ||
680 | bdata.flags = 0; | |
681 | bdata.pads = NULL; | |
682 | bdata.pads_cnt = 0; | |
683 | ||
684 | bdata.id = 0; | |
c86845db | 685 | omap_serial_init_port(&bdata, NULL); |
0b50c691 TL |
686 | |
687 | bdata.id = 1; | |
c86845db | 688 | omap_serial_init_port(&bdata, NULL); |
0b50c691 TL |
689 | |
690 | bdata.id = 2; | |
691 | bdata.pads = serial2_pads; | |
692 | bdata.pads_cnt = ARRAY_SIZE(serial2_pads); | |
c86845db | 693 | omap_serial_init_port(&bdata, NULL); |
0b50c691 TL |
694 | } |
695 | ||
696 | #else | |
697 | ||
698 | static inline void board_serial_init(void) | |
699 | { | |
700 | omap_serial_init(); | |
701 | } | |
702 | ||
bd8f0fc9 TL |
703 | #endif |
704 | ||
63138812 KV |
705 | static void __init n8x0_init_machine(void) |
706 | { | |
bd8f0fc9 | 707 | omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); |
63138812 KV |
708 | /* FIXME: add n810 spi devices */ |
709 | spi_register_board_info(n800_spi_board_info, | |
710 | ARRAY_SIZE(n800_spi_board_info)); | |
a7f97d25 JN |
711 | omap_register_i2c_bus(1, 400, n8x0_i2c_board_info_1, |
712 | ARRAY_SIZE(n8x0_i2c_board_info_1)); | |
366498d4 JN |
713 | omap_register_i2c_bus(2, 400, NULL, 0); |
714 | if (machine_is_nokia_n810()) | |
715 | i2c_register_board_info(2, n810_i2c_board_info_2, | |
716 | ARRAY_SIZE(n810_i2c_board_info_2)); | |
0b50c691 | 717 | board_serial_init(); |
a4ca9dbe | 718 | omap_sdrc_init(NULL, NULL); |
a1a92e6f | 719 | gpmc_onenand_init(board_onenand_data); |
9418c65f | 720 | n8x0_mmc_init(); |
97b9ad16 | 721 | n8x0_usb_init(); |
0857ba3c | 722 | n8x0_cbus_init(); |
63138812 KV |
723 | } |
724 | ||
725 | MACHINE_START(NOKIA_N800, "Nokia N800") | |
5e52b435 | 726 | .atag_offset = 0x100, |
71ee7dad | 727 | .reserve = omap_reserve, |
e990a406 | 728 | .map_io = omap242x_map_io, |
8f5b5a41 | 729 | .init_early = omap2420_init_early, |
741e3a89 | 730 | .init_irq = omap2_init_irq, |
6b2f55d7 | 731 | .handle_irq = omap2_intc_handle_irq, |
63138812 | 732 | .init_machine = n8x0_init_machine, |
bbd707ac | 733 | .init_late = omap2420_init_late, |
6bb27d73 | 734 | .init_time = omap2_sync32k_timer_init, |
187e3e06 | 735 | .restart = omap2xxx_restart, |
63138812 KV |
736 | MACHINE_END |
737 | ||
738 | MACHINE_START(NOKIA_N810, "Nokia N810") | |
5e52b435 | 739 | .atag_offset = 0x100, |
71ee7dad | 740 | .reserve = omap_reserve, |
e990a406 | 741 | .map_io = omap242x_map_io, |
8f5b5a41 | 742 | .init_early = omap2420_init_early, |
741e3a89 | 743 | .init_irq = omap2_init_irq, |
6b2f55d7 | 744 | .handle_irq = omap2_intc_handle_irq, |
63138812 | 745 | .init_machine = n8x0_init_machine, |
bbd707ac | 746 | .init_late = omap2420_init_late, |
6bb27d73 | 747 | .init_time = omap2_sync32k_timer_init, |
187e3e06 | 748 | .restart = omap2xxx_restart, |
63138812 KV |
749 | MACHINE_END |
750 | ||
751 | MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") | |
5e52b435 | 752 | .atag_offset = 0x100, |
71ee7dad | 753 | .reserve = omap_reserve, |
e990a406 | 754 | .map_io = omap242x_map_io, |
8f5b5a41 | 755 | .init_early = omap2420_init_early, |
741e3a89 | 756 | .init_irq = omap2_init_irq, |
6b2f55d7 | 757 | .handle_irq = omap2_intc_handle_irq, |
63138812 | 758 | .init_machine = n8x0_init_machine, |
bbd707ac | 759 | .init_late = omap2420_init_late, |
6bb27d73 | 760 | .init_time = omap2_sync32k_timer_init, |
187e3e06 | 761 | .restart = omap2xxx_restart, |
63138812 | 762 | MACHINE_END |