[thirdparty/u-boot.git] / arch / arm / mach-omap2 / omap3 / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <sunilsaini05@gmail.com>
 *      Shashi Ranjan <shashiranjanmca05@gmail.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 */
#include <common.h>
#include <dm.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <asm/gpio.h>
#include <asm/omap_common.h>
#include <linux/compiler.h>

/* Declarations */
extern omap3_sysinfo sysinfo;
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_invalidate_l2_cache_secure(void);
#endif

#ifdef CONFIG_DM_GPIO
static const struct omap_gpio_platdata omap34xx_gpio[] = {
	{ 0, OMAP34XX_GPIO1_BASE },
	{ 1, OMAP34XX_GPIO2_BASE },
	{ 2, OMAP34XX_GPIO3_BASE },
	{ 3, OMAP34XX_GPIO4_BASE },
	{ 4, OMAP34XX_GPIO5_BASE },
	{ 5, OMAP34XX_GPIO6_BASE },
};

U_BOOT_DEVICES(omap34xx_gpios) = {
	{ "gpio_omap", &omap34xx_gpio[0] },
	{ "gpio_omap", &omap34xx_gpio[1] },
	{ "gpio_omap", &omap34xx_gpio[2] },
	{ "gpio_omap", &omap34xx_gpio[3] },
	{ "gpio_omap", &omap34xx_gpio[4] },
	{ "gpio_omap", &omap34xx_gpio[5] },
};

#else

static const struct gpio_bank gpio_bank_34xx[6] = {
	{ (void *)OMAP34XX_GPIO1_BASE },
	{ (void *)OMAP34XX_GPIO2_BASE },
	{ (void *)OMAP34XX_GPIO3_BASE },
	{ (void *)OMAP34XX_GPIO4_BASE },
	{ (void *)OMAP34XX_GPIO5_BASE },
	{ (void *)OMAP34XX_GPIO6_BASE },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;

#endif

/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
void secure_unlock_mem(void)
{
	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
void secureworld_exit(void)
{
	unsigned long i;

	/* configure non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
void try_unlock_memory(void)
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

void early_system_init(void)
{
	hw_data_init();
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	watchdog_init();
	early_system_init();

	try_unlock_memory();

#ifndef CONFIG_SYS_L2CACHE_OFF
	/* Invalidate L2-cache from secure mode */
	omap3_invalidate_l2_cache_secure();
#endif

	set_muxconf_regs();
	sdelay(100);

	prcm_init();

	per_clocks_enable();

#ifdef CONFIG_USB_EHCI_OMAP
	ehci_clocks_enable();
#endif
}

#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
	early_system_init();
	mem_init();
	/*
	* Save the boot parameters passed from romcode.
	* We cannot delay the saving further than this,
	* to prevent overwrites.
	*/
	save_omap_boot_params();
}
#endif

/*
 * Routine: misc_init_r
 * Description: A basic misc_init_r that just displays the die ID
 */
int __weak misc_init_r(void)
{
	omap_die_id_display();

	return 0;
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
static void wait_for_command_complete(struct watchdog *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	setbits_le32(&prcm_base->fclken_wkup, 0x20);
	setbits_le32(&prcm_base->iclken_wkup, 0x20);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	int hw, strength = 1;

	if (argc < 2 || argc > 3)
		goto usage;

	if (strncmp(argv[1], "hw", 2) == 0) {
		hw = 1;
		if (argc == 3) {
			if (strncmp(argv[2], "bch8", 4) == 0)
				strength = 8;
			else if (strncmp(argv[2], "bch16", 5) == 0)
				strength = 16;
			else if (strncmp(argv[2], "hamming", 7) != 0)
				goto usage;
		}
	} else if (strncmp(argv[1], "sw", 2) == 0) {
		hw = 0;
		if (argc == 3) {
			if (strncmp(argv[2], "bch8", 4) == 0)
				strength = 8;
			else if (strncmp(argv[2], "hamming", 7) != 0)
				goto usage;
		}
	} else {
		goto usage;
	}

	return -omap_nand_switch_ecc(hw, strength);

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 3, 1,	do_switch_ecc,
	"switch OMAP3 NAND ECC calculation algorithm",
	"hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
	" and 8-bit/16-bit BCH\n"
	"                           ecc calculation (second parameter may"
	" be omitted).\n"
	"nandecc sw               - Switch to NAND software ecc algorithm."
);

#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */

#ifdef CONFIG_DISPLAY_BOARDINFO
/**
 * Print board information
 */
int checkboard (void)
{
	char *mem_s ;

	if (is_mem_sdr())
		mem_s = "mSDR";
	else
		mem_s = "LPDDR";

	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
			sysinfo.nand_string);

	return 0;
}
#endif	/* CONFIG_DISPLAY_BOARDINFO */

static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
{
	u32 i, num_params = *parameters;
	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;

	/*
	 * copy the parameters to an un-cached area to avoid coherency
	 * issues
	 */
	for (i = 0; i < num_params; i++) {
		__raw_writel(*parameters, sram_scratch_space);
		parameters++;
		sram_scratch_space++;
	}

	/* Now make the PPA call */
	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}

void __weak omap3_set_aux_cr_secure(u32 acr)
{
	struct emu_hal_params emu_romcode_params;

	emu_romcode_params.num_params = 1;
	emu_romcode_params.param1 = acr;
	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
			       (u32 *)&emu_romcode_params);
}

void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
				 u32 cpu_rev_comb, u32 cpu_variant,
				 u32 cpu_rev)
{
	if (get_device_type() == GP_DEVICE)
		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);

	/* L2 Cache Auxiliary Control Register is not banked */
}

void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
			  u32 cpu_variant, u32 cpu_rev)
{
	/* Write ACR - affects secure banked bits */
	if (get_device_type() == GP_DEVICE)
		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
	else
		omap3_set_aux_cr_secure(acr);

	/* Write ACR - affects non-secure banked bits - some erratas need it */
	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}


#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;
	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);

}

/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
	if (get_device_type() == GP_DEVICE) {
		omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = 0;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
				       (u32 *)&emu_romcode_params);
	}
}

void v7_outer_cache_enable(void)
{

	/*
	 * Set L2EN
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in setting both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0x2, 0);
}

void omap3_outer_cache_disable(void)
{
	/*
	 * Clear L2EN
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in clearing both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0, 0x2);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
91eee546 DB	2	/*
	3	*
	4	* Common board functions for OMAP3 based boards.
	5	*
	6	* (C) Copyright 2004-2008
	7	* Texas Instruments, <www.ti.com>
	8	*
	9	* Author :
	10	* Sunil Kumar <sunilsaini05@gmail.com>
	11	* Shashi Ranjan <shashiranjanmca05@gmail.com>
	12	*
	13	* Derived from Beagle Board and 3430 SDP code by
	14	* Richard Woodruff <r-woodruff2@ti.com>
	15	* Syed Mohammed Khasim <khasim@ti.com>
	16	*
91eee546 DB	17	*/
91eee546 DB	18	#include <common.h>
b3f4ca11	19	#include <dm.h>
47f7bcae	20	#include <spl.h>
91eee546 DB	21	#include <asm/io.h>
	22	#include <asm/arch/sys_proto.h>
	23	#include <asm/arch/mem.h>
06e758e7	24	#include <asm/cache.h>
45bf0585	25	#include <asm/armv7.h>
b3f4ca11	26	#include <asm/gpio.h>
bb085b87	27	#include <asm/omap_common.h>
8a87a3d7	28	#include <linux/compiler.h>
91eee546	29
45bf0585	30	/* Declarations */
91eee546	31	extern omap3_sysinfo sysinfo;
57f588be	32	#ifndef CONFIG_SYS_L2CACHE_OFF
45bf0585	33	static void omap3_invalidate_l2_cache_secure(void);
57f588be	34	#endif
91eee546	35
b3f4ca11 SG	36	#ifdef CONFIG_DM_GPIO
b3f4ca11 SG	37	static const struct omap_gpio_platdata omap34xx_gpio[] = {
0a9e3405 TR	38	{ 0, OMAP34XX_GPIO1_BASE },
	39	{ 1, OMAP34XX_GPIO2_BASE },
	40	{ 2, OMAP34XX_GPIO3_BASE },
	41	{ 3, OMAP34XX_GPIO4_BASE },
	42	{ 4, OMAP34XX_GPIO5_BASE },
	43	{ 5, OMAP34XX_GPIO6_BASE },
b3f4ca11 SG	44	};
b3f4ca11 SG	45
44913aa5	46	U_BOOT_DEVICES(omap34xx_gpios) = {
b3f4ca11 SG	47	{ "gpio_omap", &omap34xx_gpio[0] },
	48	{ "gpio_omap", &omap34xx_gpio[1] },
	49	{ "gpio_omap", &omap34xx_gpio[2] },
	50	{ "gpio_omap", &omap34xx_gpio[3] },
	51	{ "gpio_omap", &omap34xx_gpio[4] },
	52	{ "gpio_omap", &omap34xx_gpio[5] },
	53	};
	54
	55	#else
	56
25223a68	57	static const struct gpio_bank gpio_bank_34xx[6] = {
0a9e3405 TR	58	{ (void *)OMAP34XX_GPIO1_BASE },
	59	{ (void *)OMAP34XX_GPIO2_BASE },
	60	{ (void *)OMAP34XX_GPIO3_BASE },
	61	{ (void *)OMAP34XX_GPIO4_BASE },
	62	{ (void *)OMAP34XX_GPIO5_BASE },
	63	{ (void *)OMAP34XX_GPIO6_BASE },
25223a68 A	64	};
	65
	66	const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
	67
b3f4ca11 SG	68	#endif
b3f4ca11 SG	69
91eee546 DB	70	/******************************************************************************
	71	* Routine: secure_unlock
	72	* Description: Setup security registers for access
	73	* (GP Device only)
	74	*****************************************************************************/
	75	void secure_unlock_mem(void)
	76	{
97a099ea DB	77	struct pm pm_rt_ape_base = (struct pm )PM_RT_APE_BASE_ADDR_ARM;
	78	struct pm pm_gpmc_base = (struct pm )PM_GPMC_BASE_ADDR_ARM;
	79	struct pm pm_ocm_ram_base = (struct pm )PM_OCM_RAM_BASE_ADDR_ARM;
	80	struct pm pm_iva2_base = (struct pm )PM_IVA2_BASE_ADDR_ARM;
	81	struct sms sms_base = (struct sms )OMAP34XX_SMS_BASE;
91eee546 DB	82
	83	/* Protection Module Register Target APE (PM_RT) */
	84	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	85	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	86	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	87	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
	88
	89	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	90	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	91	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
	92
	93	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	94	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	95	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	96	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
	97
	98	/* IVA Changes */
	99	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	100	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	101	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
	102
	103	/* SDRC region 0 public */
	104	writel(UNLOCK_1, &sms_base->rg_att0);
	105	}
	106
	107	/******************************************************************************
	108	* Routine: secureworld_exit()
	109	* Description: If chip is EMU and boot type is external
	110	* configure secure registers and exit secure world
	111	* general use.
	112	*****************************************************************************/
fd3f401b	113	void secureworld_exit(void)
91eee546 DB	114	{
	115	unsigned long i;
	116
a4958313	117	/* configure non-secure access control register */
91eee546 DB	118	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	119	/* enabling co-processor CP10 and CP11 accesses in NS world */
	120	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	121	/*
	122	* allow allocation of locked TLBs and L2 lines in NS world
	123	* allow use of PLE registers in NS world also
	124	*/
	125	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	126	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
	127
	128	/* Enable ASA in ACR register */
	129	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	130	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	131	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	132
	133	/* Exiting secure world */
	134	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	135	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	136	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
	137	}
	138
91eee546 DB	139	/******************************************************************************
	140	* Routine: try_unlock_sram()
	141	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
	142	* general use.
	143	*****************************************************************************/
fd3f401b	144	void try_unlock_memory(void)
91eee546 DB	145	{
	146	int mode;
	147	int in_sdram = is_running_in_sdram();
	148
	149	/*
	150	* if GP device unlock device SRAM for general use
	151	* secure code breaks for Secure/Emulation device - HS/E/T
	152	*/
	153	mode = get_device_type();
	154	if (mode == GP_DEVICE)
	155	secure_unlock_mem();
	156
	157	/*
	158	* If device is EMU and boot is XIP external booting
	159	* Unlock firewalls and disable L2 and put chip
	160	* out of secure world
	161	*
	162	* Assuming memories are unlocked by the demon who put us in SDRAM
	163	*/
	164	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	165	&& (!in_sdram)) {
	166	secure_unlock_mem();
	167	secureworld_exit();
	168	}
	169
	170	return;
	171	}
	172
00bbe96e SP	173	void early_system_init(void)
	174	{
	175	hw_data_init();
	176	}
	177
91eee546 DB	178	/******************************************************************************
	179	* Routine: s_init
	180	* Description: Does early system init of muxing and clocks.
	181	* - Called path is with SRAM stack.
	182	*****************************************************************************/
	183	void s_init(void)
	184	{
91eee546	185	watchdog_init();
00bbe96e	186	early_system_init();
91eee546 DB	187
	188	try_unlock_memory();
	189
45bf0585 A	190	#ifndef CONFIG_SYS_L2CACHE_OFF
	191	/* Invalidate L2-cache from secure mode */
	192	omap3_invalidate_l2_cache_secure();
91eee546	193	#endif
91eee546 DB	194
91eee546 DB	195	set_muxconf_regs();
86623add	196	sdelay(100);
91eee546 DB	197
	198	prcm_init();
	199
	200	per_clocks_enable();
	201
95f87910 G	202	#ifdef CONFIG_USB_EHCI_OMAP
	203	ehci_clocks_enable();
	204	#endif
7ae8350f	205	}
95f87910	206
7ae8350f SG	207	#ifdef CONFIG_SPL_BUILD
	208	void board_init_f(ulong dummy)
	209	{
00bbe96e	210	early_system_init();
7ae8350f	211	mem_init();
c3bec547 AF	212	/*
	213	* Save the boot parameters passed from romcode.
	214	* We cannot delay the saving further than this,
	215	* to prevent overwrites.
	216	*/
	217	save_omap_boot_params();
91eee546	218	}
7ae8350f	219	#endif
91eee546	220
8a87a3d7 TR	221	/*
	222	* Routine: misc_init_r
	223	* Description: A basic misc_init_r that just displays the die ID
	224	*/
	225	int __weak misc_init_r(void)
	226	{
679f82c3	227	omap_die_id_display();
8a87a3d7 TR	228
	229	return 0;
	230	}
	231
91eee546 DB	232	/******************************************************************************
	233	* Routine: wait_for_command_complete
	234	* Description: Wait for posting to finish on watchdog
	235	*****************************************************************************/
98431d58	236	static void wait_for_command_complete(struct watchdog *wd_base)
91eee546 DB	237	{
	238	int pending = 1;
	239	do {
	240	pending = readl(&wd_base->wwps);
	241	} while (pending);
	242	}
	243
	244	/******************************************************************************
	245	* Routine: watchdog_init
	246	* Description: Shut down watch dogs
	247	*****************************************************************************/
	248	void watchdog_init(void)
	249	{
97a099ea DB	250	struct watchdog wd2_base = (struct watchdog )WD2_BASE;
97a099ea DB	251	struct prcm prcm_base = (struct prcm )PRCM_BASE;
91eee546 DB	252
	253	/*
	254	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	255	* either taken care of by ROM (HS/EMU) or not accessible (GP).
	256	* We need to take care of WD2-MPU or take a PRCM reset. WD3
	257	* should not be running and does not generate a PRCM reset.
	258	*/
	259
e7300f46 WD	260	setbits_le32(&prcm_base->fclken_wkup, 0x20);
e7300f46 WD	261	setbits_le32(&prcm_base->iclken_wkup, 0x20);
91eee546 DB	262	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
	263
	264	writel(WD_UNLOCK1, &wd2_base->wspr);
	265	wait_for_command_complete(wd2_base);
	266	writel(WD_UNLOCK2, &wd2_base->wspr);
	267	}
	268
91eee546 DB	269	/******************************************************************************
	270	* Dummy function to handle errors for EABI incompatibility
	271	*****************************************************************************/
	272	void abort(void)
	273	{
	274	}
	275
bb085b87	276	#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
91eee546 DB	277	/******************************************************************************
	278	* OMAP3 specific command to switch between NAND HW and SW ecc
	279	*****************************************************************************/
54841ab5	280	static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
91eee546	281	{
50075153 LM	282	int hw, strength = 1;
50075153 LM	283
da634ae3	284	if (argc < 2 \|\| argc > 3)
91eee546	285	goto usage;
da634ae3 AB	286
da634ae3 AB	287	if (strncmp(argv[1], "hw", 2) == 0) {
50075153 LM	288	hw = 1;
	289	if (argc == 3) {
	290	if (strncmp(argv[2], "bch8", 4) == 0)
	291	strength = 8;
3a504d96	292	else if (strncmp(argv[2], "bch16", 5) == 0)
50075153 LM	293	strength = 16;
50075153 LM	294	else if (strncmp(argv[2], "hamming", 7) != 0)
da634ae3 AB	295	goto usage;
	296	}
	297	} else if (strncmp(argv[1], "sw", 2) == 0) {
50075153 LM	298	hw = 0;
	299	if (argc == 3) {
	300	if (strncmp(argv[2], "bch8", 4) == 0)
	301	strength = 8;
	302	else if (strncmp(argv[2], "hamming", 7) != 0)
b050898e AC	303	goto usage;
b050898e AC	304	}
da634ae3	305	} else {
91eee546	306	goto usage;
da634ae3	307	}
91eee546	308
50075153	309	return -omap_nand_switch_ecc(hw, strength);
91eee546 DB	310
91eee546 DB	311	usage:
36003268	312	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	313	return 1;
	314	}
	315
	316	U_BOOT_CMD(
da634ae3	317	nandecc, 3, 1, do_switch_ecc,
a93c92cd	318	"switch OMAP3 NAND ECC calculation algorithm",
3a504d96 HS	319	"hw [hamming\|bch8\|bch16] - Switch between NAND hardware 1-bit hamming"
3a504d96 HS	320	" and 8-bit/16-bit BCH\n"
da634ae3 AB	321	" ecc calculation (second parameter may"
	322	" be omitted).\n"
	323	"nandecc sw - Switch to NAND software ecc algorithm."
a89c33db	324	);
91eee546	325
bb085b87	326	#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
6a6b62e3 SP	327
	328	#ifdef CONFIG_DISPLAY_BOARDINFO
	329	/**
	330	* Print board information
	331	*/
	332	int checkboard (void)
	333	{
	334	char *mem_s ;
	335
	336	if (is_mem_sdr())
	337	mem_s = "mSDR";
	338	else
	339	mem_s = "LPDDR";
	340
	341	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
	342	sysinfo.nand_string);
	343
	344	return 0;
	345	}
	346	#endif /* CONFIG_DISPLAY_BOARDINFO */
45bf0585 A	347
	348	static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
	349	{
	350	u32 i, num_params = *parameters;
	351	u32 sram_scratch_space = (u32 )OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
	352
	353	/*
	354	* copy the parameters to an un-cached area to avoid coherency
	355	* issues
	356	*/
	357	for (i = 0; i < num_params; i++) {
	358	__raw_writel(*parameters, sram_scratch_space);
	359	parameters++;
	360	sram_scratch_space++;
	361	}
	362
	363	/* Now make the PPA call */
	364	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
	365	}
	366
cdef0b3f	367	void __weak omap3_set_aux_cr_secure(u32 acr)
45bf0585	368	{
cdef0b3f NM	369	struct emu_hal_params emu_romcode_params;
	370
	371	emu_romcode_params.num_params = 1;
	372	emu_romcode_params.param1 = acr;
	373	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
	374	(u32 *)&emu_romcode_params);
45bf0585 A	375	}
45bf0585 A	376
19a75b8c SS	377	void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
	378	u32 cpu_rev_comb, u32 cpu_variant,
	379	u32 cpu_rev)
	380	{
	381	if (get_device_type() == GP_DEVICE)
	382	omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
	383
	384	/* L2 Cache Auxiliary Control Register is not banked */
	385	}
	386
cdef0b3f NM	387	void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
cdef0b3f NM	388	u32 cpu_variant, u32 cpu_rev)
45bf0585	389	{
cdef0b3f NM	390	/* Write ACR - affects secure banked bits */
	391	if (get_device_type() == GP_DEVICE)
	392	omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
	393	else
	394	omap3_set_aux_cr_secure(acr);
c6f90e14	395
cdef0b3f NM	396	/* Write ACR - affects non-secure banked bits - some erratas need it */
cdef0b3f NM	397	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
45bf0585 A	398	}
45bf0585 A	399
cdef0b3f	400
45bf0585	401	#ifndef CONFIG_SYS_L2CACHE_OFF
57f588be TR	402	static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
	403	{
	404	u32 acr;
	405
	406	/* Read ACR */
	407	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	408	acr &= ~clear_bits;
	409	acr \|= set_bits;
cdef0b3f	410	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
57f588be	411
57f588be TR	412	}
57f588be TR	413
45bf0585 A	414	/* Invalidate the entire L2 cache from secure mode */
	415	static void omap3_invalidate_l2_cache_secure(void)
	416	{
	417	if (get_device_type() == GP_DEVICE) {
49ec9490	418	omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
45bf0585 A	419	} else {
	420	struct emu_hal_params emu_romcode_params;
	421	emu_romcode_params.num_params = 1;
	422	emu_romcode_params.param1 = 0;
	423	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
	424	(u32 *)&emu_romcode_params);
	425	}
	426	}
	427
	428	void v7_outer_cache_enable(void)
	429	{
45bf0585 A	430
45bf0585 A	431	/*
cdef0b3f	432	* Set L2EN
45bf0585 A	433	* On some revisions L2EN bit is banked on some revisions it's not
	434	* No harm in setting both banked bits(in fact this is required
	435	* by an erratum)
	436	*/
	437	omap3_update_aux_cr(0x2, 0);
	438	}
	439
f1f2c3ca	440	void omap3_outer_cache_disable(void)
45bf0585	441	{
45bf0585	442	/*
cdef0b3f	443	* Clear L2EN
45bf0585 A	444	* On some revisions L2EN bit is banked on some revisions it's not
	445	* No harm in clearing both banked bits(in fact this is required
	446	* by an erratum)
	447	*/
	448	omap3_update_aux_cr(0, 0x2);
	449	}
e3fe6257	450	#endif /* !CONFIG_SYS_L2CACHE_OFF */