[thirdparty/u-boot.git] / arch / arm / mach-omap2 / omap4 / sdram_elpida.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Timing and Organization details of the Elpida parts used in OMAP4
 * SDPs and Panda
 *
 * (C) Copyright 2010
 * Texas Instruments, <www.ti.com>
 *
 * Aneesh V <aneesh@ti.com>
 */

#include <asm/emif.h>
#include <asm/arch/sys_proto.h>

/*
 * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
 * SDP and Panda. Since the parts used and geometry are identical for
 * SDP and Panda for a given OMAP4 revision, this information is kept
 * here instead of being in board directory. However the key functions
 * exported are weakly linked so that they can be over-ridden in the board
 * directory if there is a OMAP4 board in the future that uses a different
 * memory device or geometry.
 *
 * For any new board with different memory devices over-ride one or more
 * of the following functions as per the CONFIG flags you intend to enable:
 * - emif_get_reg_dump()
 * - emif_get_dmm_regs()
 * - emif_get_device_details()
 * - emif_get_device_timings()
 */

#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS

const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
	.sdram_config_init		= 0x80000eb9,
	.sdram_config			= 0x80001ab9,
	.ref_ctrl			= 0x0000030c,
	.sdram_tim1			= 0x08648311,
	.sdram_tim2			= 0x101b06ca,
	.sdram_tim3			= 0x0048a19f,
	.read_idle_ctrl			= 0x000501ff,
	.zq_config			= 0x500b3214,
	.temp_alert_config		= 0xd8016893,
	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
	.emif_ddr_phy_ctlr_1		= 0x049ff808
};

const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
	.sdram_config_init		= 0x80000eb1,
	.sdram_config			= 0x80001ab1,
	.ref_ctrl			= 0x000005cd,
	.sdram_tim1			= 0x10cb0622,
	.sdram_tim2			= 0x20350d52,
	.sdram_tim3			= 0x00b1431f,
	.read_idle_ctrl			= 0x000501ff,
	.zq_config			= 0x500b3214,
	.temp_alert_config		= 0x58016893,
	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
	.emif_ddr_phy_ctlr_1		= 0x049ff418
};

const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
	.sdram_config_init		= 0x80800eb2,
	.sdram_config			= 0x80801ab2,
	.ref_ctrl			= 0x00000618,
	.sdram_tim1			= 0x10eb0662,
	.sdram_tim2			= 0x20370dd2,
	.sdram_tim3			= 0x00b1c33f,
	.read_idle_ctrl			= 0x000501ff,
	.zq_config			= 0x500b3215,
	.temp_alert_config		= 0x58016893,
	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
	.emif_ddr_phy_ctlr_1		= 0x049ff418
};

const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
	.sdram_config_init		= 0x80000eb9,
	.sdram_config			= 0x80001ab9,
	.ref_ctrl			= 0x00000618,
	.sdram_tim1			= 0x10eb0662,
	.sdram_tim2			= 0x20370dd2,
	.sdram_tim3			= 0x00b1c33f,
	.read_idle_ctrl			= 0x000501ff,
	.zq_config			= 0xd00b3214,
	.temp_alert_config		= 0xd8016893,
	.emif_ddr_phy_ctlr_1_init	= 0x049ffff5,
	.emif_ddr_phy_ctlr_1		= 0x049ff418
};

const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
	.dmm_lisa_map_0 = 0xFF020100,
	.dmm_lisa_map_1 = 0,
	.dmm_lisa_map_2 = 0,
	.dmm_lisa_map_3 = 0x80540300,
	.is_ma_present	= 0x0
};

const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
	.dmm_lisa_map_0 = 0xFF020100,
	.dmm_lisa_map_1 = 0,
	.dmm_lisa_map_2 = 0,
	.dmm_lisa_map_3 = 0x80640300,
	.is_ma_present	= 0x0
};

const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
	.dmm_lisa_map_0 = 0xFF020100,
	.dmm_lisa_map_1 = 0,
	.dmm_lisa_map_2 = 0,
	.dmm_lisa_map_3 = 0x80640300,
	.is_ma_present	= 0x1
};

static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
{
	u32 omap4_rev = omap_revision();

	/* Same devices and geometry on both EMIFs */
	if (omap4_rev == OMAP4430_ES1_0)
		*regs = &emif_regs_elpida_380_mhz_1cs;
	else if (omap4_rev == OMAP4430_ES2_0)
		*regs = &emif_regs_elpida_200_mhz_2cs;
	else if (omap4_rev < OMAP4470_ES1_0)
		*regs = &emif_regs_elpida_400_mhz_2cs;
	else
		*regs = &emif_regs_elpida_400_mhz_1cs;
}
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
	__attribute__((weak, alias("emif_get_reg_dump_sdp")));

static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
						**dmm_lisa_regs)
{
	u32 omap_rev = omap_revision();

	if (omap_rev == OMAP4430_ES1_0)
		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
	else if (omap_rev < OMAP4460_ES1_0)
		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
	else
		*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
}

void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));

#else

const struct lpddr2_device_details elpida_2G_S4_details = {
	.type		= LPDDR2_TYPE_S4,
	.density	= LPDDR2_DENSITY_2Gb,
	.io_width	= LPDDR2_IO_WIDTH_32,
	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
};

const struct lpddr2_device_details elpida_4G_S4_details = {
	.type		= LPDDR2_TYPE_S4,
	.density	= LPDDR2_DENSITY_4Gb,
	.io_width	= LPDDR2_IO_WIDTH_32,
	.manufacturer	= LPDDR2_MANUFACTURER_ELPIDA
};

struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
			struct lpddr2_device_details *lpddr2_dev_details)
{
	u32 omap_rev = omap_revision();

	/* EMIF1 & EMIF2 have identical configuration */
	if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
		&& (cs == CS1)) {
		/* Nothing connected on CS1 for 4430/4470 ES1.0 */
		return NULL;
	} else if (omap_rev < OMAP4470_ES1_0) {
		/* In all other 4430/4460 cases Elpida 2G device */
		*lpddr2_dev_details = elpida_2G_S4_details;
	} else {
		/* 4470: 4G device */
		*lpddr2_dev_details = elpida_4G_S4_details;
	}
	return lpddr2_dev_details;
}

struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
			struct lpddr2_device_details *lpddr2_dev_details)
	__attribute__((weak, alias("emif_get_device_details_sdp")));

#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */

#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
	.max_freq	= 400000000,
	.RL		= 6,
	.tRPab		= 21,
	.tRCD		= 18,
	.tWR		= 15,
	.tRASmin	= 42,
	.tRRD		= 10,
	.tWTRx2		= 15,
	.tXSR		= 140,
	.tXPx2		= 15,
	.tRFCab		= 130,
	.tRTPx2		= 15,
	.tCKE		= 3,
	.tCKESR		= 15,
	.tZQCS		= 90,
	.tZQCL		= 360,
	.tZQINIT	= 1000,
	.tDQSCKMAXx2	= 11,
	.tRASmax	= 70,
	.tFAW		= 50
};

static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
	.max_freq	= 333000000,
	.RL		= 5,
	.tRPab		= 21,
	.tRCD		= 18,
	.tWR		= 15,
	.tRASmin	= 42,
	.tRRD		= 10,
	.tWTRx2		= 15,
	.tXSR		= 140,
	.tXPx2		= 15,
	.tRFCab		= 130,
	.tRTPx2		= 15,
	.tCKE		= 3,
	.tCKESR		= 15,
	.tZQCS		= 90,
	.tZQCL		= 360,
	.tZQINIT	= 1000,
	.tDQSCKMAXx2	= 11,
	.tRASmax	= 70,
	.tFAW		= 50
};

static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
	.max_freq	= 200000000,
	.RL		= 3,
	.tRPab		= 21,
	.tRCD		= 18,
	.tWR		= 15,
	.tRASmin	= 42,
	.tRRD		= 10,
	.tWTRx2		= 20,
	.tXSR		= 140,
	.tXPx2		= 15,
	.tRFCab		= 130,
	.tRTPx2		= 15,
	.tCKE		= 3,
	.tCKESR		= 15,
	.tZQCS		= 90,
	.tZQCL		= 360,
	.tZQINIT	= 1000,
	.tDQSCKMAXx2	= 11,
	.tRASmax	= 70,
	.tFAW		= 50
};

static const struct lpddr2_min_tck min_tck_elpida = {
	.tRL		= 3,
	.tRP_AB		= 3,
	.tRCD		= 3,
	.tWR		= 3,
	.tRAS_MIN	= 3,
	.tRRD		= 2,
	.tWTR		= 2,
	.tXP		= 2,
	.tRTP		= 2,
	.tCKE		= 3,
	.tCKESR		= 3,
	.tFAW		= 8
};

static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
		&timings_elpida_200_mhz,
		&timings_elpida_333_mhz,
		&timings_elpida_400_mhz
};

const struct lpddr2_device_timings elpida_2G_S4_timings = {
	.ac_timings	= elpida_ac_timings,
	.min_tck	= &min_tck_elpida,
};

void emif_get_device_timings_sdp(u32 emif_nr,
		const struct lpddr2_device_timings **cs0_device_timings,
		const struct lpddr2_device_timings **cs1_device_timings)
{
	u32 omap_rev = omap_revision();

	/* Identical devices on EMIF1 & EMIF2 */
	*cs0_device_timings = &elpida_2G_S4_timings;

	if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
		*cs1_device_timings = NULL;
	else
		*cs1_device_timings = &elpida_2G_S4_timings;
}

void emif_get_device_timings(u32 emif_nr,
		const struct lpddr2_device_timings **cs0_device_timings,
		const struct lpddr2_device_timings **cs1_device_timings)
	__attribute__((weak, alias("emif_get_device_timings_sdp")));

#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */

const struct lpddr2_mr_regs mr_regs = {
	.mr1	= MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
	.mr2	= 0x4,
	.mr3	= -1,
	.mr10	= MR10_ZQ_ZQINIT,
	.mr16	= MR16_REF_FULL_ARRAY
};

void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
{
	*regs = &mr_regs;
}

__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
{
	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
2ae610f0 A	2	/*
	3	* Timing and Organization details of the Elpida parts used in OMAP4
	4	* SDPs and Panda
	5	*
	6	* (C) Copyright 2010
	7	* Texas Instruments, <www.ti.com>
	8	*
	9	* Aneesh V <aneesh@ti.com>
2ae610f0 A	10	*/
2ae610f0 A	11
bb772a59	12	#include <asm/emif.h>
2ae610f0 A	13	#include <asm/arch/sys_proto.h>
	14
	15	/*
	16	* This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
	17	* SDP and Panda. Since the parts used and geometry are identical for
	18	* SDP and Panda for a given OMAP4 revision, this information is kept
	19	* here instead of being in board directory. However the key functions
	20	* exported are weakly linked so that they can be over-ridden in the board
	21	* directory if there is a OMAP4 board in the future that uses a different
	22	* memory device or geometry.
	23	*
	24	* For any new board with different memory devices over-ride one or more
	25	* of the following functions as per the CONFIG flags you intend to enable:
	26	* - emif_get_reg_dump()
	27	* - emif_get_dmm_regs()
	28	* - emif_get_device_details()
	29	* - emif_get_device_timings()
	30	*/
	31
095aea29 A	32	#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
095aea29 A	33
675cc77a	34	const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
2ae610f0 A	35	.sdram_config_init = 0x80000eb9,
	36	.sdram_config = 0x80001ab9,
	37	.ref_ctrl = 0x0000030c,
	38	.sdram_tim1 = 0x08648311,
	39	.sdram_tim2 = 0x101b06ca,
	40	.sdram_tim3 = 0x0048a19f,
	41	.read_idle_ctrl = 0x000501ff,
	42	.zq_config = 0x500b3214,
	43	.temp_alert_config = 0xd8016893,
	44	.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
	45	.emif_ddr_phy_ctlr_1 = 0x049ff808
	46	};
	47
675cc77a	48	const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
2ae610f0 A	49	.sdram_config_init = 0x80000eb1,
	50	.sdram_config = 0x80001ab1,
	51	.ref_ctrl = 0x000005cd,
	52	.sdram_tim1 = 0x10cb0622,
	53	.sdram_tim2 = 0x20350d52,
	54	.sdram_tim3 = 0x00b1431f,
	55	.read_idle_ctrl = 0x000501ff,
	56	.zq_config = 0x500b3214,
	57	.temp_alert_config = 0x58016893,
	58	.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
	59	.emif_ddr_phy_ctlr_1 = 0x049ff418
	60	};
	61
81aee972 LP	62	const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
	63	.sdram_config_init = 0x80800eb2,
	64	.sdram_config = 0x80801ab2,
	65	.ref_ctrl = 0x00000618,
	66	.sdram_tim1 = 0x10eb0662,
	67	.sdram_tim2 = 0x20370dd2,
	68	.sdram_tim3 = 0x00b1c33f,
	69	.read_idle_ctrl = 0x000501ff,
	70	.zq_config = 0x500b3215,
	71	.temp_alert_config = 0x58016893,
	72	.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
	73	.emif_ddr_phy_ctlr_1 = 0x049ff418
	74	};
	75
2ae610f0 A	76	const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
	77	.sdram_config_init = 0x80000eb9,
	78	.sdram_config = 0x80001ab9,
	79	.ref_ctrl = 0x00000618,
	80	.sdram_tim1 = 0x10eb0662,
	81	.sdram_tim2 = 0x20370dd2,
	82	.sdram_tim3 = 0x00b1c33f,
	83	.read_idle_ctrl = 0x000501ff,
	84	.zq_config = 0xd00b3214,
	85	.temp_alert_config = 0xd8016893,
	86	.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
	87	.emif_ddr_phy_ctlr_1 = 0x049ff418
	88	};
f4010734	89
2ae610f0 A	90	const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
	91	.dmm_lisa_map_0 = 0xFF020100,
	92	.dmm_lisa_map_1 = 0,
	93	.dmm_lisa_map_2 = 0,
7831419d LV	94	.dmm_lisa_map_3 = 0x80540300,
7831419d LV	95	.is_ma_present = 0x0
2ae610f0 A	96	};
	97
	98	const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
	99	.dmm_lisa_map_0 = 0xFF020100,
	100	.dmm_lisa_map_1 = 0,
	101	.dmm_lisa_map_2 = 0,
7831419d LV	102	.dmm_lisa_map_3 = 0x80640300,
	103	.is_ma_present = 0x0
	104	};
	105
	106	const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
	107	.dmm_lisa_map_0 = 0xFF020100,
	108	.dmm_lisa_map_1 = 0,
	109	.dmm_lisa_map_2 = 0,
	110	.dmm_lisa_map_3 = 0x80640300,
	111	.is_ma_present = 0x1
2ae610f0 A	112	};
	113
	114	static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
	115	{
	116	u32 omap4_rev = omap_revision();
	117
	118	/* Same devices and geometry on both EMIFs */
	119	if (omap4_rev == OMAP4430_ES1_0)
	120	*regs = &emif_regs_elpida_380_mhz_1cs;
	121	else if (omap4_rev == OMAP4430_ES2_0)
	122	*regs = &emif_regs_elpida_200_mhz_2cs;
81aee972	123	else if (omap4_rev < OMAP4470_ES1_0)
2ae610f0	124	*regs = &emif_regs_elpida_400_mhz_2cs;
81aee972 LP	125	else
81aee972 LP	126	*regs = &emif_regs_elpida_400_mhz_1cs;
2ae610f0 A	127	}
	128	void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
	129	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
	130
	131	static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
	132	**dmm_lisa_regs)
	133	{
	134	u32 omap_rev = omap_revision();
	135
	136	if (omap_rev == OMAP4430_ES1_0)
	137	*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
7831419d	138	else if (omap_rev < OMAP4460_ES1_0)
2ae610f0	139	*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
7831419d LV	140	else
7831419d LV	141	*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
2ae610f0 A	142	}
	143
	144	void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
	145	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
095aea29 A	146
	147	#else
	148
7cb998ba	149	const struct lpddr2_device_details elpida_2G_S4_details = {
095aea29 A	150	.type = LPDDR2_TYPE_S4,
	151	.density = LPDDR2_DENSITY_2Gb,
	152	.io_width = LPDDR2_IO_WIDTH_32,
	153	.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
	154	};
	155
7cb998ba	156	const struct lpddr2_device_details elpida_4G_S4_details = {
81aee972 LP	157	.type = LPDDR2_TYPE_S4,
	158	.density = LPDDR2_DENSITY_4Gb,
	159	.io_width = LPDDR2_IO_WIDTH_32,
	160	.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
	161	};
	162
025bc425 A	163	struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
025bc425 A	164	struct lpddr2_device_details *lpddr2_dev_details)
095aea29 A	165	{
	166	u32 omap_rev = omap_revision();
	167
	168	/* EMIF1 & EMIF2 have identical configuration */
81aee972 LP	169	if (((omap_rev == OMAP4430_ES1_0) \|\| (omap_rev == OMAP4470_ES1_0))
	170	&& (cs == CS1)) {
	171	/* Nothing connected on CS1 for 4430/4470 ES1.0 */
025bc425	172	return NULL;
81aee972 LP	173	} else if (omap_rev < OMAP4470_ES1_0) {
81aee972 LP	174	/* In all other 4430/4460 cases Elpida 2G device */
025bc425	175	*lpddr2_dev_details = elpida_2G_S4_details;
81aee972 LP	176	} else {
	177	/* 4470: 4G device */
	178	*lpddr2_dev_details = elpida_4G_S4_details;
025bc425	179	}
81aee972	180	return lpddr2_dev_details;
095aea29 A	181	}
095aea29 A	182
025bc425 A	183	struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
025bc425 A	184	struct lpddr2_device_details *lpddr2_dev_details)
095aea29 A	185	__attribute__((weak, alias("emif_get_device_details_sdp")));
	186
	187	#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
	188
	189	#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
	190	static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
	191	.max_freq = 400000000,
	192	.RL = 6,
	193	.tRPab = 21,
	194	.tRCD = 18,
	195	.tWR = 15,
	196	.tRASmin = 42,
	197	.tRRD = 10,
	198	.tWTRx2 = 15,
	199	.tXSR = 140,
	200	.tXPx2 = 15,
	201	.tRFCab = 130,
	202	.tRTPx2 = 15,
	203	.tCKE = 3,
	204	.tCKESR = 15,
	205	.tZQCS = 90,
	206	.tZQCL = 360,
	207	.tZQINIT = 1000,
	208	.tDQSCKMAXx2 = 11,
	209	.tRASmax = 70,
	210	.tFAW = 50
	211	};
	212
	213	static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
	214	.max_freq = 333000000,
	215	.RL = 5,
	216	.tRPab = 21,
	217	.tRCD = 18,
	218	.tWR = 15,
	219	.tRASmin = 42,
	220	.tRRD = 10,
	221	.tWTRx2 = 15,
	222	.tXSR = 140,
	223	.tXPx2 = 15,
	224	.tRFCab = 130,
	225	.tRTPx2 = 15,
	226	.tCKE = 3,
	227	.tCKESR = 15,
	228	.tZQCS = 90,
	229	.tZQCL = 360,
	230	.tZQINIT = 1000,
	231	.tDQSCKMAXx2 = 11,
	232	.tRASmax = 70,
	233	.tFAW = 50
	234	};
	235
	236	static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
	237	.max_freq = 200000000,
	238	.RL = 3,
	239	.tRPab = 21,
	240	.tRCD = 18,
	241	.tWR = 15,
	242	.tRASmin = 42,
	243	.tRRD = 10,
	244	.tWTRx2 = 20,
	245	.tXSR = 140,
	246	.tXPx2 = 15,
	247	.tRFCab = 130,
	248	.tRTPx2 = 15,
249	.tCKE = 3,
250	.tCKESR = 15,
251	.tZQCS = 90,
252	.tZQCL = 360,
253	.tZQINIT = 1000,
254	.tDQSCKMAXx2 = 11,
255	.tRASmax = 70,
256	.tFAW = 50
257	};
258
259	static const struct lpddr2_min_tck min_tck_elpida = {
260	.tRL = 3,
261	.tRP_AB = 3,
262	.tRCD = 3,
263	.tWR = 3,
264	.tRAS_MIN = 3,
265	.tRRD = 2,
266	.tWTR = 2,
267	.tXP = 2,
268	.tRTP = 2,
269	.tCKE = 3,
270	.tCKESR = 3,
271	.tFAW = 8
272	};
273
274	static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
275	&timings_elpida_200_mhz,
276	&timings_elpida_333_mhz,
277	&timings_elpida_400_mhz
278	};
279
96703acd	280	const struct lpddr2_device_timings elpida_2G_S4_timings = {
095aea29 A	281	.ac_timings = elpida_ac_timings,
	282	.min_tck = &min_tck_elpida,
	283	};
	284
	285	void emif_get_device_timings_sdp(u32 emif_nr,
	286	const struct lpddr2_device_timings **cs0_device_timings,
	287	const struct lpddr2_device_timings **cs1_device_timings)
	288	{
	289	u32 omap_rev = omap_revision();
	290
	291	/* Identical devices on EMIF1 & EMIF2 */
	292	*cs0_device_timings = &elpida_2G_S4_timings;
	293
81aee972	294	if ((omap_rev == OMAP4430_ES1_0) \|\| (omap_rev == OMAP4470_ES1_0))
095aea29 A	295	*cs1_device_timings = NULL;
	296	else
	297	*cs1_device_timings = &elpida_2G_S4_timings;
	298	}
	299
	300	void emif_get_device_timings(u32 emif_nr,
	301	const struct lpddr2_device_timings **cs0_device_timings,
	302	const struct lpddr2_device_timings **cs1_device_timings)
	303	__attribute__((weak, alias("emif_get_device_timings_sdp")));
	304
	305	#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
e05a4f1f LV	306
	307	const struct lpddr2_mr_regs mr_regs = {
	308	.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
	309	.mr2 = 0x4,
	310	.mr3 = -1,
	311	.mr10 = MR10_ZQ_ZQINIT,
	312	.mr16 = MR16_REF_FULL_ARRAY
	313	};
	314
	315	void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
	316	{
	317	*regs = &mr_regs;
	318	}
54d022e7 S	319
	320	__weak const struct read_write_regs get_bug_regs(u32 iterations)
	321	{
	322	return 0;
	323	}