[people/ms/u-boot.git] / arch / arm / mach-omap2 / omap5 / hwinit.c

/*
 *
 * Functions for omap5 based boards.
 *
 * (C) Copyright 2011
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *	Aneesh V	<aneesh@ti.com>
 *	Steve Sakoman	<steve@sakoman.com>
 *	Sricharan	<r.sricharan@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <palmas.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <linux/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include <asm/omap_common.h>

DECLARE_GLOBAL_DATA_PTR;

u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;

#ifndef CONFIG_DM_GPIO
static struct gpio_bank gpio_bank_54xx[8] = {
	{ (void *)OMAP54XX_GPIO1_BASE },
	{ (void *)OMAP54XX_GPIO2_BASE },
	{ (void *)OMAP54XX_GPIO3_BASE },
	{ (void *)OMAP54XX_GPIO4_BASE },
	{ (void *)OMAP54XX_GPIO5_BASE },
	{ (void *)OMAP54XX_GPIO6_BASE },
	{ (void *)OMAP54XX_GPIO7_BASE },
	{ (void *)OMAP54XX_GPIO8_BASE },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
#endif

void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
{
	int i;
	struct pad_conf_entry *pad = (struct pad_conf_entry *)array;

	for (i = 0; i < size; i++, pad++)
		writel(pad->val, base + pad->offset);
}

#ifdef CONFIG_SPL_BUILD
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
	const struct ctrl_ioregs *ioregs;

	get_ioregs(&ioregs);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
}

/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
	u32 io_settings = 0;
	const struct ctrl_ioregs *ioregs;

	get_ioregs(&ioregs);
	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);

	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);

	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);

	if (!is_dra7xx()) {
		writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
		writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	}

	/* omap5432 does not use lpddr2 */
	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);

	writel(ioregs->ctrl_emif_sdram_config_ext,
	       (*ctrl)->control_emif1_sdram_config_ext);
	if (!is_dra72x())
		writel(ioregs->ctrl_emif_sdram_config_ext,
		       (*ctrl)->control_emif2_sdram_config_ext);

	if (is_omap54xx()) {
		/* Disable DLL select */
		io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
							& 0xFFEFFFFF);
		writel(io_settings,
			(*ctrl)->control_port_emif1_sdram_config);

		io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
							& 0xFFEFFFFF);
		writel(io_settings,
			(*ctrl)->control_port_emif2_sdram_config);
	} else {
		writel(ioregs->ctrl_ddr_ctrl_ext_0,
				(*ctrl)->control_ddr_control_ext_0);
	}
}

/*
 * Some tuning of IOs for optimal power and performance
 */
void do_io_settings(void)
{
	u32 io_settings = 0, mask = 0;
	struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;

	/* Impedance settings EMMC, C2C 1,2, hsi2 */
	mask = (ds_mask << 2) | (ds_mask << 8) |
		(ds_mask << 16) | (ds_mask << 18);
	io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
				(~mask);
	io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
			(ds_45_ohm << 18) | (ds_60_ohm << 2);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_0);

	/* Impedance settings Mcspi2 */
	mask = (ds_mask << 30);
	io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
			(~mask);
	io_settings |= (ds_60_ohm << 30);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_1);

	/* Impedance settings C2C 3,4 */
	mask = (ds_mask << 14) | (ds_mask << 16);
	io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
			(~mask);
	io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
	writel(io_settings, (*ctrl)->control_smart1io_padconf_2);

	/* Slew rate settings EMMC, C2C 1,2 */
	mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
	io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
			(~mask);
	io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_0);

	/* Slew rate settings hsi2, Mcspi2 */
	mask = (sc_mask << 24) | (sc_mask << 28);
	io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
			(~mask);
	io_settings |= (sc_fast << 28) | (sc_fast << 24);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_1);

	/* Slew rate settings C2C 3,4 */
	mask = (sc_mask << 16) | (sc_mask << 18);
	io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
			(~mask);
	io_settings |= (sc_na << 16) | (sc_na << 18);
	writel(io_settings, (*ctrl)->control_smart2io_padconf_2);

	/* impedance and slew rate settings for usb */
	mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
		(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
	io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
			(~mask);
	io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
		       (ds_60_ohm << 23) | (sc_fast << 20) |
		       (sc_fast << 17) | (sc_fast << 14);
	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);

	if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
		io_settings_lpddr2();
	else
		io_settings_ddr3();
}

static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
	{0x45, 0x1},	/* 12 MHz   */
	{-1, -1},	/* 13 MHz   */
	{0x63, 0x2},	/* 16.8 MHz */
	{0x57, 0x2},	/* 19.2 MHz */
	{0x20, 0x1},	/* 26 MHz   */
	{-1, -1},	/* 27 MHz   */
	{0x41, 0x3}	/* 38.4 MHz */
};

void srcomp_enable(void)
{
	u32 srcomp_value, mul_factor, div_factor, clk_val, i;
	u32 sysclk_ind	= get_sys_clk_index();
	u32 omap_rev	= omap_revision();

	if (!is_omap54xx())
		return;

	mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
	div_factor = srcomp_parameters[sysclk_ind].divide_factor;

	for (i = 0; i < 4; i++) {
		srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
		srcomp_value &=
			~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
			(div_factor << DIVIDE_FACTOR_XS_SHIFT);
		writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
	}

	if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);

		for (i = 0; i < 4; i++) {
			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~PWRDWN_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);

			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
				& SRCODE_READ_XS_MASK) >>
				SRCODE_READ_XS_SHIFT) == 0)
				;

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~OVERRIDE_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}
	} else {
		srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
				  DIVIDE_FACTOR_XS_MASK);
		srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
				(div_factor << DIVIDE_FACTOR_XS_SHIFT);
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		for (i = 0; i < 4; i++) {
			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~OVERRIDE_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~OVERRIDE_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);

		clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);

		clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
		clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
		writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);

		for (i = 0; i < 4; i++) {
			while (((readl((*ctrl)->control_srcomp_north_side + i*4)
				& SRCODE_READ_XS_MASK) >>
				SRCODE_READ_XS_SHIFT) == 0)
				;

			srcomp_value =
				readl((*ctrl)->control_srcomp_north_side + i*4);
			srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
			writel(srcomp_value,
			       (*ctrl)->control_srcomp_north_side + i*4);
		}

		while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
			SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
			;

		srcomp_value =
			readl((*ctrl)->control_srcomp_east_side_wkup);
		srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
		writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	}
}
#endif

void config_data_eye_leveling_samples(u32 emif_base)
{
	const struct ctrl_ioregs *ioregs;

	get_ioregs(&ioregs);

	/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
	if (emif_base == EMIF1_BASE)
		writel(ioregs->ctrl_emif_sdram_config_ext_final,
		       (*ctrl)->control_emif1_sdram_config_ext);
	else if (emif_base == EMIF2_BASE)
		writel(ioregs->ctrl_emif_sdram_config_ext_final,
		       (*ctrl)->control_emif2_sdram_config_ext);
}

void init_cpu_configuration(void)
{
	u32 l2actlr;

	asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
	/*
	 * L2ACTLR: Ensure to enable the following:
	 * 3: Disable clean/evict push to external
	 * 4: Disable WriteUnique and WriteLineUnique transactions from master
	 * 8: Disable DVM/CMO message broadcast
	 */
	l2actlr |= 0x118;
	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
}

void init_omap_revision(void)
{
	/*
	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
	 * Also, ES1 and ES2 have different ARM revisions
	 * So use ARM revision for identification
	 */
	unsigned int rev = cortex_rev();

	switch (readl(CONTROL_ID_CODE)) {
	case OMAP5430_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = OMAP5430_ES1_0;
		if (rev == MIDR_CORTEX_A15_R2P2)
			*omap_si_rev = OMAP5430_ES2_0;
		break;
	case OMAP5432_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = OMAP5432_ES1_0;
		if (rev == MIDR_CORTEX_A15_R2P2)
			*omap_si_rev = OMAP5432_ES2_0;
		break;
	case OMAP5430_CONTROL_ID_CODE_ES2_0:
		*omap_si_rev = OMAP5430_ES2_0;
		break;
	case OMAP5432_CONTROL_ID_CODE_ES2_0:
		*omap_si_rev = OMAP5432_ES2_0;
		break;
	case DRA762_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = DRA762_ES1_0;
		break;
	case DRA752_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = DRA752_ES1_0;
		break;
	case DRA752_CONTROL_ID_CODE_ES1_1:
		*omap_si_rev = DRA752_ES1_1;
		break;
	case DRA752_CONTROL_ID_CODE_ES2_0:
		*omap_si_rev = DRA752_ES2_0;
		break;
	case DRA722_CONTROL_ID_CODE_ES1_0:
		*omap_si_rev = DRA722_ES1_0;
		break;
	case DRA722_CONTROL_ID_CODE_ES2_0:
		*omap_si_rev = DRA722_ES2_0;
		break;
	default:
		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
	}
	init_cpu_configuration();
}

void omap_die_id(unsigned int *die_id)
{
	die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
	die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
	die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
	die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
}

void reset_cpu(ulong ignored)
{
	u32 omap_rev = omap_revision();

	/*
	 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
	 * So use cold reset in case instead.
	 */
	if (omap_rev == OMAP5430_ES1_0)
		writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
	else
		writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
}

u32 warm_reset(void)
{
	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}

void setup_warmreset_time(void)
{
	u32 rst_time, rst_val;

	/*
	 * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
	 * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
	 * into microsec and passing the value.
	 */
	rst_time = usec_to_32k(CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC)
		<< RSTTIME1_SHIFT;

	if (rst_time > RSTTIME1_MASK)
		rst_time = RSTTIME1_MASK;

	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
	rst_val |= rst_time;
	writel(rst_val, (*prcm)->prm_rsttime);
}

void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
				 u32 cpu_rev_comb, u32 cpu_variant,
				 u32 cpu_rev)
{
	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
}

void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
			  u32 cpu_variant, u32 cpu_rev)
{

#ifdef CONFIG_ARM_ERRATA_801819
	/*
	 * DRA72x processors are uniprocessors and DONOT have
	 * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
	 * Extensions) Hence the erratum workaround is not applicable for
	 * DRA72x processors.
	 */
	if (is_dra72x())
		acr &= ~((0x3 << 23) | (0x3 << 25));
#endif
	omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
}

#if defined(CONFIG_PALMAS_POWER)
__weak void board_mmc_poweron_ldo(uint voltage)
{
	palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
}

void vmmc_pbias_config(uint voltage)
{
	u32 value = 0;

	value = readl((*ctrl)->control_pbias);
	value &= ~SDCARD_PWRDNZ;
	writel(value, (*ctrl)->control_pbias);
	udelay(10); /* wait 10 us */
	value &= ~SDCARD_BIAS_PWRDNZ;
	writel(value, (*ctrl)->control_pbias);

	board_mmc_poweron_ldo(voltage);

	value = readl((*ctrl)->control_pbias);
	value |= SDCARD_BIAS_PWRDNZ;
	writel(value, (*ctrl)->control_pbias);
	udelay(150); /* wait 150 us */
	value |= SDCARD_PWRDNZ;
	writel(value, (*ctrl)->control_pbias);
	udelay(150); /* wait 150 us */
}
#endif
Commit	Line	Data
508a58fa S	1	/*
	2	*
	3	* Functions for omap5 based boards.
	4	*
	5	* (C) Copyright 2011
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Aneesh V <aneesh@ti.com>
	10	* Steve Sakoman <steve@sakoman.com>
	11	* Sricharan <r.sricharan@ti.com>
	12	*
1a459660	13	* SPDX-License-Identifier: GPL-2.0+
508a58fa S	14	*/
508a58fa S	15	#include <common.h>
b4b06006	16	#include <palmas.h>
508a58fa S	17	#include <asm/armv7.h>
	18	#include <asm/arch/cpu.h>
	19	#include <asm/arch/sys_proto.h>
af1d002f	20	#include <asm/arch/clock.h>
1ace4022	21	#include <linux/sizes.h>
508a58fa S	22	#include <asm/utils.h>
508a58fa S	23	#include <asm/arch/gpio.h>
784ab7c5	24	#include <asm/emif.h>
f92f2277	25	#include <asm/omap_common.h>
508a58fa S	26
	27	DECLARE_GLOBAL_DATA_PTR;
	28
f92f2277	29	u32 const omap_si_rev = (u32 )OMAP_SRAM_SCRATCH_OMAP_REV;
508a58fa	30
0a9e3405	31	#ifndef CONFIG_DM_GPIO
87bd05d7	32	static struct gpio_bank gpio_bank_54xx[8] = {
0a9e3405 TR	33	{ (void *)OMAP54XX_GPIO1_BASE },
	34	{ (void *)OMAP54XX_GPIO2_BASE },
	35	{ (void *)OMAP54XX_GPIO3_BASE },
	36	{ (void *)OMAP54XX_GPIO4_BASE },
	37	{ (void *)OMAP54XX_GPIO5_BASE },
	38	{ (void *)OMAP54XX_GPIO6_BASE },
	39	{ (void *)OMAP54XX_GPIO7_BASE },
	40	{ (void *)OMAP54XX_GPIO8_BASE },
508a58fa S	41	};
	42
	43	const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
0a9e3405	44	#endif
508a58fa	45
1f68451c LV	46	void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
	47	{
	48	int i;
	49	struct pad_conf_entry pad = (struct pad_conf_entry )array;
	50
	51	for (i = 0; i < size; i++, pad++)
	52	writel(pad->val, base + pad->offset);
	53	}
	54
508a58fa	55	#ifdef CONFIG_SPL_BUILD
eb4e18e8 LV	56	/* LPDDR2 specific IO settings */
	57	static void io_settings_lpddr2(void)
	58	{
ef1697e9 LV	59	const struct ctrl_ioregs *ioregs;
	60
	61	get_ioregs(&ioregs);
	62	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	63	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
	64	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	65	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
	66	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
	67	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	68	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
	69	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
	70	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
eb4e18e8 LV	71	}
	72
	73	/* DDR3 specific IO settings */
	74	static void io_settings_ddr3(void)
	75	{
	76	u32 io_settings = 0;
ef1697e9	77	const struct ctrl_ioregs *ioregs;
eb4e18e8	78
ef1697e9 LV	79	get_ioregs(&ioregs);
	80	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
	81	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
	82	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
eb4e18e8	83
ef1697e9 LV	84	writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
	85	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
	86	writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
eb4e18e8	87
ef1697e9 LV	88	writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
ef1697e9 LV	89	writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
a5c5c5b5 LV	90
	91	if (!is_dra7xx()) {
	92	writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
	93	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
	94	}
eb4e18e8 LV	95
eb4e18e8 LV	96	/* omap5432 does not use lpddr2 */
ef1697e9	97	writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
eb4e18e8	98
ef1697e9 LV	99	writel(ioregs->ctrl_emif_sdram_config_ext,
ef1697e9 LV	100	(*ctrl)->control_emif1_sdram_config_ext);
a5c5c5b5 LV	101	if (!is_dra72x())
	102	writel(ioregs->ctrl_emif_sdram_config_ext,
	103	(*ctrl)->control_emif2_sdram_config_ext);
eb4e18e8	104
92b0482c S	105	if (is_omap54xx()) {
	106	/* Disable DLL select */
	107	io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
eb4e18e8	108	& 0xFFEFFFFF);
92b0482c S	109	writel(io_settings,
92b0482c S	110	(*ctrl)->control_port_emif1_sdram_config);
eb4e18e8	111
92b0482c	112	io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
eb4e18e8	113	& 0xFFEFFFFF);
92b0482c S	114	writel(io_settings,
	115	(*ctrl)->control_port_emif2_sdram_config);
	116	} else {
	117	writel(ioregs->ctrl_ddr_ctrl_ext_0,
	118	(*ctrl)->control_ddr_control_ext_0);
	119	}
eb4e18e8 LV	120	}
eb4e18e8 LV	121
508a58fa S	122	/*
	123	* Some tuning of IOs for optimal power and performance
	124	*/
	125	void do_io_settings(void)
	126	{
6ad8d67d	127	u32 io_settings = 0, mask = 0;
7c352cd3	128	struct emif_reg_struct emif = (struct emif_reg_struct )EMIF1_BASE;
6ad8d67d S	129
	130	/* Impedance settings EMMC, C2C 1,2, hsi2 */
	131	mask = (ds_mask << 2) \| (ds_mask << 8) \|
	132	(ds_mask << 16) \| (ds_mask << 18);
c43c8339	133	io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
6ad8d67d S	134	(~mask);
	135	io_settings \|= (ds_60_ohm << 8) \| (ds_45_ohm << 16) \|
	136	(ds_45_ohm << 18) \| (ds_60_ohm << 2);
c43c8339	137	writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
6ad8d67d S	138
	139	/* Impedance settings Mcspi2 */
	140	mask = (ds_mask << 30);
c43c8339	141	io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
6ad8d67d S	142	(~mask);
6ad8d67d S	143	io_settings \|= (ds_60_ohm << 30);
c43c8339	144	writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
6ad8d67d S	145
	146	/* Impedance settings C2C 3,4 */
	147	mask = (ds_mask << 14) \| (ds_mask << 16);
c43c8339	148	io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
6ad8d67d S	149	(~mask);
6ad8d67d S	150	io_settings \|= (ds_45_ohm << 14) \| (ds_45_ohm << 16);
c43c8339	151	writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
6ad8d67d S	152
	153	/* Slew rate settings EMMC, C2C 1,2 */
	154	mask = (sc_mask << 8) \| (sc_mask << 16) \| (sc_mask << 18);
c43c8339	155	io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
6ad8d67d S	156	(~mask);
6ad8d67d S	157	io_settings \|= (sc_fast << 8) \| (sc_na << 16) \| (sc_na << 18);
c43c8339	158	writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
6ad8d67d S	159
	160	/* Slew rate settings hsi2, Mcspi2 */
	161	mask = (sc_mask << 24) \| (sc_mask << 28);
c43c8339	162	io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
6ad8d67d S	163	(~mask);
6ad8d67d S	164	io_settings \|= (sc_fast << 28) \| (sc_fast << 24);
c43c8339	165	writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
6ad8d67d S	166
	167	/* Slew rate settings C2C 3,4 */
	168	mask = (sc_mask << 16) \| (sc_mask << 18);
c43c8339	169	io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
6ad8d67d S	170	(~mask);
6ad8d67d S	171	io_settings \|= (sc_na << 16) \| (sc_na << 18);
c43c8339	172	writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
6ad8d67d S	173
	174	/* impedance and slew rate settings for usb */
	175	mask = (usb_i_mask << 29) \| (usb_i_mask << 26) \| (usb_i_mask << 23) \|
	176	(usb_i_mask << 20) \| (usb_i_mask << 17) \| (usb_i_mask << 14);
c43c8339	177	io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
6ad8d67d S	178	(~mask);
	179	io_settings \|= (ds_60_ohm << 29) \| (ds_60_ohm << 26) \|
	180	(ds_60_ohm << 23) \| (sc_fast << 20) \|
	181	(sc_fast << 17) \| (sc_fast << 14);
c43c8339	182	writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
6ad8d67d	183
7c352cd3	184	if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
eb4e18e8 LV	185	io_settings_lpddr2();
	186	else
	187	io_settings_ddr3();
508a58fa	188	}
d4d986ee LV	189
	190	static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
	191	{0x45, 0x1}, /* 12 MHz */
	192	{-1, -1}, /* 13 MHz */
	193	{0x63, 0x2}, /* 16.8 MHz */
	194	{0x57, 0x2}, /* 19.2 MHz */
	195	{0x20, 0x1}, /* 26 MHz */
	196	{-1, -1}, /* 27 MHz */
	197	{0x41, 0x3} /* 38.4 MHz */
	198	};
	199
	200	void srcomp_enable(void)
	201	{
	202	u32 srcomp_value, mul_factor, div_factor, clk_val, i;
	203	u32 sysclk_ind = get_sys_clk_index();
	204	u32 omap_rev = omap_revision();
	205
e9d6cd04 LV	206	if (!is_omap54xx())
	207	return;
	208
d4d986ee LV	209	mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
	210	div_factor = srcomp_parameters[sysclk_ind].divide_factor;
	211
	212	for (i = 0; i < 4; i++) {
	213	srcomp_value = readl((ctrl)->control_srcomp_north_side + i4);
	214	srcomp_value &=
	215	~(MULTIPLY_FACTOR_XS_MASK \| DIVIDE_FACTOR_XS_MASK);
	216	srcomp_value \|= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) \|
	217	(div_factor << DIVIDE_FACTOR_XS_SHIFT);
	218	writel(srcomp_value, (ctrl)->control_srcomp_north_side + i4);
	219	}
	220
	221	if ((omap_rev == OMAP5430_ES1_0) \|\| (omap_rev == OMAP5432_ES1_0)) {
	222	clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
	223	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
	224	writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
	225
	226	for (i = 0; i < 4; i++) {
	227	srcomp_value =
	228	readl((ctrl)->control_srcomp_north_side + i4);
	229	srcomp_value &= ~PWRDWN_XS_MASK;
	230	writel(srcomp_value,
	231	(ctrl)->control_srcomp_north_side + i4);
	232
	233	while (((readl((ctrl)->control_srcomp_north_side + i4)
	234	& SRCODE_READ_XS_MASK) >>
	235	SRCODE_READ_XS_SHIFT) == 0)
	236	;
	237
	238	srcomp_value =
	239	readl((ctrl)->control_srcomp_north_side + i4);
	240	srcomp_value &= ~OVERRIDE_XS_MASK;
	241	writel(srcomp_value,
	242	(ctrl)->control_srcomp_north_side + i4);
	243	}
	244	} else {
	245	srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
	246	srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK \|
	247	DIVIDE_FACTOR_XS_MASK);
	248	srcomp_value \|= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) \|
	249	(div_factor << DIVIDE_FACTOR_XS_SHIFT);
	250	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	251
	252	for (i = 0; i < 4; i++) {
	253	srcomp_value =
	254	readl((ctrl)->control_srcomp_north_side + i4);
	255	srcomp_value \|= SRCODE_OVERRIDE_SEL_XS_MASK;
	256	writel(srcomp_value,
	257	(ctrl)->control_srcomp_north_side + i4);
	258
	259	srcomp_value =
	260	readl((ctrl)->control_srcomp_north_side + i4);
	261	srcomp_value &= ~OVERRIDE_XS_MASK;
	262	writel(srcomp_value,
	263	(ctrl)->control_srcomp_north_side + i4);
	264	}
	265
	266	srcomp_value =
	267	readl((*ctrl)->control_srcomp_east_side_wkup);
	268	srcomp_value \|= SRCODE_OVERRIDE_SEL_XS_MASK;
	269	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
	270
	271	srcomp_value =
	272	readl((*ctrl)->control_srcomp_east_side_wkup);
273	srcomp_value &= ~OVERRIDE_XS_MASK;
274	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
275
276	clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
277	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
278	writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
279
280	clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
281	clk_val \|= OPTFCLKEN_SRCOMP_FCLK_MASK;
282	writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
283
284	for (i = 0; i < 4; i++) {
285	while (((readl((ctrl)->control_srcomp_north_side + i4)
286	& SRCODE_READ_XS_MASK) >>
287	SRCODE_READ_XS_SHIFT) == 0)
288	;
289
290	srcomp_value =
291	readl((ctrl)->control_srcomp_north_side + i4);
292	srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
293	writel(srcomp_value,
294	(ctrl)->control_srcomp_north_side + i4);
295	}
296
297	while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
298	SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
299	;
300
301	srcomp_value =
302	readl((*ctrl)->control_srcomp_east_side_wkup);
303	srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
304	writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
305	}
306	}
508a58fa S	307	#endif
508a58fa S	308
784ab7c5 LV	309	void config_data_eye_leveling_samples(u32 emif_base)
784ab7c5 LV	310	{
6c70935d S	311	const struct ctrl_ioregs *ioregs;
	312
	313	get_ioregs(&ioregs);
	314
784ab7c5 LV	315	/EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4/
784ab7c5 LV	316	if (emif_base == EMIF1_BASE)
6c70935d S	317	writel(ioregs->ctrl_emif_sdram_config_ext_final,
6c70935d S	318	(*ctrl)->control_emif1_sdram_config_ext);
784ab7c5	319	else if (emif_base == EMIF2_BASE)
6c70935d S	320	writel(ioregs->ctrl_emif_sdram_config_ext_final,
6c70935d S	321	(*ctrl)->control_emif2_sdram_config_ext);
784ab7c5 LV	322	}
784ab7c5 LV	323
fc7368ec NM	324	void init_cpu_configuration(void)
	325	{
	326	u32 l2actlr;
	327
	328	asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
	329	/*
	330	* L2ACTLR: Ensure to enable the following:
	331	* 3: Disable clean/evict push to external
	332	* 4: Disable WriteUnique and WriteLineUnique transactions from master
	333	* 8: Disable DVM/CMO message broadcast
	334	*/
	335	l2actlr \|= 0x118;
	336	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
	337	}
	338
508a58fa S	339	void init_omap_revision(void)
	340	{
	341	/*
	342	* For some of the ES2/ES1 boards ID_CODE is not reliable:
	343	* Also, ES1 and ES2 have different ARM revisions
	344	* So use ARM revision for identification
	345	*/
	346	unsigned int rev = cortex_rev();
	347
eed7c0f7 S	348	switch (readl(CONTROL_ID_CODE)) {
	349	case OMAP5430_CONTROL_ID_CODE_ES1_0:
	350	*omap_si_rev = OMAP5430_ES1_0;
	351	if (rev == MIDR_CORTEX_A15_R2P2)
	352	*omap_si_rev = OMAP5430_ES2_0;
	353	break;
	354	case OMAP5432_CONTROL_ID_CODE_ES1_0:
	355	*omap_si_rev = OMAP5432_ES1_0;
	356	if (rev == MIDR_CORTEX_A15_R2P2)
	357	*omap_si_rev = OMAP5432_ES2_0;
	358	break;
	359	case OMAP5430_CONTROL_ID_CODE_ES2_0:
	360	*omap_si_rev = OMAP5430_ES2_0;
	361	break;
	362	case OMAP5432_CONTROL_ID_CODE_ES2_0:
	363	*omap_si_rev = OMAP5432_ES2_0;
cdd50a8d	364	break;
0f9e6aee PB	365	case DRA762_CONTROL_ID_CODE_ES1_0:
	366	*omap_si_rev = DRA762_ES1_0;
	367	break;
de62688b LV	368	case DRA752_CONTROL_ID_CODE_ES1_0:
	369	*omap_si_rev = DRA752_ES1_0;
	370	break;
3ac8c0bf NM	371	case DRA752_CONTROL_ID_CODE_ES1_1:
	372	*omap_si_rev = DRA752_ES1_1;
	373	break;
c1ea3bec NM	374	case DRA752_CONTROL_ID_CODE_ES2_0:
	375	*omap_si_rev = DRA752_ES2_0;
	376	break;
ee77a238 LV	377	case DRA722_CONTROL_ID_CODE_ES1_0:
	378	*omap_si_rev = DRA722_ES1_0;
	379	break;
d851ad3a RB	380	case DRA722_CONTROL_ID_CODE_ES2_0:
	381	*omap_si_rev = DRA722_ES2_0;
	382	break;
508a58fa	383	default:
087189fb	384	*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
508a58fa	385	}
fc7368ec	386	init_cpu_configuration();
508a58fa	387	}
0696473b	388
9fd54016 PK	389	void omap_die_id(unsigned int *die_id)
	390	{
	391	die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
	392	die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
	393	die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
	394	die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
	395	}
	396
0696473b S	397	void reset_cpu(ulong ignored)
	398	{
	399	u32 omap_rev = omap_revision();
	400
	401	/*
	402	* WARM reset is not functional in case of OMAP5430 ES1.0 soc.
	403	* So use cold reset in case instead.
	404	*/
	405	if (omap_rev == OMAP5430_ES1_0)
d4e4129c	406	writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
0696473b	407	else
d4e4129c LV	408	writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
	409	}
	410
	411	u32 warm_reset(void)
	412	{
	413	return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
0696473b	414	}
0b1b60c7 LV	415
	416	void setup_warmreset_time(void)
	417	{
	418	u32 rst_time, rst_val;
	419
d87f8296 TR	420	/*
	421	* MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
	422	* 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
	423	* into microsec and passing the value.
	424	*/
	425	rst_time = usec_to_32k(CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC)
	426	<< RSTTIME1_SHIFT;
0b1b60c7 LV	427
	428	if (rst_time > RSTTIME1_MASK)
	429	rst_time = RSTTIME1_MASK;
	430
	431	rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
	432	rst_val \|= rst_time;
	433	writel(rst_val, (*prcm)->prm_rsttime);
	434	}
5f603761 PR	435
	436	void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
	437	u32 cpu_rev_comb, u32 cpu_variant,
	438	u32 cpu_rev)
	439	{
	440	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
	441	}
1bbb556a NM	442
	443	void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
	444	u32 cpu_variant, u32 cpu_rev)
	445	{
095a5ef8 NM	446
	447	#ifdef CONFIG_ARM_ERRATA_801819
	448	/*
	449	* DRA72x processors are uniprocessors and DONOT have
	450	* ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
	451	* Extensions) Hence the erratum workaround is not applicable for
	452	* DRA72x processors.
	453	*/
	454	if (is_dra72x())
	455	acr &= ~((0x3 << 23) \| (0x3 << 25));
	456	#endif
1bbb556a NM	457	omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
1bbb556a NM	458	}
b4b06006 LV	459
b4b06006 LV	460	#if defined(CONFIG_PALMAS_POWER)
91d3e906 LV	461	__weak void board_mmc_poweron_ldo(uint voltage)
91d3e906 LV	462	{
db4fce8f	463	palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
91d3e906 LV	464	}
91d3e906 LV	465
b4b06006 LV	466	void vmmc_pbias_config(uint voltage)
	467	{
	468	u32 value = 0;
b4b06006 LV	469
	470	value = readl((*ctrl)->control_pbias);
	471	value &= ~SDCARD_PWRDNZ;
	472	writel(value, (*ctrl)->control_pbias);
	473	udelay(10); /* wait 10 us */
	474	value &= ~SDCARD_BIAS_PWRDNZ;
	475	writel(value, (*ctrl)->control_pbias);
	476
91d3e906	477	board_mmc_poweron_ldo(voltage);
b4b06006 LV	478
	479	value = readl((*ctrl)->control_pbias);
	480	value \|= SDCARD_BIAS_PWRDNZ;
	481	writel(value, (*ctrl)->control_pbias);
	482	udelay(150); /* wait 150 us */
	483	value \|= SDCARD_PWRDNZ;
	484	writel(value, (*ctrl)->control_pbias);
	485	udelay(150); /* wait 150 us */
	486	}
	487	#endif