]>
Commit | Line | Data |
---|---|---|
63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, BenoƮt Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
edfaf05c | 75 | * | ({read,write}l_relaxed, clk*) | |
74ff3a68 PW |
76 | * +-------------------------------+ |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
f5b00f6f | 133 | #include <linux/clk.h> |
f5dd3bb5 | 134 | #include <linux/clk-provider.h> |
63c85238 PW |
135 | #include <linux/delay.h> |
136 | #include <linux/err.h> | |
137 | #include <linux/list.h> | |
138 | #include <linux/mutex.h> | |
dc6d1cda | 139 | #include <linux/spinlock.h> |
abc2d545 | 140 | #include <linux/slab.h> |
f7b861b7 | 141 | #include <linux/cpu.h> |
079abade SS |
142 | #include <linux/of.h> |
143 | #include <linux/of_address.h> | |
57c8a661 | 144 | #include <linux/memblock.h> |
63c85238 | 145 | |
49a0a3d8 TL |
146 | #include <linux/platform_data/ti-sysc.h> |
147 | ||
8c879705 TL |
148 | #include <dt-bindings/bus/ti-sysc.h> |
149 | ||
fa200222 PW |
150 | #include <asm/system_misc.h> |
151 | ||
a135eaae | 152 | #include "clock.h" |
2a296c8f | 153 | #include "omap_hwmod.h" |
63c85238 | 154 | |
dbc04161 TL |
155 | #include "soc.h" |
156 | #include "common.h" | |
157 | #include "clockdomain.h" | |
158 | #include "powerdomain.h" | |
ff4ae5d9 PW |
159 | #include "cm2xxx.h" |
160 | #include "cm3xxx.h" | |
1688bf19 | 161 | #include "cm33xx.h" |
b13159af | 162 | #include "prm.h" |
139563ad | 163 | #include "prm3xxx.h" |
d198b514 | 164 | #include "prm44xx.h" |
1688bf19 | 165 | #include "prm33xx.h" |
eaac329d | 166 | #include "prminst44xx.h" |
5165882a | 167 | #include "pm.h" |
63c85238 | 168 | |
63c85238 | 169 | /* Name of the OMAP hwmod for the MPU */ |
5c2c0296 | 170 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 | 171 | |
2221b5cd PW |
172 | /* |
173 | * Number of struct omap_hwmod_link records per struct | |
174 | * omap_hwmod_ocp_if record (master->slave and slave->master) | |
175 | */ | |
176 | #define LINKS_PER_OCP_IF 2 | |
177 | ||
4ebf5b28 TK |
178 | /* |
179 | * Address offset (in bytes) between the reset control and the reset | |
180 | * status registers: 4 bytes on OMAP4 | |
181 | */ | |
182 | #define OMAP4_RST_CTRL_ST_OFFSET 4 | |
183 | ||
9fabc1a2 TK |
184 | /* |
185 | * Maximum length for module clock handle names | |
186 | */ | |
187 | #define MOD_CLK_MAX_NAME_LEN 32 | |
188 | ||
70f05be3 TK |
189 | /** |
190 | * struct clkctrl_provider - clkctrl provider mapping data | |
1b9c30fe TK |
191 | * @num_addrs: number of base address ranges for the provider |
192 | * @addr: base address(es) for the provider | |
193 | * @size: size(s) of the provider address space(s) | |
70f05be3 TK |
194 | * @node: device node associated with the provider |
195 | * @link: list link | |
196 | */ | |
197 | struct clkctrl_provider { | |
1b9c30fe TK |
198 | int num_addrs; |
199 | u32 *addr; | |
200 | u32 *size; | |
70f05be3 TK |
201 | struct device_node *node; |
202 | struct list_head link; | |
203 | }; | |
204 | ||
205 | static LIST_HEAD(clkctrl_providers); | |
206 | ||
9ebfd285 KH |
207 | /** |
208 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | |
209 | * @enable_module: function to enable a module (via MODULEMODE) | |
210 | * @disable_module: function to disable a module (via MODULEMODE) | |
211 | * | |
212 | * XXX Eventually this functionality will be hidden inside the PRM/CM | |
213 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | |
214 | * conditionals in this code. | |
215 | */ | |
216 | struct omap_hwmod_soc_ops { | |
217 | void (*enable_module)(struct omap_hwmod *oh); | |
218 | int (*disable_module)(struct omap_hwmod *oh); | |
8f6aa8ee | 219 | int (*wait_target_ready)(struct omap_hwmod *oh); |
b8249cf2 KH |
220 | int (*assert_hardreset)(struct omap_hwmod *oh, |
221 | struct omap_hwmod_rst_info *ohri); | |
222 | int (*deassert_hardreset)(struct omap_hwmod *oh, | |
223 | struct omap_hwmod_rst_info *ohri); | |
224 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | |
225 | struct omap_hwmod_rst_info *ohri); | |
0a179eaa | 226 | int (*init_clkdm)(struct omap_hwmod *oh); |
e6d3a8b0 RN |
227 | void (*update_context_lost)(struct omap_hwmod *oh); |
228 | int (*get_context_lost)(struct omap_hwmod *oh); | |
9fabc1a2 | 229 | int (*disable_direct_prcm)(struct omap_hwmod *oh); |
6e83ecaa | 230 | u32 (*xlate_clkctrl)(struct omap_hwmod *oh); |
9ebfd285 KH |
231 | }; |
232 | ||
233 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | |
234 | static struct omap_hwmod_soc_ops soc_ops; | |
235 | ||
63c85238 PW |
236 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
237 | static LIST_HEAD(omap_hwmod_list); | |
238 | ||
63c85238 PW |
239 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
240 | static struct omap_hwmod *mpu_oh; | |
241 | ||
9ebfd285 KH |
242 | /* inited: set to true once the hwmod code is initialized */ |
243 | static bool inited; | |
244 | ||
63c85238 PW |
245 | /* Private functions */ |
246 | ||
247 | /** | |
248 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
249 | * @oh: struct omap_hwmod * | |
250 | * | |
251 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
252 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
253 | * OCP_SYSCONFIG register or 0 upon success. | |
254 | */ | |
255 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
256 | { | |
43b40992 PW |
257 | if (!oh->class->sysc) { |
258 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
259 | return -EINVAL; |
260 | } | |
261 | ||
262 | /* XXX ensure module interface clock is up */ | |
263 | ||
cc7a1d2a | 264 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 265 | |
43b40992 | 266 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 267 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
268 | |
269 | return 0; | |
270 | } | |
271 | ||
272 | /** | |
273 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
274 | * @v: OCP_SYSCONFIG value to write | |
275 | * @oh: struct omap_hwmod * | |
276 | * | |
43b40992 PW |
277 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
278 | * one. No return value. | |
63c85238 PW |
279 | */ |
280 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
281 | { | |
43b40992 PW |
282 | if (!oh->class->sysc) { |
283 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
284 | return; |
285 | } | |
286 | ||
287 | /* XXX ensure module interface clock is up */ | |
288 | ||
233cbe5b RN |
289 | /* Module might have lost context, always update cache and register */ |
290 | oh->_sysc_cache = v; | |
aaf2c0fb LV |
291 | |
292 | /* | |
293 | * Some IP blocks (such as RTC) require unlocking of IP before | |
294 | * accessing its registers. If a function pointer is present | |
295 | * to unlock, then call it before accessing sysconfig and | |
296 | * call lock after writing sysconfig. | |
297 | */ | |
298 | if (oh->class->unlock) | |
299 | oh->class->unlock(oh); | |
300 | ||
233cbe5b | 301 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); |
aaf2c0fb LV |
302 | |
303 | if (oh->class->lock) | |
304 | oh->class->lock(oh); | |
63c85238 PW |
305 | } |
306 | ||
307 | /** | |
308 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
309 | * @oh: struct omap_hwmod * | |
310 | * @standbymode: MIDLEMODE field bits | |
311 | * @v: pointer to register contents to modify | |
312 | * | |
313 | * Update the master standby mode bits in @v to be @standbymode for | |
314 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
315 | * upon error or 0 upon success. | |
316 | */ | |
317 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
318 | u32 *v) | |
319 | { | |
358f0e63 TG |
320 | u32 mstandby_mask; |
321 | u8 mstandby_shift; | |
322 | ||
43b40992 PW |
323 | if (!oh->class->sysc || |
324 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
325 | return -EINVAL; |
326 | ||
43b40992 PW |
327 | if (!oh->class->sysc->sysc_fields) { |
328 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
329 | return -EINVAL; |
330 | } | |
331 | ||
43b40992 | 332 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
333 | mstandby_mask = (0x3 << mstandby_shift); |
334 | ||
335 | *v &= ~mstandby_mask; | |
336 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
337 | |
338 | return 0; | |
339 | } | |
340 | ||
341 | /** | |
342 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
343 | * @oh: struct omap_hwmod * | |
344 | * @idlemode: SIDLEMODE field bits | |
345 | * @v: pointer to register contents to modify | |
346 | * | |
347 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
348 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
349 | * or 0 upon success. | |
350 | */ | |
351 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
352 | { | |
358f0e63 TG |
353 | u32 sidle_mask; |
354 | u8 sidle_shift; | |
355 | ||
43b40992 PW |
356 | if (!oh->class->sysc || |
357 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
358 | return -EINVAL; |
359 | ||
43b40992 PW |
360 | if (!oh->class->sysc->sysc_fields) { |
361 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
362 | return -EINVAL; |
363 | } | |
364 | ||
43b40992 | 365 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
366 | sidle_mask = (0x3 << sidle_shift); |
367 | ||
368 | *v &= ~sidle_mask; | |
369 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
370 | |
371 | return 0; | |
372 | } | |
373 | ||
374 | /** | |
375 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
376 | * @oh: struct omap_hwmod * | |
377 | * @clockact: CLOCKACTIVITY field bits | |
378 | * @v: pointer to register contents to modify | |
379 | * | |
380 | * Update the clockactivity mode bits in @v to be @clockact for the | |
381 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
382 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
383 | * success. | |
384 | */ | |
385 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
386 | { | |
358f0e63 TG |
387 | u32 clkact_mask; |
388 | u8 clkact_shift; | |
389 | ||
43b40992 PW |
390 | if (!oh->class->sysc || |
391 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
392 | return -EINVAL; |
393 | ||
43b40992 PW |
394 | if (!oh->class->sysc->sysc_fields) { |
395 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
396 | return -EINVAL; |
397 | } | |
398 | ||
43b40992 | 399 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
400 | clkact_mask = (0x3 << clkact_shift); |
401 | ||
402 | *v &= ~clkact_mask; | |
403 | *v |= clockact << clkact_shift; | |
63c85238 PW |
404 | |
405 | return 0; | |
406 | } | |
407 | ||
408 | /** | |
313a76ee | 409 | * _set_softreset: set OCP_SYSCONFIG.SOFTRESET bit in @v |
63c85238 PW |
410 | * @oh: struct omap_hwmod * |
411 | * @v: pointer to register contents to modify | |
412 | * | |
413 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
414 | * error or 0 upon success. | |
415 | */ | |
416 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
417 | { | |
358f0e63 TG |
418 | u32 softrst_mask; |
419 | ||
43b40992 PW |
420 | if (!oh->class->sysc || |
421 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
422 | return -EINVAL; |
423 | ||
43b40992 PW |
424 | if (!oh->class->sysc->sysc_fields) { |
425 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
426 | return -EINVAL; |
427 | } | |
428 | ||
43b40992 | 429 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
430 | |
431 | *v |= softrst_mask; | |
63c85238 PW |
432 | |
433 | return 0; | |
434 | } | |
435 | ||
313a76ee RQ |
436 | /** |
437 | * _clear_softreset: clear OCP_SYSCONFIG.SOFTRESET bit in @v | |
438 | * @oh: struct omap_hwmod * | |
439 | * @v: pointer to register contents to modify | |
440 | * | |
441 | * Clear the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
442 | * error or 0 upon success. | |
443 | */ | |
444 | static int _clear_softreset(struct omap_hwmod *oh, u32 *v) | |
445 | { | |
446 | u32 softrst_mask; | |
447 | ||
448 | if (!oh->class->sysc || | |
449 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
450 | return -EINVAL; | |
451 | ||
452 | if (!oh->class->sysc->sysc_fields) { | |
453 | WARN(1, | |
454 | "omap_hwmod: %s: sysc_fields absent for sysconfig class\n", | |
455 | oh->name); | |
456 | return -EINVAL; | |
457 | } | |
458 | ||
459 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
460 | ||
461 | *v &= ~softrst_mask; | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
613ad0e9 TK |
466 | /** |
467 | * _wait_softreset_complete - wait for an OCP softreset to complete | |
468 | * @oh: struct omap_hwmod * to wait on | |
469 | * | |
470 | * Wait until the IP block represented by @oh reports that its OCP | |
471 | * softreset is complete. This can be triggered by software (see | |
472 | * _ocp_softreset()) or by hardware upon returning from off-mode (one | |
473 | * example is HSMMC). Waits for up to MAX_MODULE_SOFTRESET_WAIT | |
474 | * microseconds. Returns the number of microseconds waited. | |
475 | */ | |
476 | static int _wait_softreset_complete(struct omap_hwmod *oh) | |
477 | { | |
478 | struct omap_hwmod_class_sysconfig *sysc; | |
479 | u32 softrst_mask; | |
480 | int c = 0; | |
481 | ||
482 | sysc = oh->class->sysc; | |
483 | ||
103fd8e7 | 484 | if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS && sysc->syss_offs > 0) |
613ad0e9 TK |
485 | omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs) |
486 | & SYSS_RESETDONE_MASK), | |
487 | MAX_MODULE_SOFTRESET_WAIT, c); | |
488 | else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { | |
489 | softrst_mask = (0x1 << sysc->sysc_fields->srst_shift); | |
490 | omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs) | |
491 | & softrst_mask), | |
492 | MAX_MODULE_SOFTRESET_WAIT, c); | |
493 | } | |
494 | ||
495 | return c; | |
496 | } | |
497 | ||
6668546f KVA |
498 | /** |
499 | * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v | |
500 | * @oh: struct omap_hwmod * | |
501 | * | |
502 | * The DMADISABLE bit is a semi-automatic bit present in sysconfig register | |
503 | * of some modules. When the DMA must perform read/write accesses, the | |
504 | * DMADISABLE bit is cleared by the hardware. But when the DMA must stop | |
505 | * for power management, software must set the DMADISABLE bit back to 1. | |
506 | * | |
507 | * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon | |
508 | * error or 0 upon success. | |
509 | */ | |
510 | static int _set_dmadisable(struct omap_hwmod *oh) | |
511 | { | |
512 | u32 v; | |
513 | u32 dmadisable_mask; | |
514 | ||
515 | if (!oh->class->sysc || | |
516 | !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) | |
517 | return -EINVAL; | |
518 | ||
519 | if (!oh->class->sysc->sysc_fields) { | |
520 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
521 | return -EINVAL; | |
522 | } | |
523 | ||
524 | /* clocks must be on for this operation */ | |
525 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
526 | pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); | |
527 | return -EINVAL; | |
528 | } | |
529 | ||
530 | pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); | |
531 | ||
532 | v = oh->_sysc_cache; | |
533 | dmadisable_mask = | |
534 | (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); | |
535 | v |= dmadisable_mask; | |
536 | _write_sysconfig(v, oh); | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
726072e5 PW |
541 | /** |
542 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
543 | * @oh: struct omap_hwmod * | |
544 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
545 | * @v: pointer to register contents to modify | |
546 | * | |
547 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
548 | * hwmod. The autoidle bit controls whether the module can gate | |
549 | * internal clocks automatically when it isn't doing anything; the | |
550 | * exact function of this bit varies on a per-module basis. This | |
551 | * function does not write to the hardware. Returns -EINVAL upon | |
552 | * error or 0 upon success. | |
553 | */ | |
554 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
555 | u32 *v) | |
556 | { | |
358f0e63 TG |
557 | u32 autoidle_mask; |
558 | u8 autoidle_shift; | |
559 | ||
43b40992 PW |
560 | if (!oh->class->sysc || |
561 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
562 | return -EINVAL; |
563 | ||
43b40992 PW |
564 | if (!oh->class->sysc->sysc_fields) { |
565 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
566 | return -EINVAL; |
567 | } | |
568 | ||
43b40992 | 569 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 570 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
571 | |
572 | *v &= ~autoidle_mask; | |
573 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
574 | |
575 | return 0; | |
576 | } | |
577 | ||
63c85238 PW |
578 | /** |
579 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
580 | * @oh: struct omap_hwmod * | |
581 | * | |
582 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
583 | * upon error or 0 upon success. | |
584 | */ | |
5a7ddcbd | 585 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 586 | { |
43b40992 | 587 | if (!oh->class->sysc || |
86009eb3 | 588 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
589 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
590 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
591 | return -EINVAL; |
592 | ||
43b40992 PW |
593 | if (!oh->class->sysc->sysc_fields) { |
594 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
595 | return -EINVAL; |
596 | } | |
597 | ||
1fe74113 BC |
598 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
599 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 600 | |
86009eb3 BC |
601 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
602 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
603 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
604 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 605 | |
63c85238 PW |
606 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
607 | ||
63c85238 PW |
608 | return 0; |
609 | } | |
610 | ||
611 | /** | |
612 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
613 | * @oh: struct omap_hwmod * | |
614 | * | |
615 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
616 | * upon error or 0 upon success. | |
617 | */ | |
5a7ddcbd | 618 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 619 | { |
43b40992 | 620 | if (!oh->class->sysc || |
86009eb3 | 621 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
622 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
623 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
624 | return -EINVAL; |
625 | ||
43b40992 PW |
626 | if (!oh->class->sysc->sysc_fields) { |
627 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
628 | return -EINVAL; |
629 | } | |
630 | ||
1fe74113 BC |
631 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
632 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 633 | |
86009eb3 BC |
634 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
635 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 | 636 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
561038f0 | 637 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v); |
86009eb3 | 638 | |
63c85238 PW |
639 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
640 | ||
63c85238 PW |
641 | return 0; |
642 | } | |
643 | ||
f5dd3bb5 RN |
644 | static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) |
645 | { | |
c4a1ea2c RN |
646 | struct clk_hw_omap *clk; |
647 | ||
f5dd3bb5 RN |
648 | if (oh->clkdm) { |
649 | return oh->clkdm; | |
650 | } else if (oh->_clk) { | |
924f9498 TK |
651 | if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC) |
652 | return NULL; | |
f5dd3bb5 RN |
653 | clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); |
654 | return clk->clkdm; | |
f5dd3bb5 RN |
655 | } |
656 | return NULL; | |
657 | } | |
658 | ||
63c85238 PW |
659 | /** |
660 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
661 | * @oh: struct omap_hwmod * | |
662 | * | |
663 | * Prevent the hardware module @oh from entering idle while the | |
664 | * hardare module initiator @init_oh is active. Useful when a module | |
665 | * will be accessed by a particular initiator (e.g., if a module will | |
666 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
667 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
668 | * mode. If the clockdomain is marked as not needing autodeps, return |
669 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
670 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
671 | */ |
672 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
673 | { | |
f5dd3bb5 RN |
674 | struct clockdomain *clkdm, *init_clkdm; |
675 | ||
676 | clkdm = _get_clkdm(oh); | |
677 | init_clkdm = _get_clkdm(init_oh); | |
678 | ||
679 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
680 | return -EINVAL; |
681 | ||
f5dd3bb5 | 682 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
683 | return 0; |
684 | ||
f5dd3bb5 | 685 | return clkdm_add_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
686 | } |
687 | ||
688 | /** | |
689 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
690 | * @oh: struct omap_hwmod * | |
691 | * | |
692 | * Allow the hardware module @oh to enter idle while the hardare | |
693 | * module initiator @init_oh is active. Useful when a module will not | |
694 | * be accessed by a particular initiator (e.g., if a module will not | |
695 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
696 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
697 | * mode. If the clockdomain is marked as not needing autodeps, return |
698 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
699 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
700 | */ |
701 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
702 | { | |
f5dd3bb5 RN |
703 | struct clockdomain *clkdm, *init_clkdm; |
704 | ||
705 | clkdm = _get_clkdm(oh); | |
706 | init_clkdm = _get_clkdm(init_oh); | |
707 | ||
708 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
709 | return -EINVAL; |
710 | ||
f5dd3bb5 | 711 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
712 | return 0; |
713 | ||
f5dd3bb5 | 714 | return clkdm_del_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
715 | } |
716 | ||
70f05be3 TK |
717 | static const struct of_device_id ti_clkctrl_match_table[] __initconst = { |
718 | { .compatible = "ti,clkctrl" }, | |
719 | { } | |
720 | }; | |
721 | ||
0ca14cde | 722 | static int __init _setup_clkctrl_provider(struct device_node *np) |
70f05be3 TK |
723 | { |
724 | const __be32 *addrp; | |
725 | struct clkctrl_provider *provider; | |
6e83ecaa | 726 | u64 size; |
1b9c30fe | 727 | int i; |
70f05be3 | 728 | |
eb31d559 | 729 | provider = memblock_alloc(sizeof(*provider), 0); |
70f05be3 TK |
730 | if (!provider) |
731 | return -ENOMEM; | |
732 | ||
70f05be3 TK |
733 | provider->node = np; |
734 | ||
1b9c30fe TK |
735 | provider->num_addrs = |
736 | of_property_count_elems_of_size(np, "reg", sizeof(u32)) / 2; | |
737 | ||
738 | provider->addr = | |
eb31d559 | 739 | memblock_alloc(sizeof(void *) * provider->num_addrs, 0); |
1b9c30fe TK |
740 | if (!provider->addr) |
741 | return -ENOMEM; | |
742 | ||
743 | provider->size = | |
eb31d559 | 744 | memblock_alloc(sizeof(u32) * provider->num_addrs, 0); |
1b9c30fe TK |
745 | if (!provider->size) |
746 | return -ENOMEM; | |
747 | ||
748 | for (i = 0; i < provider->num_addrs; i++) { | |
749 | addrp = of_get_address(np, i, &size, NULL); | |
750 | provider->addr[i] = (u32)of_translate_address(np, addrp); | |
751 | provider->size[i] = size; | |
752 | pr_debug("%s: %pOF: %x...%x\n", __func__, np, provider->addr[i], | |
753 | provider->addr[i] + provider->size[i]); | |
754 | } | |
70f05be3 TK |
755 | |
756 | list_add(&provider->link, &clkctrl_providers); | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
0ca14cde | 761 | static int __init _init_clkctrl_providers(void) |
70f05be3 TK |
762 | { |
763 | struct device_node *np; | |
764 | int ret = 0; | |
765 | ||
766 | for_each_matching_node(np, ti_clkctrl_match_table) { | |
767 | ret = _setup_clkctrl_provider(np); | |
768 | if (ret) | |
769 | break; | |
770 | } | |
771 | ||
772 | return ret; | |
773 | } | |
774 | ||
6e83ecaa | 775 | static u32 _omap4_xlate_clkctrl(struct omap_hwmod *oh) |
70f05be3 | 776 | { |
6e83ecaa TK |
777 | if (!oh->prcm.omap4.modulemode) |
778 | return 0; | |
779 | ||
780 | return omap_cm_xlate_clkctrl(oh->clkdm->prcm_partition, | |
781 | oh->clkdm->cm_inst, | |
782 | oh->prcm.omap4.clkctrl_offs); | |
70f05be3 TK |
783 | } |
784 | ||
785 | static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh) | |
786 | { | |
787 | struct clkctrl_provider *provider; | |
788 | struct clk *clk; | |
6e83ecaa | 789 | u32 addr; |
70f05be3 TK |
790 | |
791 | if (!soc_ops.xlate_clkctrl) | |
792 | return NULL; | |
793 | ||
6e83ecaa TK |
794 | addr = soc_ops.xlate_clkctrl(oh); |
795 | if (!addr) | |
796 | return NULL; | |
797 | ||
798 | pr_debug("%s: %s: addr=%x\n", __func__, oh->name, addr); | |
799 | ||
70f05be3 | 800 | list_for_each_entry(provider, &clkctrl_providers, link) { |
1b9c30fe TK |
801 | int i; |
802 | ||
803 | for (i = 0; i < provider->num_addrs; i++) { | |
804 | if (provider->addr[i] <= addr && | |
805 | provider->addr[i] + provider->size[i] > addr) { | |
806 | struct of_phandle_args clkspec; | |
70f05be3 | 807 | |
1b9c30fe TK |
808 | clkspec.np = provider->node; |
809 | clkspec.args_count = 2; | |
810 | clkspec.args[0] = addr - provider->addr[0]; | |
811 | clkspec.args[1] = 0; | |
70f05be3 | 812 | |
1b9c30fe | 813 | clk = of_clk_get_from_provider(&clkspec); |
70f05be3 | 814 | |
1b9c30fe TK |
815 | pr_debug("%s: %s got %p (offset=%x, provider=%pOF)\n", |
816 | __func__, oh->name, clk, | |
817 | clkspec.args[0], provider->node); | |
6e83ecaa | 818 | |
1b9c30fe TK |
819 | return clk; |
820 | } | |
70f05be3 TK |
821 | } |
822 | } | |
823 | ||
824 | return NULL; | |
825 | } | |
826 | ||
63c85238 PW |
827 | /** |
828 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
829 | * @oh: struct omap_hwmod * | |
830 | * | |
831 | * Called from _init_clocks(). Populates the @oh _clk (main | |
9fabc1a2 TK |
832 | * functional clock pointer) if a clock matching the hwmod name is found, |
833 | * or a main_clk is present. Returns 0 on success or -EINVAL on error. | |
63c85238 PW |
834 | */ |
835 | static int _init_main_clk(struct omap_hwmod *oh) | |
836 | { | |
63c85238 | 837 | int ret = 0; |
70f05be3 | 838 | struct clk *clk = NULL; |
63c85238 | 839 | |
70f05be3 | 840 | clk = _lookup_clkctrl_clk(oh); |
9fabc1a2 | 841 | |
70f05be3 TK |
842 | if (!IS_ERR_OR_NULL(clk)) { |
843 | pr_debug("%s: mapped main_clk %s for %s\n", __func__, | |
844 | __clk_get_name(clk), oh->name); | |
845 | oh->main_clk = __clk_get_name(clk); | |
9fabc1a2 TK |
846 | oh->_clk = clk; |
847 | soc_ops.disable_direct_prcm(oh); | |
9fabc1a2 TK |
848 | } else { |
849 | if (!oh->main_clk) | |
850 | return 0; | |
851 | ||
852 | oh->_clk = clk_get(NULL, oh->main_clk); | |
853 | } | |
63c85238 | 854 | |
6ea74cb9 | 855 | if (IS_ERR(oh->_clk)) { |
3d0cb73e JP |
856 | pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
857 | oh->name, oh->main_clk); | |
63403384 | 858 | return -EINVAL; |
dc75925d | 859 | } |
4d7cb45e RN |
860 | /* |
861 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
862 | * to do something meaningful. Today its just a no-op. | |
863 | * If clk_prepare() is used at some point to do things like | |
864 | * voltage scaling etc, then this would have to be moved to | |
865 | * some point where subsystems like i2c and pmic become | |
866 | * available. | |
867 | */ | |
868 | clk_prepare(oh->_clk); | |
63c85238 | 869 | |
f5dd3bb5 | 870 | if (!_get_clkdm(oh)) |
3bb05dbf | 871 | pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", |
5dcc3b97 | 872 | oh->name, oh->main_clk); |
81d7c6ff | 873 | |
63c85238 PW |
874 | return ret; |
875 | } | |
876 | ||
877 | /** | |
887adeac | 878 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
879 | * @oh: struct omap_hwmod * |
880 | * | |
881 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
882 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
883 | */ | |
884 | static int _init_interface_clks(struct omap_hwmod *oh) | |
885 | { | |
5d95dde7 | 886 | struct omap_hwmod_ocp_if *os; |
63c85238 | 887 | struct clk *c; |
63c85238 PW |
888 | int ret = 0; |
889 | ||
b8e1bddc | 890 | list_for_each_entry(os, &oh->slave_ports, node) { |
50ebdac2 | 891 | if (!os->clk) |
63c85238 PW |
892 | continue; |
893 | ||
6ea74cb9 RN |
894 | c = clk_get(NULL, os->clk); |
895 | if (IS_ERR(c)) { | |
3d0cb73e JP |
896 | pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
897 | oh->name, os->clk); | |
63c85238 | 898 | ret = -EINVAL; |
0e7dc862 | 899 | continue; |
dc75925d | 900 | } |
63c85238 | 901 | os->_clk = c; |
4d7cb45e RN |
902 | /* |
903 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
904 | * to do something meaningful. Today its just a no-op. | |
905 | * If clk_prepare() is used at some point to do things like | |
906 | * voltage scaling etc, then this would have to be moved to | |
907 | * some point where subsystems like i2c and pmic become | |
908 | * available. | |
909 | */ | |
910 | clk_prepare(os->_clk); | |
63c85238 PW |
911 | } |
912 | ||
913 | return ret; | |
914 | } | |
915 | ||
916 | /** | |
917 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
918 | * @oh: struct omap_hwmod * | |
919 | * | |
920 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
921 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
922 | */ | |
923 | static int _init_opt_clks(struct omap_hwmod *oh) | |
924 | { | |
925 | struct omap_hwmod_opt_clk *oc; | |
926 | struct clk *c; | |
927 | int i; | |
928 | int ret = 0; | |
929 | ||
930 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
6ea74cb9 RN |
931 | c = clk_get(NULL, oc->clk); |
932 | if (IS_ERR(c)) { | |
3d0cb73e JP |
933 | pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
934 | oh->name, oc->clk); | |
63c85238 | 935 | ret = -EINVAL; |
0e7dc862 | 936 | continue; |
dc75925d | 937 | } |
63c85238 | 938 | oc->_clk = c; |
4d7cb45e RN |
939 | /* |
940 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
941 | * to do something meaningful. Today its just a no-op. | |
942 | * If clk_prepare() is used at some point to do things like | |
943 | * voltage scaling etc, then this would have to be moved to | |
944 | * some point where subsystems like i2c and pmic become | |
945 | * available. | |
946 | */ | |
947 | clk_prepare(oc->_clk); | |
63c85238 PW |
948 | } |
949 | ||
950 | return ret; | |
951 | } | |
952 | ||
c12ba8ce PU |
953 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
954 | { | |
955 | struct omap_hwmod_opt_clk *oc; | |
956 | int i; | |
957 | ||
958 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
959 | ||
960 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
961 | if (oc->_clk) { | |
962 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
963 | __clk_get_name(oc->_clk)); | |
964 | clk_enable(oc->_clk); | |
965 | } | |
966 | } | |
967 | ||
968 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
969 | { | |
970 | struct omap_hwmod_opt_clk *oc; | |
971 | int i; | |
972 | ||
973 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
974 | ||
975 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
976 | if (oc->_clk) { | |
977 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
978 | __clk_get_name(oc->_clk)); | |
979 | clk_disable(oc->_clk); | |
980 | } | |
981 | } | |
982 | ||
63c85238 PW |
983 | /** |
984 | * _enable_clocks - enable hwmod main clock and interface clocks | |
985 | * @oh: struct omap_hwmod * | |
986 | * | |
987 | * Enables all clocks necessary for register reads and writes to succeed | |
988 | * on the hwmod @oh. Returns 0. | |
989 | */ | |
990 | static int _enable_clocks(struct omap_hwmod *oh) | |
991 | { | |
5d95dde7 | 992 | struct omap_hwmod_ocp_if *os; |
63c85238 PW |
993 | |
994 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
995 | ||
392ea5dd TK |
996 | if (oh->flags & HWMOD_OPT_CLKS_NEEDED) |
997 | _enable_optional_clocks(oh); | |
998 | ||
4d3ae5a9 | 999 | if (oh->_clk) |
63c85238 PW |
1000 | clk_enable(oh->_clk); |
1001 | ||
b8e1bddc | 1002 | list_for_each_entry(os, &oh->slave_ports, node) { |
5d95dde7 PW |
1003 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
1004 | clk_enable(os->_clk); | |
63c85238 PW |
1005 | } |
1006 | ||
1007 | /* The opt clocks are controlled by the device driver. */ | |
1008 | ||
1009 | return 0; | |
1010 | } | |
1011 | ||
8823ddf2 TL |
1012 | /** |
1013 | * _omap4_clkctrl_managed_by_clkfwk - true if clkctrl managed by clock framework | |
1014 | * @oh: struct omap_hwmod * | |
1015 | */ | |
1016 | static bool _omap4_clkctrl_managed_by_clkfwk(struct omap_hwmod *oh) | |
1017 | { | |
1018 | if (oh->prcm.omap4.flags & HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK) | |
1019 | return true; | |
1020 | ||
1021 | return false; | |
1022 | } | |
1023 | ||
1024 | /** | |
1025 | * _omap4_has_clkctrl_clock - returns true if a module has clkctrl clock | |
1026 | * @oh: struct omap_hwmod * | |
1027 | */ | |
1028 | static bool _omap4_has_clkctrl_clock(struct omap_hwmod *oh) | |
1029 | { | |
1030 | if (oh->prcm.omap4.clkctrl_offs) | |
1031 | return true; | |
1032 | ||
1033 | if (!oh->prcm.omap4.clkctrl_offs && | |
1034 | oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET) | |
1035 | return true; | |
1036 | ||
1037 | return false; | |
1038 | } | |
1039 | ||
63c85238 PW |
1040 | /** |
1041 | * _disable_clocks - disable hwmod main clock and interface clocks | |
1042 | * @oh: struct omap_hwmod * | |
1043 | * | |
1044 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
1045 | */ | |
1046 | static int _disable_clocks(struct omap_hwmod *oh) | |
1047 | { | |
5d95dde7 | 1048 | struct omap_hwmod_ocp_if *os; |
63c85238 PW |
1049 | |
1050 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
1051 | ||
4d3ae5a9 | 1052 | if (oh->_clk) |
63c85238 PW |
1053 | clk_disable(oh->_clk); |
1054 | ||
b8e1bddc | 1055 | list_for_each_entry(os, &oh->slave_ports, node) { |
5d95dde7 PW |
1056 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
1057 | clk_disable(os->_clk); | |
63c85238 PW |
1058 | } |
1059 | ||
c12ba8ce PU |
1060 | if (oh->flags & HWMOD_OPT_CLKS_NEEDED) |
1061 | _disable_optional_clocks(oh); | |
1062 | ||
63c85238 PW |
1063 | /* The opt clocks are controlled by the device driver. */ |
1064 | ||
1065 | return 0; | |
1066 | } | |
1067 | ||
45c38252 | 1068 | /** |
3d9f0327 | 1069 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
45c38252 BC |
1070 | * @oh: struct omap_hwmod * |
1071 | * | |
1072 | * Enables the PRCM module mode related to the hwmod @oh. | |
1073 | * No return value. | |
1074 | */ | |
3d9f0327 | 1075 | static void _omap4_enable_module(struct omap_hwmod *oh) |
45c38252 | 1076 | { |
8823ddf2 TL |
1077 | if (!oh->clkdm || !oh->prcm.omap4.modulemode || |
1078 | _omap4_clkctrl_managed_by_clkfwk(oh)) | |
45c38252 BC |
1079 | return; |
1080 | ||
3d9f0327 KH |
1081 | pr_debug("omap_hwmod: %s: %s: %d\n", |
1082 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
45c38252 | 1083 | |
128603f0 TK |
1084 | omap_cm_module_enable(oh->prcm.omap4.modulemode, |
1085 | oh->clkdm->prcm_partition, | |
1086 | oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs); | |
1688bf19 VH |
1087 | } |
1088 | ||
45c38252 | 1089 | /** |
bfc141e3 BC |
1090 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
1091 | * @oh: struct omap_hwmod * | |
1092 | * | |
1093 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
1094 | * does not have an IDLEST bit or if the module successfully enters | |
1095 | * slave idle; otherwise, pass along the return value of the | |
1096 | * appropriate *_cm*_wait_module_idle() function. | |
1097 | */ | |
1098 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
1099 | { | |
2b026d13 | 1100 | if (!oh) |
bfc141e3 BC |
1101 | return -EINVAL; |
1102 | ||
2b026d13 | 1103 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) |
bfc141e3 BC |
1104 | return 0; |
1105 | ||
1106 | if (oh->flags & HWMOD_NO_IDLEST) | |
1107 | return 0; | |
1108 | ||
8823ddf2 TL |
1109 | if (_omap4_clkctrl_managed_by_clkfwk(oh)) |
1110 | return 0; | |
1111 | ||
1112 | if (!_omap4_has_clkctrl_clock(oh)) | |
428929c7 DG |
1113 | return 0; |
1114 | ||
a8ae5afa TK |
1115 | return omap_cm_wait_module_idle(oh->clkdm->prcm_partition, |
1116 | oh->clkdm->cm_inst, | |
1117 | oh->prcm.omap4.clkctrl_offs, 0); | |
1688bf19 VH |
1118 | } |
1119 | ||
63c85238 | 1120 | /** |
24dbc213 | 1121 | * _save_mpu_port_index - find and save the index to @oh's MPU port |
63c85238 PW |
1122 | * @oh: struct omap_hwmod * |
1123 | * | |
24dbc213 PW |
1124 | * Determines the array index of the OCP slave port that the MPU uses |
1125 | * to address the device, and saves it into the struct omap_hwmod. | |
1126 | * Intended to be called during hwmod registration only. No return | |
1127 | * value. | |
63c85238 | 1128 | */ |
24dbc213 | 1129 | static void __init _save_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1130 | { |
24dbc213 | 1131 | struct omap_hwmod_ocp_if *os = NULL; |
63c85238 | 1132 | |
5d95dde7 | 1133 | if (!oh) |
24dbc213 PW |
1134 | return; |
1135 | ||
1136 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
63c85238 | 1137 | |
b8e1bddc | 1138 | list_for_each_entry(os, &oh->slave_ports, node) { |
63c85238 | 1139 | if (os->user & OCP_USER_MPU) { |
2221b5cd | 1140 | oh->_mpu_port = os; |
24dbc213 | 1141 | oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; |
63c85238 PW |
1142 | break; |
1143 | } | |
1144 | } | |
1145 | ||
24dbc213 | 1146 | return; |
63c85238 PW |
1147 | } |
1148 | ||
2d6141ba PW |
1149 | /** |
1150 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1151 | * @oh: struct omap_hwmod * | |
1152 | * | |
1153 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1154 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1155 | * communicate with the IP block. This interface need not be directly | |
1156 | * connected to the MPU (and almost certainly is not), but is directly | |
1157 | * connected to the IP block represented by @oh. Returns a pointer | |
1158 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1159 | * error or if there does not appear to be a path from the MPU to this | |
1160 | * IP block. | |
1161 | */ | |
1162 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1163 | { | |
1164 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1165 | return NULL; | |
1166 | ||
11cd4b94 | 1167 | return oh->_mpu_port; |
2d6141ba PW |
1168 | }; |
1169 | ||
63c85238 | 1170 | /** |
74ff3a68 | 1171 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1172 | * @oh: struct omap_hwmod * |
1173 | * | |
006c7f18 PW |
1174 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
1175 | * by @oh is set to indicate to the PRCM that the IP block is active. | |
1176 | * Usually this means placing the module into smart-idle mode and | |
1177 | * smart-standby, but if there is a bug in the automatic idle handling | |
1178 | * for the IP block, it may need to be placed into the force-idle or | |
1179 | * no-idle variants of these modes. No return value. | |
63c85238 | 1180 | */ |
74ff3a68 | 1181 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1182 | { |
43b40992 | 1183 | u8 idlemode, sf; |
63c85238 | 1184 | u32 v; |
006c7f18 | 1185 | bool clkdm_act; |
f5dd3bb5 | 1186 | struct clockdomain *clkdm; |
63c85238 | 1187 | |
43b40992 | 1188 | if (!oh->class->sysc) |
63c85238 PW |
1189 | return; |
1190 | ||
613ad0e9 TK |
1191 | /* |
1192 | * Wait until reset has completed, this is needed as the IP | |
1193 | * block is reset automatically by hardware in some cases | |
1194 | * (off-mode for example), and the drivers require the | |
1195 | * IP to be ready when they access it | |
1196 | */ | |
1197 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1198 | _enable_optional_clocks(oh); | |
1199 | _wait_softreset_complete(oh); | |
1200 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1201 | _disable_optional_clocks(oh); | |
1202 | ||
63c85238 | 1203 | v = oh->_sysc_cache; |
43b40992 | 1204 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1205 | |
f5dd3bb5 | 1206 | clkdm = _get_clkdm(oh); |
43b40992 | 1207 | if (sf & SYSC_HAS_SIDLEMODE) { |
ca43ea34 RN |
1208 | if (oh->flags & HWMOD_SWSUP_SIDLE || |
1209 | oh->flags & HWMOD_SWSUP_SIDLE_ACT) { | |
35513171 RN |
1210 | idlemode = HWMOD_IDLEMODE_NO; |
1211 | } else { | |
1212 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1213 | _enable_wakeup(oh, &v); | |
1214 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1215 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1216 | else | |
1217 | idlemode = HWMOD_IDLEMODE_SMART; | |
1218 | } | |
1219 | ||
1220 | /* | |
1221 | * This is special handling for some IPs like | |
1222 | * 32k sync timer. Force them to idle! | |
1223 | */ | |
f5dd3bb5 | 1224 | clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); |
006c7f18 PW |
1225 | if (clkdm_act && !(oh->class->sysc->idlemodes & |
1226 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1227 | idlemode = HWMOD_IDLEMODE_FORCE; | |
35513171 | 1228 | |
63c85238 PW |
1229 | _set_slave_idlemode(oh, idlemode, &v); |
1230 | } | |
1231 | ||
43b40992 | 1232 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1233 | if (oh->flags & HWMOD_FORCE_MSTANDBY) { |
1234 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1235 | } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) { | |
724019b0 BC |
1236 | idlemode = HWMOD_IDLEMODE_NO; |
1237 | } else { | |
1238 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1239 | _enable_wakeup(oh, &v); | |
1240 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1241 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1242 | else | |
1243 | idlemode = HWMOD_IDLEMODE_SMART; | |
1244 | } | |
63c85238 PW |
1245 | _set_master_standbymode(oh, idlemode, &v); |
1246 | } | |
1247 | ||
a16b1f7f PW |
1248 | /* |
1249 | * XXX The clock framework should handle this, by | |
1250 | * calling into this code. But this must wait until the | |
1251 | * clock structures are tagged with omap_hwmod entries | |
1252 | */ | |
43b40992 PW |
1253 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1254 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
ca5339b1 | 1255 | _set_clockactivity(oh, CLOCKACT_TEST_ICLK, &v); |
63c85238 | 1256 | |
3ca4a238 | 1257 | _write_sysconfig(v, oh); |
78f26e87 HH |
1258 | |
1259 | /* | |
1260 | * Set the autoidle bit only after setting the smartidle bit | |
1261 | * Setting this will not have any impact on the other modules. | |
1262 | */ | |
1263 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1264 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1265 | 0 : 1; | |
1266 | _set_module_autoidle(oh, idlemode, &v); | |
1267 | _write_sysconfig(v, oh); | |
1268 | } | |
63c85238 PW |
1269 | } |
1270 | ||
1271 | /** | |
74ff3a68 | 1272 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1273 | * @oh: struct omap_hwmod * |
1274 | * | |
1275 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1276 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1277 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1278 | * configure it for smart-standby. No return value. | |
1279 | */ | |
74ff3a68 | 1280 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1281 | { |
43b40992 | 1282 | u8 idlemode, sf; |
63c85238 PW |
1283 | u32 v; |
1284 | ||
43b40992 | 1285 | if (!oh->class->sysc) |
63c85238 PW |
1286 | return; |
1287 | ||
1288 | v = oh->_sysc_cache; | |
43b40992 | 1289 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1290 | |
43b40992 | 1291 | if (sf & SYSC_HAS_SIDLEMODE) { |
35513171 | 1292 | if (oh->flags & HWMOD_SWSUP_SIDLE) { |
006c7f18 | 1293 | idlemode = HWMOD_IDLEMODE_FORCE; |
35513171 RN |
1294 | } else { |
1295 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1296 | _enable_wakeup(oh, &v); | |
1297 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) | |
1298 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1299 | else | |
1300 | idlemode = HWMOD_IDLEMODE_SMART; | |
1301 | } | |
63c85238 PW |
1302 | _set_slave_idlemode(oh, idlemode, &v); |
1303 | } | |
1304 | ||
43b40992 | 1305 | if (sf & SYSC_HAS_MIDLEMODE) { |
092bc089 GI |
1306 | if ((oh->flags & HWMOD_SWSUP_MSTANDBY) || |
1307 | (oh->flags & HWMOD_FORCE_MSTANDBY)) { | |
724019b0 BC |
1308 | idlemode = HWMOD_IDLEMODE_FORCE; |
1309 | } else { | |
1310 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1311 | _enable_wakeup(oh, &v); | |
1312 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1313 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1314 | else | |
1315 | idlemode = HWMOD_IDLEMODE_SMART; | |
1316 | } | |
63c85238 PW |
1317 | _set_master_standbymode(oh, idlemode, &v); |
1318 | } | |
1319 | ||
3ca4a238 LV |
1320 | /* If the cached value is the same as the new value, skip the write */ |
1321 | if (oh->_sysc_cache != v) | |
1322 | _write_sysconfig(v, oh); | |
63c85238 PW |
1323 | } |
1324 | ||
1325 | /** | |
74ff3a68 | 1326 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1327 | * @oh: struct omap_hwmod * |
1328 | * | |
1329 | * Force the module into slave idle and master suspend. No return | |
1330 | * value. | |
1331 | */ | |
74ff3a68 | 1332 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1333 | { |
1334 | u32 v; | |
43b40992 | 1335 | u8 sf; |
63c85238 | 1336 | |
43b40992 | 1337 | if (!oh->class->sysc) |
63c85238 PW |
1338 | return; |
1339 | ||
1340 | v = oh->_sysc_cache; | |
43b40992 | 1341 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1342 | |
43b40992 | 1343 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1344 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1345 | ||
43b40992 | 1346 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1347 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1348 | ||
43b40992 | 1349 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1350 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1351 | |
1352 | _write_sysconfig(v, oh); | |
1353 | } | |
1354 | ||
1355 | /** | |
1356 | * _lookup - find an omap_hwmod by name | |
1357 | * @name: find an omap_hwmod by name | |
1358 | * | |
1359 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1360 | */ |
1361 | static struct omap_hwmod *_lookup(const char *name) | |
1362 | { | |
1363 | struct omap_hwmod *oh, *temp_oh; | |
1364 | ||
1365 | oh = NULL; | |
1366 | ||
1367 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1368 | if (!strcmp(name, temp_oh->name)) { | |
1369 | oh = temp_oh; | |
1370 | break; | |
1371 | } | |
1372 | } | |
1373 | ||
1374 | return oh; | |
1375 | } | |
868c157d | 1376 | |
6ae76997 BC |
1377 | /** |
1378 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1379 | * @oh: struct omap_hwmod * | |
1380 | * | |
1381 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1382 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
868c157d | 1383 | * Return -EINVAL if the clkdm_name lookup failed. |
6ae76997 BC |
1384 | */ |
1385 | static int _init_clkdm(struct omap_hwmod *oh) | |
1386 | { | |
3bb05dbf PW |
1387 | if (!oh->clkdm_name) { |
1388 | pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); | |
6ae76997 | 1389 | return 0; |
3bb05dbf | 1390 | } |
6ae76997 | 1391 | |
6ae76997 BC |
1392 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1393 | if (!oh->clkdm) { | |
3d0cb73e | 1394 | pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n", |
6ae76997 | 1395 | oh->name, oh->clkdm_name); |
0385c582 | 1396 | return 0; |
6ae76997 BC |
1397 | } |
1398 | ||
1399 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1400 | oh->name, oh->clkdm_name); | |
1401 | ||
1402 | return 0; | |
1403 | } | |
63c85238 PW |
1404 | |
1405 | /** | |
6ae76997 BC |
1406 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1407 | * well the clockdomain. | |
63c85238 | 1408 | * @oh: struct omap_hwmod * |
70f05be3 | 1409 | * @np: device_node mapped to this hwmod |
63c85238 | 1410 | * |
a2debdbd | 1411 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1412 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1413 | * success, or a negative error code on failure. | |
63c85238 | 1414 | */ |
70f05be3 | 1415 | static int _init_clocks(struct omap_hwmod *oh, struct device_node *np) |
63c85238 PW |
1416 | { |
1417 | int ret = 0; | |
1418 | ||
48d54f3f PW |
1419 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1420 | return 0; | |
63c85238 PW |
1421 | |
1422 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1423 | ||
b797be1d VH |
1424 | if (soc_ops.init_clkdm) |
1425 | ret |= soc_ops.init_clkdm(oh); | |
1426 | ||
63c85238 PW |
1427 | ret |= _init_main_clk(oh); |
1428 | ret |= _init_interface_clks(oh); | |
1429 | ret |= _init_opt_clks(oh); | |
1430 | ||
f5c1f84b BC |
1431 | if (!ret) |
1432 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a | 1433 | else |
3d0cb73e | 1434 | pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name); |
63c85238 | 1435 | |
09c35f2f | 1436 | return ret; |
63c85238 PW |
1437 | } |
1438 | ||
5365efbe | 1439 | /** |
cc1226e7 | 1440 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1441 | * @oh: struct omap_hwmod * |
1442 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1443 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1444 | * |
1445 | * Return the bit position of the reset line that match the | |
1446 | * input name. Return -ENOENT if not found. | |
1447 | */ | |
a032d33b PW |
1448 | static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1449 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1450 | { |
1451 | int i; | |
1452 | ||
1453 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1454 | const char *rst_line = oh->rst_lines[i].name; | |
1455 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1456 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1457 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1458 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1459 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1460 | ohri->st_shift); | |
5365efbe | 1461 | |
cc1226e7 | 1462 | return 0; |
5365efbe BC |
1463 | } |
1464 | } | |
1465 | ||
1466 | return -ENOENT; | |
1467 | } | |
1468 | ||
1469 | /** | |
1470 | * _assert_hardreset - assert the HW reset line of submodules | |
1471 | * contained in the hwmod module. | |
1472 | * @oh: struct omap_hwmod * | |
1473 | * @name: name of the reset line to lookup and assert | |
1474 | * | |
b8249cf2 KH |
1475 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1476 | * reset line to be assert / deassert in order to enable fully the IP. | |
1477 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1478 | * asserting the hardreset line on the currently-booted SoC, or passes | |
1479 | * along the return value from _lookup_hardreset() or the SoC's | |
1480 | * assert_hardreset code. | |
5365efbe BC |
1481 | */ |
1482 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1483 | { | |
cc1226e7 | 1484 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1485 | int ret = -EINVAL; |
5365efbe BC |
1486 | |
1487 | if (!oh) | |
1488 | return -EINVAL; | |
1489 | ||
b8249cf2 KH |
1490 | if (!soc_ops.assert_hardreset) |
1491 | return -ENOSYS; | |
1492 | ||
cc1226e7 | 1493 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1494 | if (ret < 0) |
cc1226e7 | 1495 | return ret; |
5365efbe | 1496 | |
b8249cf2 KH |
1497 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1498 | ||
1499 | return ret; | |
5365efbe BC |
1500 | } |
1501 | ||
1502 | /** | |
1503 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1504 | * in the hwmod module. | |
1505 | * @oh: struct omap_hwmod * | |
1506 | * @name: name of the reset line to look up and deassert | |
1507 | * | |
b8249cf2 KH |
1508 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1509 | * reset line to be assert / deassert in order to enable fully the IP. | |
1510 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1511 | * deasserting the hardreset line on the currently-booted SoC, or passes | |
1512 | * along the return value from _lookup_hardreset() or the SoC's | |
1513 | * deassert_hardreset code. | |
5365efbe BC |
1514 | */ |
1515 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1516 | { | |
cc1226e7 | 1517 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1518 | int ret = -EINVAL; |
5365efbe BC |
1519 | |
1520 | if (!oh) | |
1521 | return -EINVAL; | |
1522 | ||
b8249cf2 KH |
1523 | if (!soc_ops.deassert_hardreset) |
1524 | return -ENOSYS; | |
1525 | ||
cc1226e7 | 1526 | ret = _lookup_hardreset(oh, name, &ohri); |
c48cd659 | 1527 | if (ret < 0) |
cc1226e7 | 1528 | return ret; |
5365efbe | 1529 | |
e8e96dff ORL |
1530 | if (oh->clkdm) { |
1531 | /* | |
1532 | * A clockdomain must be in SW_SUP otherwise reset | |
1533 | * might not be completed. The clockdomain can be set | |
1534 | * in HW_AUTO only when the module become ready. | |
1535 | */ | |
1d9a5425 | 1536 | clkdm_deny_idle(oh->clkdm); |
e8e96dff ORL |
1537 | ret = clkdm_hwmod_enable(oh->clkdm, oh); |
1538 | if (ret) { | |
1539 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1540 | oh->name, oh->clkdm->name, ret); | |
1541 | return ret; | |
1542 | } | |
1543 | } | |
1544 | ||
1545 | _enable_clocks(oh); | |
1546 | if (soc_ops.enable_module) | |
1547 | soc_ops.enable_module(oh); | |
1548 | ||
b8249cf2 | 1549 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
e8e96dff ORL |
1550 | |
1551 | if (soc_ops.disable_module) | |
1552 | soc_ops.disable_module(oh); | |
1553 | _disable_clocks(oh); | |
1554 | ||
cc1226e7 | 1555 | if (ret == -EBUSY) |
3d0cb73e | 1556 | pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name); |
5365efbe | 1557 | |
80d2518d | 1558 | if (oh->clkdm) { |
e8e96dff ORL |
1559 | /* |
1560 | * Set the clockdomain to HW_AUTO, assuming that the | |
1561 | * previous state was HW_AUTO. | |
1562 | */ | |
1d9a5425 | 1563 | clkdm_allow_idle(oh->clkdm); |
80d2518d TK |
1564 | |
1565 | clkdm_hwmod_disable(oh->clkdm, oh); | |
e8e96dff ORL |
1566 | } |
1567 | ||
cc1226e7 | 1568 | return ret; |
5365efbe BC |
1569 | } |
1570 | ||
1571 | /** | |
1572 | * _read_hardreset - read the HW reset line state of submodules | |
1573 | * contained in the hwmod module | |
1574 | * @oh: struct omap_hwmod * | |
1575 | * @name: name of the reset line to look up and read | |
1576 | * | |
b8249cf2 KH |
1577 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1578 | * null, -ENOSYS if we have no way of reading the hardreset line | |
1579 | * status on the currently-booted SoC, or passes along the return | |
1580 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | |
1581 | * code. | |
5365efbe BC |
1582 | */ |
1583 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1584 | { | |
cc1226e7 | 1585 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1586 | int ret = -EINVAL; |
5365efbe BC |
1587 | |
1588 | if (!oh) | |
1589 | return -EINVAL; | |
1590 | ||
b8249cf2 KH |
1591 | if (!soc_ops.is_hardreset_asserted) |
1592 | return -ENOSYS; | |
1593 | ||
cc1226e7 | 1594 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1595 | if (ret < 0) |
cc1226e7 | 1596 | return ret; |
5365efbe | 1597 | |
b8249cf2 | 1598 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
5365efbe BC |
1599 | } |
1600 | ||
747834ab | 1601 | /** |
eb05f691 | 1602 | * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset |
747834ab PW |
1603 | * @oh: struct omap_hwmod * |
1604 | * | |
eb05f691 ORL |
1605 | * If all hardreset lines associated with @oh are asserted, then return true. |
1606 | * Otherwise, if part of @oh is out hardreset or if no hardreset lines | |
1607 | * associated with @oh are asserted, then return false. | |
747834ab | 1608 | * This function is used to avoid executing some parts of the IP block |
eb05f691 | 1609 | * enable/disable sequence if its hardreset line is set. |
747834ab | 1610 | */ |
eb05f691 | 1611 | static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) |
747834ab | 1612 | { |
eb05f691 | 1613 | int i, rst_cnt = 0; |
747834ab PW |
1614 | |
1615 | if (oh->rst_lines_cnt == 0) | |
1616 | return false; | |
1617 | ||
1618 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1619 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
eb05f691 ORL |
1620 | rst_cnt++; |
1621 | ||
1622 | if (oh->rst_lines_cnt == rst_cnt) | |
1623 | return true; | |
747834ab PW |
1624 | |
1625 | return false; | |
1626 | } | |
1627 | ||
e9332b6e PW |
1628 | /** |
1629 | * _are_any_hardreset_lines_asserted - return true if any part of @oh is | |
1630 | * hard-reset | |
1631 | * @oh: struct omap_hwmod * | |
1632 | * | |
1633 | * If any hardreset lines associated with @oh are asserted, then | |
1634 | * return true. Otherwise, if no hardreset lines associated with @oh | |
1635 | * are asserted, or if @oh has no hardreset lines, then return false. | |
1636 | * This function is used to avoid executing some parts of the IP block | |
1637 | * enable/disable sequence if any hardreset line is set. | |
1638 | */ | |
1639 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1640 | { | |
1641 | int rst_cnt = 0; | |
1642 | int i; | |
1643 | ||
1644 | for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++) | |
1645 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1646 | rst_cnt++; | |
1647 | ||
1648 | return (rst_cnt) ? true : false; | |
1649 | } | |
1650 | ||
747834ab PW |
1651 | /** |
1652 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1653 | * @oh: struct omap_hwmod * | |
1654 | * | |
1655 | * Disable the PRCM module mode related to the hwmod @oh. | |
1656 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1657 | */ | |
1658 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1659 | { | |
1660 | int v; | |
1661 | ||
8823ddf2 TL |
1662 | if (!oh->clkdm || !oh->prcm.omap4.modulemode || |
1663 | _omap4_clkctrl_managed_by_clkfwk(oh)) | |
747834ab PW |
1664 | return -EINVAL; |
1665 | ||
eb05f691 ORL |
1666 | /* |
1667 | * Since integration code might still be doing something, only | |
1668 | * disable if all lines are under hardreset. | |
1669 | */ | |
e9332b6e | 1670 | if (_are_any_hardreset_lines_asserted(oh)) |
eb05f691 ORL |
1671 | return 0; |
1672 | ||
747834ab PW |
1673 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); |
1674 | ||
128603f0 TK |
1675 | omap_cm_module_disable(oh->clkdm->prcm_partition, oh->clkdm->cm_inst, |
1676 | oh->prcm.omap4.clkctrl_offs); | |
747834ab | 1677 | |
747834ab PW |
1678 | v = _omap4_wait_target_disable(oh); |
1679 | if (v) | |
1680 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1681 | oh->name); | |
1682 | ||
1683 | return 0; | |
1684 | } | |
1685 | ||
63c85238 | 1686 | /** |
bd36179e | 1687 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1688 | * @oh: struct omap_hwmod * |
1689 | * | |
1690 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1691 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1692 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1693 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1694 | * |
1695 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1696 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1697 | * use the SYSCONFIG softreset bit to provide the status. |
1698 | * | |
bd36179e PW |
1699 | * Note that some IP like McBSP do have reset control but don't have |
1700 | * reset status. | |
63c85238 | 1701 | */ |
bd36179e | 1702 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1703 | { |
613ad0e9 | 1704 | u32 v; |
6f8b7ff5 | 1705 | int c = 0; |
96835af9 | 1706 | int ret = 0; |
63c85238 | 1707 | |
43b40992 | 1708 | if (!oh->class->sysc || |
2cb06814 | 1709 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1710 | return -ENOENT; |
63c85238 PW |
1711 | |
1712 | /* clocks must be on for this operation */ | |
1713 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
7852ec05 PW |
1714 | pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", |
1715 | oh->name); | |
63c85238 PW |
1716 | return -EINVAL; |
1717 | } | |
1718 | ||
96835af9 BC |
1719 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1720 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1721 | _enable_optional_clocks(oh); | |
1722 | ||
bd36179e | 1723 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1724 | |
1725 | v = oh->_sysc_cache; | |
96835af9 BC |
1726 | ret = _set_softreset(oh, &v); |
1727 | if (ret) | |
1728 | goto dis_opt_clks; | |
313a76ee | 1729 | |
63c85238 PW |
1730 | _write_sysconfig(v, oh); |
1731 | ||
d99de7f5 FGL |
1732 | if (oh->class->sysc->srst_udelay) |
1733 | udelay(oh->class->sysc->srst_udelay); | |
1734 | ||
613ad0e9 | 1735 | c = _wait_softreset_complete(oh); |
01142519 | 1736 | if (c == MAX_MODULE_SOFTRESET_WAIT) { |
3d0cb73e JP |
1737 | pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1738 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
01142519 IS |
1739 | ret = -ETIMEDOUT; |
1740 | goto dis_opt_clks; | |
1741 | } else { | |
5365efbe | 1742 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
01142519 IS |
1743 | } |
1744 | ||
1745 | ret = _clear_softreset(oh, &v); | |
1746 | if (ret) | |
1747 | goto dis_opt_clks; | |
1748 | ||
1749 | _write_sysconfig(v, oh); | |
63c85238 PW |
1750 | |
1751 | /* | |
1752 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1753 | * _wait_target_ready() or _reset() | |
1754 | */ | |
1755 | ||
96835af9 BC |
1756 | dis_opt_clks: |
1757 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1758 | _disable_optional_clocks(oh); | |
1759 | ||
1760 | return ret; | |
63c85238 PW |
1761 | } |
1762 | ||
bd36179e PW |
1763 | /** |
1764 | * _reset - reset an omap_hwmod | |
1765 | * @oh: struct omap_hwmod * | |
1766 | * | |
30e105c0 PW |
1767 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1768 | * function pointer defined, then call it to reset the IP block, and | |
1769 | * pass along its return value to the caller. Otherwise, if the IP | |
1770 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1771 | * associated with it, call a function to reset the IP block via that | |
1772 | * method, and pass along the return value to the caller. Finally, if | |
1773 | * the IP block has some hardreset lines associated with it, assert | |
1774 | * all of those, but do _not_ deassert them. (This is because driver | |
1775 | * authors have expressed an apparent requirement to control the | |
1776 | * deassertion of the hardreset lines themselves.) | |
1777 | * | |
1778 | * The default software reset mechanism for most OMAP IP blocks is | |
1779 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1780 | * hwmods cannot be reset via this method. Some are not targets and | |
1781 | * therefore have no OCP header registers to access. Others (like the | |
1782 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1783 | * rare cases, custom reset code can be supplied in the struct | |
6668546f KVA |
1784 | * omap_hwmod_class .reset function pointer. |
1785 | * | |
1786 | * _set_dmadisable() is called to set the DMADISABLE bit so that it | |
1787 | * does not prevent idling of the system. This is necessary for cases | |
1788 | * where ROMCODE/BOOTLOADER uses dma and transfers control to the | |
1789 | * kernel without disabling dma. | |
1790 | * | |
1791 | * Passes along the return value from either _ocp_softreset() or the | |
1792 | * custom reset function - these must return -EINVAL if the hwmod | |
1793 | * cannot be reset this way or if the hwmod is in the wrong state, | |
1794 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
bd36179e PW |
1795 | */ |
1796 | static int _reset(struct omap_hwmod *oh) | |
1797 | { | |
30e105c0 | 1798 | int i, r; |
bd36179e PW |
1799 | |
1800 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1801 | ||
30e105c0 PW |
1802 | if (oh->class->reset) { |
1803 | r = oh->class->reset(oh); | |
1804 | } else { | |
1805 | if (oh->rst_lines_cnt > 0) { | |
1806 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1807 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1808 | return 0; | |
1809 | } else { | |
1810 | r = _ocp_softreset(oh); | |
1811 | if (r == -ENOENT) | |
1812 | r = 0; | |
1813 | } | |
1814 | } | |
1815 | ||
6668546f KVA |
1816 | _set_dmadisable(oh); |
1817 | ||
9c8b0ec7 | 1818 | /* |
30e105c0 PW |
1819 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1820 | * softreset. The _enable() function should be split to avoid | |
1821 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1822 | */ |
2800852a RN |
1823 | if (oh->class->sysc) { |
1824 | _update_sysc_cache(oh); | |
1825 | _enable_sysc(oh); | |
1826 | } | |
1827 | ||
30e105c0 | 1828 | return r; |
bd36179e PW |
1829 | } |
1830 | ||
e6d3a8b0 RN |
1831 | /** |
1832 | * _omap4_update_context_lost - increment hwmod context loss counter if | |
1833 | * hwmod context was lost, and clear hardware context loss reg | |
1834 | * @oh: hwmod to check for context loss | |
1835 | * | |
1836 | * If the PRCM indicates that the hwmod @oh lost context, increment | |
1837 | * our in-memory context loss counter, and clear the RM_*_CONTEXT | |
1838 | * bits. No return value. | |
1839 | */ | |
1840 | static void _omap4_update_context_lost(struct omap_hwmod *oh) | |
1841 | { | |
1842 | if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT) | |
1843 | return; | |
1844 | ||
1845 | if (!prm_was_any_context_lost_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
1846 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1847 | oh->prcm.omap4.context_offs)) | |
1848 | return; | |
1849 | ||
1850 | oh->prcm.omap4.context_lost_counter++; | |
1851 | prm_clear_context_loss_flags_old(oh->clkdm->pwrdm.ptr->prcm_partition, | |
1852 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1853 | oh->prcm.omap4.context_offs); | |
1854 | } | |
1855 | ||
1856 | /** | |
1857 | * _omap4_get_context_lost - get context loss counter for a hwmod | |
1858 | * @oh: hwmod to get context loss counter for | |
1859 | * | |
1860 | * Returns the in-memory context loss counter for a hwmod. | |
1861 | */ | |
1862 | static int _omap4_get_context_lost(struct omap_hwmod *oh) | |
1863 | { | |
1864 | return oh->prcm.omap4.context_lost_counter; | |
1865 | } | |
1866 | ||
6d266f63 PW |
1867 | /** |
1868 | * _enable_preprogram - Pre-program an IP block during the _enable() process | |
1869 | * @oh: struct omap_hwmod * | |
1870 | * | |
1871 | * Some IP blocks (such as AESS) require some additional programming | |
1872 | * after enable before they can enter idle. If a function pointer to | |
1873 | * do so is present in the hwmod data, then call it and pass along the | |
1874 | * return value; otherwise, return 0. | |
1875 | */ | |
0f497039 | 1876 | static int _enable_preprogram(struct omap_hwmod *oh) |
6d266f63 PW |
1877 | { |
1878 | if (!oh->class->enable_preprogram) | |
1879 | return 0; | |
1880 | ||
1881 | return oh->class->enable_preprogram(oh); | |
1882 | } | |
1883 | ||
63c85238 | 1884 | /** |
dc6d1cda | 1885 | * _enable - enable an omap_hwmod |
63c85238 PW |
1886 | * @oh: struct omap_hwmod * |
1887 | * | |
1888 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
1889 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1890 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1891 | */ |
dc6d1cda | 1892 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 1893 | { |
747834ab | 1894 | int r; |
63c85238 | 1895 | |
34617e2a BC |
1896 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
1897 | ||
aacf0941 | 1898 | /* |
64813c3f | 1899 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
b4281455 | 1900 | * state at init. |
aacf0941 RN |
1901 | */ |
1902 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
aacf0941 RN |
1903 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; |
1904 | return 0; | |
1905 | } | |
1906 | ||
63c85238 PW |
1907 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
1908 | oh->_state != _HWMOD_STATE_IDLE && | |
1909 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
1910 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
1911 | oh->name); | |
63c85238 PW |
1912 | return -EINVAL; |
1913 | } | |
1914 | ||
31f62866 | 1915 | /* |
eb05f691 | 1916 | * If an IP block contains HW reset lines and all of them are |
747834ab PW |
1917 | * asserted, we let integration code associated with that |
1918 | * block handle the enable. We've received very little | |
1919 | * information on what those driver authors need, and until | |
1920 | * detailed information is provided and the driver code is | |
1921 | * posted to the public lists, this is probably the best we | |
1922 | * can do. | |
31f62866 | 1923 | */ |
eb05f691 | 1924 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab | 1925 | return 0; |
63c85238 | 1926 | |
665d0013 | 1927 | _add_initiator_dep(oh, mpu_oh); |
34617e2a | 1928 | |
665d0013 RN |
1929 | if (oh->clkdm) { |
1930 | /* | |
1931 | * A clockdomain must be in SW_SUP before enabling | |
1932 | * completely the module. The clockdomain can be set | |
1933 | * in HW_AUTO only when the module become ready. | |
1934 | */ | |
1d9a5425 | 1935 | clkdm_deny_idle(oh->clkdm); |
665d0013 RN |
1936 | r = clkdm_hwmod_enable(oh->clkdm, oh); |
1937 | if (r) { | |
1938 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1939 | oh->name, oh->clkdm->name, r); | |
1940 | return r; | |
1941 | } | |
34617e2a | 1942 | } |
665d0013 RN |
1943 | |
1944 | _enable_clocks(oh); | |
9ebfd285 KH |
1945 | if (soc_ops.enable_module) |
1946 | soc_ops.enable_module(oh); | |
fa200222 | 1947 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 1948 | cpu_idle_poll_ctrl(true); |
34617e2a | 1949 | |
e6d3a8b0 RN |
1950 | if (soc_ops.update_context_lost) |
1951 | soc_ops.update_context_lost(oh); | |
1952 | ||
8f6aa8ee KH |
1953 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
1954 | -EINVAL; | |
8ff42da4 | 1955 | if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO)) |
1d9a5425 | 1956 | clkdm_allow_idle(oh->clkdm); |
665d0013 | 1957 | |
1d9a5425 | 1958 | if (!r) { |
665d0013 RN |
1959 | oh->_state = _HWMOD_STATE_ENABLED; |
1960 | ||
1961 | /* Access the sysconfig only if the target is ready */ | |
1962 | if (oh->class->sysc) { | |
1963 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
1964 | _update_sysc_cache(oh); | |
1965 | _enable_sysc(oh); | |
1966 | } | |
6d266f63 | 1967 | r = _enable_preprogram(oh); |
665d0013 | 1968 | } else { |
2577a4a6 PW |
1969 | if (soc_ops.disable_module) |
1970 | soc_ops.disable_module(oh); | |
665d0013 | 1971 | _disable_clocks(oh); |
812ce9d2 LV |
1972 | pr_err("omap_hwmod: %s: _wait_target_ready failed: %d\n", |
1973 | oh->name, r); | |
34617e2a | 1974 | |
665d0013 RN |
1975 | if (oh->clkdm) |
1976 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
1977 | } |
1978 | ||
63c85238 PW |
1979 | return r; |
1980 | } | |
1981 | ||
1982 | /** | |
dc6d1cda | 1983 | * _idle - idle an omap_hwmod |
63c85238 PW |
1984 | * @oh: struct omap_hwmod * |
1985 | * | |
1986 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
1987 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
1988 | * state or returns 0. | |
63c85238 | 1989 | */ |
dc6d1cda | 1990 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 1991 | { |
2e18f5a1 LV |
1992 | if (oh->flags & HWMOD_NO_IDLE) { |
1993 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
1994 | return 0; | |
1995 | } | |
1996 | ||
34617e2a BC |
1997 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
1998 | ||
c20c8f75 SA |
1999 | if (_are_all_hardreset_lines_asserted(oh)) |
2000 | return 0; | |
2001 | ||
63c85238 | 2002 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
2003 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
2004 | oh->name); | |
63c85238 PW |
2005 | return -EINVAL; |
2006 | } | |
2007 | ||
43b40992 | 2008 | if (oh->class->sysc) |
74ff3a68 | 2009 | _idle_sysc(oh); |
63c85238 | 2010 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 | 2011 | |
8ff42da4 RQ |
2012 | /* |
2013 | * If HWMOD_CLKDM_NOAUTO is set then we don't | |
2014 | * deny idle the clkdm again since idle was already denied | |
2015 | * in _enable() | |
2016 | */ | |
2017 | if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO)) | |
1d9a5425 TK |
2018 | clkdm_deny_idle(oh->clkdm); |
2019 | ||
fa200222 | 2020 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2021 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2022 | if (soc_ops.disable_module) |
2023 | soc_ops.disable_module(oh); | |
bfc141e3 | 2024 | |
45c38252 BC |
2025 | /* |
2026 | * The module must be in idle mode before disabling any parents | |
2027 | * clocks. Otherwise, the parent clock might be disabled before | |
2028 | * the module transition is done, and thus will prevent the | |
2029 | * transition to complete properly. | |
2030 | */ | |
2031 | _disable_clocks(oh); | |
1d9a5425 TK |
2032 | if (oh->clkdm) { |
2033 | clkdm_allow_idle(oh->clkdm); | |
665d0013 | 2034 | clkdm_hwmod_disable(oh->clkdm, oh); |
1d9a5425 | 2035 | } |
63c85238 PW |
2036 | |
2037 | oh->_state = _HWMOD_STATE_IDLE; | |
2038 | ||
2039 | return 0; | |
2040 | } | |
2041 | ||
2042 | /** | |
2043 | * _shutdown - shutdown an omap_hwmod | |
2044 | * @oh: struct omap_hwmod * | |
2045 | * | |
2046 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
2047 | * used for the hwmod is removed or unloaded or if the driver is not | |
2048 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
2049 | * state or returns 0. | |
2050 | */ | |
2051 | static int _shutdown(struct omap_hwmod *oh) | |
2052 | { | |
9c8b0ec7 | 2053 | int ret, i; |
e4dc8f50 PW |
2054 | u8 prev_state; |
2055 | ||
c20c8f75 SA |
2056 | if (_are_all_hardreset_lines_asserted(oh)) |
2057 | return 0; | |
2058 | ||
63c85238 PW |
2059 | if (oh->_state != _HWMOD_STATE_IDLE && |
2060 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
2061 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
2062 | oh->name); | |
63c85238 PW |
2063 | return -EINVAL; |
2064 | } | |
2065 | ||
2066 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | |
2067 | ||
e4dc8f50 PW |
2068 | if (oh->class->pre_shutdown) { |
2069 | prev_state = oh->_state; | |
2070 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2071 | _enable(oh); |
e4dc8f50 PW |
2072 | ret = oh->class->pre_shutdown(oh); |
2073 | if (ret) { | |
2074 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2075 | _idle(oh); |
e4dc8f50 PW |
2076 | return ret; |
2077 | } | |
2078 | } | |
2079 | ||
6481c73c MV |
2080 | if (oh->class->sysc) { |
2081 | if (oh->_state == _HWMOD_STATE_IDLE) | |
2082 | _enable(oh); | |
74ff3a68 | 2083 | _shutdown_sysc(oh); |
6481c73c | 2084 | } |
5365efbe | 2085 | |
3827f949 BC |
2086 | /* clocks and deps are already disabled in idle */ |
2087 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
2088 | _del_initiator_dep(oh, mpu_oh); | |
2089 | /* XXX what about the other system initiators here? dma, dsp */ | |
fa200222 | 2090 | if (oh->flags & HWMOD_BLOCK_WFI) |
f7b861b7 | 2091 | cpu_idle_poll_ctrl(false); |
9ebfd285 KH |
2092 | if (soc_ops.disable_module) |
2093 | soc_ops.disable_module(oh); | |
45c38252 | 2094 | _disable_clocks(oh); |
665d0013 RN |
2095 | if (oh->clkdm) |
2096 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 2097 | } |
63c85238 PW |
2098 | /* XXX Should this code also force-disable the optional clocks? */ |
2099 | ||
9c8b0ec7 PW |
2100 | for (i = 0; i < oh->rst_lines_cnt; i++) |
2101 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 2102 | |
63c85238 PW |
2103 | oh->_state = _HWMOD_STATE_DISABLED; |
2104 | ||
2105 | return 0; | |
2106 | } | |
2107 | ||
5e863c56 TL |
2108 | static int of_dev_find_hwmod(struct device_node *np, |
2109 | struct omap_hwmod *oh) | |
2110 | { | |
2111 | int count, i, res; | |
2112 | const char *p; | |
2113 | ||
2114 | count = of_property_count_strings(np, "ti,hwmods"); | |
2115 | if (count < 1) | |
2116 | return -ENODEV; | |
2117 | ||
2118 | for (i = 0; i < count; i++) { | |
2119 | res = of_property_read_string_index(np, "ti,hwmods", | |
2120 | i, &p); | |
2121 | if (res) | |
2122 | continue; | |
2123 | if (!strcmp(p, oh->name)) { | |
6e771379 RH |
2124 | pr_debug("omap_hwmod: dt %pOFn[%i] uses hwmod %s\n", |
2125 | np, i, oh->name); | |
5e863c56 TL |
2126 | return i; |
2127 | } | |
2128 | } | |
2129 | ||
2130 | return -ENODEV; | |
2131 | } | |
2132 | ||
079abade SS |
2133 | /** |
2134 | * of_dev_hwmod_lookup - look up needed hwmod from dt blob | |
2135 | * @np: struct device_node * | |
2136 | * @oh: struct omap_hwmod * | |
5e863c56 TL |
2137 | * @index: index of the entry found |
2138 | * @found: struct device_node * found or NULL | |
079abade SS |
2139 | * |
2140 | * Parse the dt blob and find out needed hwmod. Recursive function is | |
2141 | * implemented to take care hierarchical dt blob parsing. | |
5e863c56 | 2142 | * Return: Returns 0 on success, -ENODEV when not found. |
079abade | 2143 | */ |
5e863c56 TL |
2144 | static int of_dev_hwmod_lookup(struct device_node *np, |
2145 | struct omap_hwmod *oh, | |
2146 | int *index, | |
2147 | struct device_node **found) | |
079abade | 2148 | { |
5e863c56 TL |
2149 | struct device_node *np0 = NULL; |
2150 | int res; | |
2151 | ||
2152 | res = of_dev_find_hwmod(np, oh); | |
2153 | if (res >= 0) { | |
2154 | *found = np; | |
2155 | *index = res; | |
2156 | return 0; | |
2157 | } | |
079abade SS |
2158 | |
2159 | for_each_child_of_node(np, np0) { | |
5e863c56 TL |
2160 | struct device_node *fc; |
2161 | int i; | |
2162 | ||
2163 | res = of_dev_hwmod_lookup(np0, oh, &i, &fc); | |
2164 | if (res == 0) { | |
2165 | *found = fc; | |
2166 | *index = i; | |
2167 | return 0; | |
079abade SS |
2168 | } |
2169 | } | |
5e863c56 TL |
2170 | |
2171 | *found = NULL; | |
2172 | *index = 0; | |
2173 | ||
2174 | return -ENODEV; | |
079abade SS |
2175 | } |
2176 | ||
1dbcb97c TL |
2177 | /** |
2178 | * omap_hwmod_fix_mpu_rt_idx - fix up mpu_rt_idx register offsets | |
2179 | * | |
2180 | * @oh: struct omap_hwmod * | |
2181 | * @np: struct device_node * | |
2182 | * | |
2183 | * Fix up module register offsets for modules with mpu_rt_idx. | |
2184 | * Only needed for cpsw with interconnect target module defined | |
2185 | * in device tree while still using legacy hwmod platform data | |
2186 | * for rev, sysc and syss registers. | |
2187 | * | |
2188 | * Can be removed when all cpsw hwmod platform data has been | |
2189 | * dropped. | |
2190 | */ | |
2191 | static void omap_hwmod_fix_mpu_rt_idx(struct omap_hwmod *oh, | |
2192 | struct device_node *np, | |
2193 | struct resource *res) | |
2194 | { | |
2195 | struct device_node *child = NULL; | |
2196 | int error; | |
2197 | ||
2198 | child = of_get_next_child(np, child); | |
2199 | if (!child) | |
2200 | return; | |
2201 | ||
2202 | error = of_address_to_resource(child, oh->mpu_rt_idx, res); | |
2203 | if (error) | |
2204 | pr_err("%s: error mapping mpu_rt_idx: %i\n", | |
2205 | __func__, error); | |
2206 | } | |
2207 | ||
6c72b355 TL |
2208 | /** |
2209 | * omap_hwmod_parse_module_range - map module IO range from device tree | |
2210 | * @oh: struct omap_hwmod * | |
2211 | * @np: struct device_node * | |
2212 | * | |
2213 | * Parse the device tree range an interconnect target module provides | |
2214 | * for it's child device IP blocks. This way we can support the old | |
2215 | * "ti,hwmods" property with just dts data without a need for platform | |
2216 | * data for IO resources. And we don't need all the child IP device | |
2217 | * nodes available in the dts. | |
2218 | */ | |
2219 | int omap_hwmod_parse_module_range(struct omap_hwmod *oh, | |
2220 | struct device_node *np, | |
2221 | struct resource *res) | |
2222 | { | |
2223 | struct property *prop; | |
2224 | const __be32 *ranges; | |
2225 | const char *name; | |
2226 | u32 nr_addr, nr_size; | |
2227 | u64 base, size; | |
2228 | int len, error; | |
2229 | ||
2230 | if (!res) | |
2231 | return -EINVAL; | |
2232 | ||
2233 | ranges = of_get_property(np, "ranges", &len); | |
2234 | if (!ranges) | |
2235 | return -ENOENT; | |
2236 | ||
2237 | len /= sizeof(*ranges); | |
2238 | ||
2239 | if (len < 3) | |
2240 | return -EINVAL; | |
2241 | ||
2242 | of_property_for_each_string(np, "compatible", prop, name) | |
2243 | if (!strncmp("ti,sysc-", name, 8)) | |
2244 | break; | |
2245 | ||
2246 | if (!name) | |
2247 | return -ENOENT; | |
2248 | ||
2249 | error = of_property_read_u32(np, "#address-cells", &nr_addr); | |
2250 | if (error) | |
2251 | return -ENOENT; | |
2252 | ||
2253 | error = of_property_read_u32(np, "#size-cells", &nr_size); | |
2254 | if (error) | |
2255 | return -ENOENT; | |
2256 | ||
2257 | if (nr_addr != 1 || nr_size != 1) { | |
6e771379 RH |
2258 | pr_err("%s: invalid range for %s->%pOFn\n", __func__, |
2259 | oh->name, np); | |
6c72b355 TL |
2260 | return -EINVAL; |
2261 | } | |
2262 | ||
2263 | ranges++; | |
2264 | base = of_translate_address(np, ranges++); | |
2265 | size = be32_to_cpup(ranges); | |
2266 | ||
6e771379 RH |
2267 | pr_debug("omap_hwmod: %s %pOFn at 0x%llx size 0x%llx\n", |
2268 | oh->name, np, base, size); | |
6c72b355 | 2269 | |
1dbcb97c TL |
2270 | if (oh && oh->mpu_rt_idx) { |
2271 | omap_hwmod_fix_mpu_rt_idx(oh, np, res); | |
2272 | ||
2273 | return 0; | |
2274 | } | |
2275 | ||
6c72b355 TL |
2276 | res->start = base; |
2277 | res->end = base + size - 1; | |
2278 | res->flags = IORESOURCE_MEM; | |
2279 | ||
2280 | return 0; | |
2281 | } | |
2282 | ||
381d033a PW |
2283 | /** |
2284 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
2285 | * @oh: struct omap_hwmod * to locate the virtual address | |
f92d9597 | 2286 | * @data: (unused, caller should pass NULL) |
5e863c56 | 2287 | * @index: index of the reg entry iospace in device tree |
f92d9597 | 2288 | * @np: struct device_node * of the IP block's device node in the DT data |
381d033a PW |
2289 | * |
2290 | * Cache the virtual address used by the MPU to access this IP block's | |
2291 | * registers. This address is needed early so the OCP registers that | |
2292 | * are part of the device's address space can be ioremapped properly. | |
6423d6df | 2293 | * |
9a258afa RQ |
2294 | * If SYSC access is not needed, the registers will not be remapped |
2295 | * and non-availability of MPU access is not treated as an error. | |
2296 | * | |
6423d6df SA |
2297 | * Returns 0 on success, -EINVAL if an invalid hwmod is passed, and |
2298 | * -ENXIO on absent or invalid register target address space. | |
381d033a | 2299 | */ |
f92d9597 | 2300 | static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data, |
5e863c56 | 2301 | int index, struct device_node *np) |
381d033a | 2302 | { |
079abade | 2303 | void __iomem *va_start = NULL; |
6c72b355 TL |
2304 | struct resource res; |
2305 | int error; | |
c9aafd23 PW |
2306 | |
2307 | if (!oh) | |
6423d6df | 2308 | return -EINVAL; |
c9aafd23 | 2309 | |
2221b5cd PW |
2310 | _save_mpu_port_index(oh); |
2311 | ||
9a258afa RQ |
2312 | /* if we don't need sysc access we don't need to ioremap */ |
2313 | if (!oh->class->sysc) | |
2314 | return 0; | |
2315 | ||
2316 | /* we can't continue without MPU PORT if we need sysc access */ | |
381d033a | 2317 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
6423d6df | 2318 | return -ENXIO; |
381d033a | 2319 | |
9cffb1a0 TL |
2320 | if (!np) { |
2321 | pr_err("omap_hwmod: %s: no dt node\n", oh->name); | |
2322 | return -ENXIO; | |
c9aafd23 PW |
2323 | } |
2324 | ||
9cffb1a0 TL |
2325 | /* Do we have a dts range for the interconnect target module? */ |
2326 | error = omap_hwmod_parse_module_range(oh, np, &res); | |
2327 | if (!error) | |
2328 | va_start = ioremap(res.start, resource_size(&res)); | |
2329 | ||
2330 | /* No ranges, rely on device reg entry */ | |
2331 | if (!va_start) | |
2332 | va_start = of_iomap(np, index + oh->mpu_rt_idx); | |
c9aafd23 | 2333 | if (!va_start) { |
9cffb1a0 TL |
2334 | pr_err("omap_hwmod: %s: Missing dt reg%i for %pOF\n", |
2335 | oh->name, index, np); | |
6423d6df | 2336 | return -ENXIO; |
c9aafd23 PW |
2337 | } |
2338 | ||
2339 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
2340 | oh->name, va_start); | |
2341 | ||
2342 | oh->_mpu_rt_va = va_start; | |
6423d6df | 2343 | return 0; |
381d033a PW |
2344 | } |
2345 | ||
2346 | /** | |
2347 | * _init - initialize internal data for the hwmod @oh | |
2348 | * @oh: struct omap_hwmod * | |
2349 | * @n: (unused) | |
2350 | * | |
2351 | * Look up the clocks and the address space used by the MPU to access | |
2352 | * registers belonging to the hwmod @oh. @oh must already be | |
2353 | * registered at this point. This is the first of two phases for | |
2354 | * hwmod initialization. Code called here does not touch any hardware | |
2355 | * registers, it simply prepares internal data structures. Returns 0 | |
6423d6df SA |
2356 | * upon success or if the hwmod isn't registered or if the hwmod's |
2357 | * address space is not defined, or -EINVAL upon failure. | |
381d033a PW |
2358 | */ |
2359 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2360 | { | |
5e863c56 | 2361 | int r, index; |
f92d9597 | 2362 | struct device_node *np = NULL; |
1aa8f0cb | 2363 | struct device_node *bus; |
381d033a PW |
2364 | |
2365 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2366 | return 0; | |
2367 | ||
1aa8f0cb TL |
2368 | bus = of_find_node_by_name(NULL, "ocp"); |
2369 | if (!bus) | |
2370 | return -ENODEV; | |
5e863c56 | 2371 | |
1aa8f0cb TL |
2372 | r = of_dev_hwmod_lookup(bus, oh, &index, &np); |
2373 | if (r) | |
2374 | pr_debug("omap_hwmod: %s missing dt data\n", oh->name); | |
2375 | else if (np && index) | |
6e771379 RH |
2376 | pr_warn("omap_hwmod: %s using broken dt data from %pOFn\n", |
2377 | oh->name, np); | |
f92d9597 | 2378 | |
9a258afa RQ |
2379 | r = _init_mpu_rt_base(oh, NULL, index, np); |
2380 | if (r < 0) { | |
2381 | WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n", | |
2382 | oh->name); | |
2383 | return 0; | |
6423d6df | 2384 | } |
381d033a | 2385 | |
70f05be3 | 2386 | r = _init_clocks(oh, np); |
c48cd659 | 2387 | if (r < 0) { |
381d033a PW |
2388 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); |
2389 | return -EINVAL; | |
2390 | } | |
2391 | ||
3d36ad7e | 2392 | if (np) { |
f92d9597 RN |
2393 | if (of_find_property(np, "ti,no-reset-on-init", NULL)) |
2394 | oh->flags |= HWMOD_INIT_NO_RESET; | |
2395 | if (of_find_property(np, "ti,no-idle-on-init", NULL)) | |
2396 | oh->flags |= HWMOD_INIT_NO_IDLE; | |
2e18f5a1 LV |
2397 | if (of_find_property(np, "ti,no-idle", NULL)) |
2398 | oh->flags |= HWMOD_NO_IDLE; | |
3d36ad7e | 2399 | } |
f92d9597 | 2400 | |
381d033a PW |
2401 | oh->_state = _HWMOD_STATE_INITIALIZED; |
2402 | ||
2403 | return 0; | |
2404 | } | |
2405 | ||
63c85238 | 2406 | /** |
64813c3f | 2407 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2408 | * @oh: struct omap_hwmod * |
2409 | * | |
64813c3f PW |
2410 | * Set up the module's interface clocks. XXX This function is still mostly |
2411 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2412 | * the clock code. No return value. | |
63c85238 | 2413 | */ |
64813c3f | 2414 | static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2415 | { |
5d95dde7 | 2416 | struct omap_hwmod_ocp_if *os; |
b8e1bddc | 2417 | |
381d033a | 2418 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2419 | return; |
48d54f3f | 2420 | |
b8e1bddc | 2421 | list_for_each_entry(os, &oh->slave_ports, node) { |
5d95dde7 | 2422 | if (!os->_clk) |
64813c3f | 2423 | continue; |
63c85238 | 2424 | |
64813c3f PW |
2425 | if (os->flags & OCPIF_SWSUP_IDLE) { |
2426 | /* XXX omap_iclk_deny_idle(c); */ | |
2427 | } else { | |
2428 | /* XXX omap_iclk_allow_idle(c); */ | |
5d95dde7 | 2429 | clk_enable(os->_clk); |
63c85238 PW |
2430 | } |
2431 | } | |
2432 | ||
64813c3f PW |
2433 | return; |
2434 | } | |
2435 | ||
2436 | /** | |
2437 | * _setup_reset - reset an IP block during the setup process | |
2438 | * @oh: struct omap_hwmod * | |
2439 | * | |
2440 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2441 | * process. The IP block is first enabled so it can be successfully | |
2442 | * reset. Returns 0 upon success or a negative error code upon | |
2443 | * failure. | |
2444 | */ | |
2445 | static int __init _setup_reset(struct omap_hwmod *oh) | |
2446 | { | |
2447 | int r; | |
2448 | ||
2449 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2450 | return -EINVAL; | |
63c85238 | 2451 | |
5fb3d522 PW |
2452 | if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK) |
2453 | return -EPERM; | |
2454 | ||
747834ab PW |
2455 | if (oh->rst_lines_cnt == 0) { |
2456 | r = _enable(oh); | |
2457 | if (r) { | |
3d0cb73e JP |
2458 | pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n", |
2459 | oh->name, oh->_state); | |
747834ab PW |
2460 | return -EINVAL; |
2461 | } | |
9a23dfe1 | 2462 | } |
63c85238 | 2463 | |
2800852a | 2464 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2465 | r = _reset(oh); |
2466 | ||
2467 | return r; | |
2468 | } | |
2469 | ||
2470 | /** | |
2471 | * _setup_postsetup - transition to the appropriate state after _setup | |
2472 | * @oh: struct omap_hwmod * | |
2473 | * | |
2474 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2475 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2476 | * this function is called at the end of _setup().) The postsetup | |
2477 | * state for an IP block can be changed by calling | |
2478 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2479 | * before one of the omap_hwmod_setup*() functions are called for the | |
2480 | * IP block. | |
2481 | * | |
2482 | * The IP block stays in this state until a PM runtime-based driver is | |
2483 | * loaded for that IP block. A post-setup state of IDLE is | |
2484 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2485 | * drivers, since those drivers are able to enable the IP block. A | |
2486 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2487 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2488 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2489 | * included, since the WDTIMER starts running on reset and will reset | |
2490 | * the MPU if left active. | |
2491 | * | |
2492 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2493 | * drivers have been converted to use PM runtime, and all of the IP | |
2494 | * block data and interconnect data is available to the hwmod code, it | |
2495 | * should be possible to replace this mechanism with a "lazy reset" | |
2496 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2497 | * when the driver first probes, then all remaining IP blocks without | |
2498 | * drivers are either shut down or enabled after the drivers have | |
2499 | * loaded. However, this cannot take place until the above | |
2500 | * preconditions have been met, since otherwise the late reset code | |
2501 | * has no way of knowing which IP blocks are in use by drivers, and | |
2502 | * which ones are unused. | |
2503 | * | |
2504 | * No return value. | |
2505 | */ | |
2506 | static void __init _setup_postsetup(struct omap_hwmod *oh) | |
2507 | { | |
2508 | u8 postsetup_state; | |
2509 | ||
2510 | if (oh->rst_lines_cnt > 0) | |
2511 | return; | |
76e5589e | 2512 | |
2092e5cc PW |
2513 | postsetup_state = oh->_postsetup_state; |
2514 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2515 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2516 | ||
2517 | /* | |
2518 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2519 | * it should be set by the core code as a runtime flag during startup | |
2520 | */ | |
2e18f5a1 | 2521 | if ((oh->flags & (HWMOD_INIT_NO_IDLE | HWMOD_NO_IDLE)) && |
aacf0941 RN |
2522 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2523 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2524 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2525 | } |
2092e5cc PW |
2526 | |
2527 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2528 | _idle(oh); |
2092e5cc PW |
2529 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2530 | _shutdown(oh); | |
2531 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2532 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2533 | oh->name, postsetup_state); | |
63c85238 | 2534 | |
64813c3f PW |
2535 | return; |
2536 | } | |
2537 | ||
2538 | /** | |
2539 | * _setup - prepare IP block hardware for use | |
2540 | * @oh: struct omap_hwmod * | |
2541 | * @n: (unused, pass NULL) | |
2542 | * | |
2543 | * Configure the IP block represented by @oh. This may include | |
2544 | * enabling the IP block, resetting it, and placing it into a | |
2545 | * post-setup state, depending on the type of IP block and applicable | |
2546 | * flags. IP blocks are reset to prevent any previous configuration | |
2547 | * by the bootloader or previous operating system from interfering | |
2548 | * with power management or other parts of the system. The reset can | |
2549 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2550 | * two phases for hwmod initialization. Code called here generally | |
2551 | * affects the IP block hardware, or system integration hardware | |
2552 | * associated with the IP block. Returns 0. | |
2553 | */ | |
8c879705 | 2554 | static int _setup(struct omap_hwmod *oh, void *data) |
64813c3f PW |
2555 | { |
2556 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2557 | return 0; | |
2558 | ||
f22d2545 TV |
2559 | if (oh->parent_hwmod) { |
2560 | int r; | |
2561 | ||
2562 | r = _enable(oh->parent_hwmod); | |
2563 | WARN(r, "hwmod: %s: setup: failed to enable parent hwmod %s\n", | |
2564 | oh->name, oh->parent_hwmod->name); | |
2565 | } | |
2566 | ||
64813c3f PW |
2567 | _setup_iclk_autoidle(oh); |
2568 | ||
2569 | if (!_setup_reset(oh)) | |
2570 | _setup_postsetup(oh); | |
2571 | ||
f22d2545 TV |
2572 | if (oh->parent_hwmod) { |
2573 | u8 postsetup_state; | |
2574 | ||
2575 | postsetup_state = oh->parent_hwmod->_postsetup_state; | |
2576 | ||
2577 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
2578 | _idle(oh->parent_hwmod); | |
2579 | else if (postsetup_state == _HWMOD_STATE_DISABLED) | |
2580 | _shutdown(oh->parent_hwmod); | |
2581 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2582 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2583 | oh->parent_hwmod->name, postsetup_state); | |
2584 | } | |
2585 | ||
63c85238 PW |
2586 | return 0; |
2587 | } | |
2588 | ||
63c85238 | 2589 | /** |
0102b627 | 2590 | * _register - register a struct omap_hwmod |
63c85238 PW |
2591 | * @oh: struct omap_hwmod * |
2592 | * | |
43b40992 PW |
2593 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2594 | * already has been registered by the same name; -EINVAL if the | |
2595 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2596 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2597 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2598 | * success. | |
63c85238 PW |
2599 | * |
2600 | * XXX The data should be copied into bootmem, so the original data | |
2601 | * should be marked __initdata and freed after init. This would allow | |
2602 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2603 | * that the copy process would be relatively complex due to the large number | |
2604 | * of substructures. | |
2605 | */ | |
01592df9 | 2606 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2607 | { |
43b40992 PW |
2608 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2609 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2610 | return -EINVAL; |
2611 | ||
63c85238 PW |
2612 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2613 | ||
ce35b244 BC |
2614 | if (_lookup(oh->name)) |
2615 | return -EEXIST; | |
63c85238 | 2616 | |
63c85238 PW |
2617 | list_add_tail(&oh->node, &omap_hwmod_list); |
2618 | ||
2221b5cd | 2619 | INIT_LIST_HEAD(&oh->slave_ports); |
dc6d1cda | 2620 | spin_lock_init(&oh->_lock); |
69317952 | 2621 | lockdep_set_class(&oh->_lock, &oh->hwmod_key); |
2092e5cc | 2622 | |
63c85238 PW |
2623 | oh->_state = _HWMOD_STATE_REGISTERED; |
2624 | ||
569edd70 PW |
2625 | /* |
2626 | * XXX Rather than doing a strcmp(), this should test a flag | |
2627 | * set in the hwmod data, inserted by the autogenerator code. | |
2628 | */ | |
2629 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2630 | mpu_oh = oh; | |
63c85238 | 2631 | |
569edd70 | 2632 | return 0; |
63c85238 PW |
2633 | } |
2634 | ||
2221b5cd PW |
2635 | /** |
2636 | * _add_link - add an interconnect between two IP blocks | |
2637 | * @oi: pointer to a struct omap_hwmod_ocp_if record | |
2638 | * | |
a1e31235 | 2639 | * Add struct omap_hwmod_link records connecting the slave IP block |
2221b5cd PW |
2640 | * specified in @oi->slave to @oi. This code is assumed to run before |
2641 | * preemption or SMP has been enabled, thus avoiding the need for | |
2642 | * locking in this code. Changes to this assumption will require | |
2643 | * additional locking. Returns 0. | |
2644 | */ | |
2645 | static int __init _add_link(struct omap_hwmod_ocp_if *oi) | |
2646 | { | |
2221b5cd PW |
2647 | pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, |
2648 | oi->slave->name); | |
2649 | ||
a1e31235 | 2650 | list_add(&oi->node, &oi->slave->slave_ports); |
2221b5cd PW |
2651 | oi->slave->slaves_cnt++; |
2652 | ||
2653 | return 0; | |
2654 | } | |
2655 | ||
2656 | /** | |
2657 | * _register_link - register a struct omap_hwmod_ocp_if | |
2658 | * @oi: struct omap_hwmod_ocp_if * | |
2659 | * | |
2660 | * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it | |
2661 | * has already been registered; -EINVAL if @oi is NULL or if the | |
2662 | * record pointed to by @oi is missing required fields; or 0 upon | |
2663 | * success. | |
2664 | * | |
2665 | * XXX The data should be copied into bootmem, so the original data | |
2666 | * should be marked __initdata and freed after init. This would allow | |
2667 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. | |
2668 | */ | |
2669 | static int __init _register_link(struct omap_hwmod_ocp_if *oi) | |
2670 | { | |
2671 | if (!oi || !oi->master || !oi->slave || !oi->user) | |
2672 | return -EINVAL; | |
2673 | ||
2674 | if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) | |
2675 | return -EEXIST; | |
2676 | ||
2677 | pr_debug("omap_hwmod: registering link from %s to %s\n", | |
2678 | oi->master->name, oi->slave->name); | |
2679 | ||
2680 | /* | |
2681 | * Register the connected hwmods, if they haven't been | |
2682 | * registered already | |
2683 | */ | |
2684 | if (oi->master->_state != _HWMOD_STATE_REGISTERED) | |
2685 | _register(oi->master); | |
2686 | ||
2687 | if (oi->slave->_state != _HWMOD_STATE_REGISTERED) | |
2688 | _register(oi->slave); | |
2689 | ||
2690 | _add_link(oi); | |
2691 | ||
2692 | oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; | |
2693 | ||
2694 | return 0; | |
2695 | } | |
2696 | ||
8f6aa8ee KH |
2697 | /* Static functions intended only for use in soc_ops field function pointers */ |
2698 | ||
2699 | /** | |
9002e921 | 2700 | * _omap2xxx_3xxx_wait_target_ready - wait for a module to leave slave idle |
8f6aa8ee KH |
2701 | * @oh: struct omap_hwmod * |
2702 | * | |
2703 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2704 | * does not have an IDLEST bit or if the module successfully leaves | |
2705 | * slave idle; otherwise, pass along the return value of the | |
2706 | * appropriate *_cm*_wait_module_ready() function. | |
2707 | */ | |
9002e921 | 2708 | static int _omap2xxx_3xxx_wait_target_ready(struct omap_hwmod *oh) |
8f6aa8ee KH |
2709 | { |
2710 | if (!oh) | |
2711 | return -EINVAL; | |
2712 | ||
2713 | if (oh->flags & HWMOD_NO_IDLEST) | |
2714 | return 0; | |
2715 | ||
2716 | if (!_find_mpu_rt_port(oh)) | |
2717 | return 0; | |
2718 | ||
2719 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2720 | ||
021b6ff0 TK |
2721 | return omap_cm_wait_module_ready(0, oh->prcm.omap2.module_offs, |
2722 | oh->prcm.omap2.idlest_reg_id, | |
2723 | oh->prcm.omap2.idlest_idle_bit); | |
8f6aa8ee KH |
2724 | } |
2725 | ||
2726 | /** | |
2727 | * _omap4_wait_target_ready - wait for a module to leave slave idle | |
2728 | * @oh: struct omap_hwmod * | |
2729 | * | |
2730 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2731 | * does not have an IDLEST bit or if the module successfully leaves | |
2732 | * slave idle; otherwise, pass along the return value of the | |
2733 | * appropriate *_cm*_wait_module_ready() function. | |
2734 | */ | |
2735 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | |
2736 | { | |
2b026d13 | 2737 | if (!oh) |
8f6aa8ee KH |
2738 | return -EINVAL; |
2739 | ||
2b026d13 | 2740 | if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) |
8f6aa8ee KH |
2741 | return 0; |
2742 | ||
2743 | if (!_find_mpu_rt_port(oh)) | |
2744 | return 0; | |
2745 | ||
8823ddf2 TL |
2746 | if (_omap4_clkctrl_managed_by_clkfwk(oh)) |
2747 | return 0; | |
2748 | ||
2749 | if (!_omap4_has_clkctrl_clock(oh)) | |
428929c7 DG |
2750 | return 0; |
2751 | ||
8f6aa8ee KH |
2752 | /* XXX check module SIDLEMODE, hardreset status */ |
2753 | ||
021b6ff0 TK |
2754 | return omap_cm_wait_module_ready(oh->clkdm->prcm_partition, |
2755 | oh->clkdm->cm_inst, | |
2756 | oh->prcm.omap4.clkctrl_offs, 0); | |
1688bf19 VH |
2757 | } |
2758 | ||
b8249cf2 KH |
2759 | /** |
2760 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2761 | * @oh: struct omap_hwmod * to assert hardreset | |
2762 | * @ohri: hardreset line data | |
2763 | * | |
2764 | * Call omap2_prm_assert_hardreset() with parameters extracted from | |
2765 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2766 | * use as an soc_ops function pointer. Passes along the return value | |
2767 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | |
2768 | * for removal when the PRM code is moved into drivers/. | |
2769 | */ | |
2770 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | |
2771 | struct omap_hwmod_rst_info *ohri) | |
2772 | { | |
efd44dc3 TK |
2773 | return omap_prm_assert_hardreset(ohri->rst_shift, 0, |
2774 | oh->prcm.omap2.module_offs, 0); | |
b8249cf2 KH |
2775 | } |
2776 | ||
2777 | /** | |
2778 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2779 | * @oh: struct omap_hwmod * to deassert hardreset | |
2780 | * @ohri: hardreset line data | |
2781 | * | |
2782 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | |
2783 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2784 | * use as an soc_ops function pointer. Passes along the return value | |
2785 | * from omap2_prm_deassert_hardreset(). XXX This function is | |
2786 | * scheduled for removal when the PRM code is moved into drivers/. | |
2787 | */ | |
2788 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | |
2789 | struct omap_hwmod_rst_info *ohri) | |
2790 | { | |
37fb59d7 TK |
2791 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0, |
2792 | oh->prcm.omap2.module_offs, 0, 0); | |
b8249cf2 KH |
2793 | } |
2794 | ||
2795 | /** | |
2796 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | |
2797 | * @oh: struct omap_hwmod * to test hardreset | |
2798 | * @ohri: hardreset line data | |
2799 | * | |
2800 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | |
2801 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2802 | * intended for use as an soc_ops function pointer. Passes along the | |
2803 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | |
2804 | * function is scheduled for removal when the PRM code is moved into | |
2805 | * drivers/. | |
2806 | */ | |
2807 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | |
2808 | struct omap_hwmod_rst_info *ohri) | |
2809 | { | |
1bc28b34 TK |
2810 | return omap_prm_is_hardreset_asserted(ohri->st_shift, 0, |
2811 | oh->prcm.omap2.module_offs, 0); | |
b8249cf2 KH |
2812 | } |
2813 | ||
2814 | /** | |
2815 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2816 | * @oh: struct omap_hwmod * to assert hardreset | |
2817 | * @ohri: hardreset line data | |
2818 | * | |
2819 | * Call omap4_prminst_assert_hardreset() with parameters extracted | |
2820 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2821 | * intended for use as an soc_ops function pointer. Passes along the | |
2822 | * return value from omap4_prminst_assert_hardreset(). XXX This | |
2823 | * function is scheduled for removal when the PRM code is moved into | |
2824 | * drivers/. | |
2825 | */ | |
2826 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | |
2827 | struct omap_hwmod_rst_info *ohri) | |
b8249cf2 | 2828 | { |
07b3a139 PW |
2829 | if (!oh->clkdm) |
2830 | return -EINVAL; | |
2831 | ||
efd44dc3 TK |
2832 | return omap_prm_assert_hardreset(ohri->rst_shift, |
2833 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2834 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2835 | oh->prcm.omap4.rstctrl_offs); | |
b8249cf2 KH |
2836 | } |
2837 | ||
2838 | /** | |
2839 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2840 | * @oh: struct omap_hwmod * to deassert hardreset | |
2841 | * @ohri: hardreset line data | |
2842 | * | |
2843 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | |
2844 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2845 | * intended for use as an soc_ops function pointer. Passes along the | |
2846 | * return value from omap4_prminst_deassert_hardreset(). XXX This | |
2847 | * function is scheduled for removal when the PRM code is moved into | |
2848 | * drivers/. | |
2849 | */ | |
2850 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |
2851 | struct omap_hwmod_rst_info *ohri) | |
2852 | { | |
07b3a139 PW |
2853 | if (!oh->clkdm) |
2854 | return -EINVAL; | |
2855 | ||
b8249cf2 KH |
2856 | if (ohri->st_shift) |
2857 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2858 | oh->name, ohri->name); | |
4ebf5b28 | 2859 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift, |
37fb59d7 TK |
2860 | oh->clkdm->pwrdm.ptr->prcm_partition, |
2861 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
4ebf5b28 TK |
2862 | oh->prcm.omap4.rstctrl_offs, |
2863 | oh->prcm.omap4.rstctrl_offs + | |
2864 | OMAP4_RST_CTRL_ST_OFFSET); | |
b8249cf2 KH |
2865 | } |
2866 | ||
2867 | /** | |
2868 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | |
2869 | * @oh: struct omap_hwmod * to test hardreset | |
2870 | * @ohri: hardreset line data | |
2871 | * | |
2872 | * Call omap4_prminst_is_hardreset_asserted() with parameters | |
2873 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2874 | * Only intended for use as an soc_ops function pointer. Passes along | |
2875 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | |
2876 | * This function is scheduled for removal when the PRM code is moved | |
2877 | * into drivers/. | |
2878 | */ | |
2879 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |
2880 | struct omap_hwmod_rst_info *ohri) | |
2881 | { | |
07b3a139 PW |
2882 | if (!oh->clkdm) |
2883 | return -EINVAL; | |
2884 | ||
1bc28b34 TK |
2885 | return omap_prm_is_hardreset_asserted(ohri->rst_shift, |
2886 | oh->clkdm->pwrdm.ptr-> | |
2887 | prcm_partition, | |
2888 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2889 | oh->prcm.omap4.rstctrl_offs); | |
b8249cf2 KH |
2890 | } |
2891 | ||
9fabc1a2 TK |
2892 | /** |
2893 | * _omap4_disable_direct_prcm - disable direct PRCM control for hwmod | |
2894 | * @oh: struct omap_hwmod * to disable control for | |
2895 | * | |
2896 | * Disables direct PRCM clkctrl done by hwmod core. Instead, the hwmod | |
2897 | * will be using its main_clk to enable/disable the module. Returns | |
2898 | * 0 if successful. | |
2899 | */ | |
2900 | static int _omap4_disable_direct_prcm(struct omap_hwmod *oh) | |
2901 | { | |
2902 | if (!oh) | |
2903 | return -EINVAL; | |
2904 | ||
8823ddf2 | 2905 | oh->prcm.omap4.flags |= HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK; |
9fabc1a2 TK |
2906 | |
2907 | return 0; | |
2908 | } | |
2909 | ||
1688bf19 VH |
2910 | /** |
2911 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
2912 | * @oh: struct omap_hwmod * to deassert hardreset | |
2913 | * @ohri: hardreset line data | |
2914 | * | |
2915 | * Call am33xx_prminst_deassert_hardreset() with parameters extracted | |
2916 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2917 | * intended for use as an soc_ops function pointer. Passes along the | |
2918 | * return value from am33xx_prminst_deassert_hardreset(). XXX This | |
2919 | * function is scheduled for removal when the PRM code is moved into | |
2920 | * drivers/. | |
2921 | */ | |
2922 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, | |
2923 | struct omap_hwmod_rst_info *ohri) | |
2924 | { | |
a5bf00cd TK |
2925 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, |
2926 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
37fb59d7 TK |
2927 | oh->clkdm->pwrdm.ptr->prcm_offs, |
2928 | oh->prcm.omap4.rstctrl_offs, | |
2929 | oh->prcm.omap4.rstst_offs); | |
1688bf19 VH |
2930 | } |
2931 | ||
0102b627 BC |
2932 | /* Public functions */ |
2933 | ||
2934 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
2935 | { | |
2936 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 2937 | return readw_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 | 2938 | else |
edfaf05c | 2939 | return readl_relaxed(oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
2940 | } |
2941 | ||
2942 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
2943 | { | |
2944 | if (oh->flags & HWMOD_16BIT_REG) | |
edfaf05c | 2945 | writew_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 | 2946 | else |
edfaf05c | 2947 | writel_relaxed(v, oh->_mpu_rt_va + reg_offs); |
0102b627 BC |
2948 | } |
2949 | ||
6d3c55fd A |
2950 | /** |
2951 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
2952 | * @oh: struct omap_hwmod * | |
2953 | * | |
2954 | * This is a public function exposed to drivers. Some drivers may need to do | |
2955 | * some settings before and after resetting the device. Those drivers after | |
2956 | * doing the necessary settings could use this function to start a reset by | |
2957 | * setting the SYSCONFIG.SOFTRESET bit. | |
2958 | */ | |
2959 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
2960 | { | |
3c55c1ba PW |
2961 | u32 v; |
2962 | int ret; | |
2963 | ||
2964 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
2965 | return -EINVAL; |
2966 | ||
3c55c1ba PW |
2967 | v = oh->_sysc_cache; |
2968 | ret = _set_softreset(oh, &v); | |
2969 | if (ret) | |
2970 | goto error; | |
2971 | _write_sysconfig(v, oh); | |
2972 | ||
313a76ee RQ |
2973 | ret = _clear_softreset(oh, &v); |
2974 | if (ret) | |
2975 | goto error; | |
2976 | _write_sysconfig(v, oh); | |
2977 | ||
3c55c1ba PW |
2978 | error: |
2979 | return ret; | |
6d3c55fd A |
2980 | } |
2981 | ||
63c85238 PW |
2982 | /** |
2983 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
2984 | * @name: name of the omap_hwmod to look up | |
2985 | * | |
2986 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
2987 | * struct omap_hwmod *, or NULL upon error. | |
2988 | */ | |
2989 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
2990 | { | |
2991 | struct omap_hwmod *oh; | |
2992 | ||
2993 | if (!name) | |
2994 | return NULL; | |
2995 | ||
63c85238 | 2996 | oh = _lookup(name); |
63c85238 PW |
2997 | |
2998 | return oh; | |
2999 | } | |
3000 | ||
3001 | /** | |
3002 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
3003 | * @fn: pointer to a callback function | |
97d60162 | 3004 | * @data: void * data to pass to callback function |
63c85238 PW |
3005 | * |
3006 | * Call @fn for each registered omap_hwmod, passing @data to each | |
3007 | * function. @fn must return 0 for success or any other value for | |
3008 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
3009 | * will stop and the non-zero return value will be passed to the | |
3010 | * caller of omap_hwmod_for_each(). @fn is called with | |
3011 | * omap_hwmod_for_each() held. | |
3012 | */ | |
97d60162 PW |
3013 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
3014 | void *data) | |
63c85238 PW |
3015 | { |
3016 | struct omap_hwmod *temp_oh; | |
30ebad9d | 3017 | int ret = 0; |
63c85238 PW |
3018 | |
3019 | if (!fn) | |
3020 | return -EINVAL; | |
3021 | ||
63c85238 | 3022 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 3023 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
3024 | if (ret) |
3025 | break; | |
3026 | } | |
63c85238 PW |
3027 | |
3028 | return ret; | |
3029 | } | |
3030 | ||
2221b5cd PW |
3031 | /** |
3032 | * omap_hwmod_register_links - register an array of hwmod links | |
3033 | * @ois: pointer to an array of omap_hwmod_ocp_if to register | |
3034 | * | |
3035 | * Intended to be called early in boot before the clock framework is | |
3036 | * initialized. If @ois is not null, will register all omap_hwmods | |
9ebfd285 KH |
3037 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
3038 | * omap_hwmod_init() hasn't been called before calling this function, | |
3039 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | |
3040 | * success. | |
2221b5cd PW |
3041 | */ |
3042 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | |
3043 | { | |
3044 | int r, i; | |
3045 | ||
9ebfd285 KH |
3046 | if (!inited) |
3047 | return -EINVAL; | |
3048 | ||
2221b5cd PW |
3049 | if (!ois) |
3050 | return 0; | |
3051 | ||
f7f7a29b RN |
3052 | if (ois[0] == NULL) /* Empty list */ |
3053 | return 0; | |
3054 | ||
2221b5cd PW |
3055 | i = 0; |
3056 | do { | |
3057 | r = _register_link(ois[i]); | |
3058 | WARN(r && r != -EEXIST, | |
3059 | "omap_hwmod: _register_link(%s -> %s) returned %d\n", | |
3060 | ois[i]->master->name, ois[i]->slave->name, r); | |
3061 | } while (ois[++i]); | |
3062 | ||
3063 | return 0; | |
3064 | } | |
3065 | ||
381d033a PW |
3066 | /** |
3067 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
3068 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
3069 | * | |
3070 | * If the hwmod data corresponding to the MPU subsystem IP block | |
3071 | * hasn't been initialized and set up yet, do so now. This must be | |
3072 | * done first since sleep dependencies may be added from other hwmods | |
3073 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
3074 | * return value. | |
63c85238 | 3075 | */ |
381d033a | 3076 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 3077 | { |
381d033a PW |
3078 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
3079 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
3080 | __func__, MPU_INITIATOR_NAME); | |
3081 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
3082 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
3083 | } |
3084 | ||
63c85238 | 3085 | /** |
a2debdbd PW |
3086 | * omap_hwmod_setup_one - set up a single hwmod |
3087 | * @oh_name: const char * name of the already-registered hwmod to set up | |
3088 | * | |
381d033a PW |
3089 | * Initialize and set up a single hwmod. Intended to be used for a |
3090 | * small number of early devices, such as the timer IP blocks used for | |
3091 | * the scheduler clock. Must be called after omap2_clk_init(). | |
3092 | * Resolves the struct clk names to struct clk pointers for each | |
3093 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
3094 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
3095 | */ |
3096 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
3097 | { |
3098 | struct omap_hwmod *oh; | |
63c85238 | 3099 | |
a2debdbd PW |
3100 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
3101 | ||
a2debdbd PW |
3102 | oh = _lookup(oh_name); |
3103 | if (!oh) { | |
3104 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
3105 | return -EINVAL; | |
3106 | } | |
63c85238 | 3107 | |
381d033a | 3108 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 3109 | |
381d033a | 3110 | _init(oh, NULL); |
a2debdbd PW |
3111 | _setup(oh, NULL); |
3112 | ||
63c85238 PW |
3113 | return 0; |
3114 | } | |
3115 | ||
a8844306 TL |
3116 | static void omap_hwmod_check_one(struct device *dev, |
3117 | const char *name, s8 v1, u8 v2) | |
3118 | { | |
3119 | if (v1 < 0) | |
3120 | return; | |
3121 | ||
3122 | if (v1 != v2) | |
3123 | dev_warn(dev, "%s %d != %d\n", name, v1, v2); | |
3124 | } | |
3125 | ||
3126 | /** | |
3127 | * omap_hwmod_check_sysc - check sysc against platform sysc | |
3128 | * @dev: struct device | |
3129 | * @data: module data | |
3130 | * @sysc_fields: new sysc configuration | |
3131 | */ | |
3132 | static int omap_hwmod_check_sysc(struct device *dev, | |
3133 | const struct ti_sysc_module_data *data, | |
3134 | struct sysc_regbits *sysc_fields) | |
3135 | { | |
3136 | const struct sysc_regbits *regbits = data->cap->regbits; | |
3137 | ||
3138 | omap_hwmod_check_one(dev, "dmadisable_shift", | |
3139 | regbits->dmadisable_shift, | |
3140 | sysc_fields->dmadisable_shift); | |
3141 | omap_hwmod_check_one(dev, "midle_shift", | |
3142 | regbits->midle_shift, | |
3143 | sysc_fields->midle_shift); | |
3144 | omap_hwmod_check_one(dev, "sidle_shift", | |
3145 | regbits->sidle_shift, | |
3146 | sysc_fields->sidle_shift); | |
3147 | omap_hwmod_check_one(dev, "clkact_shift", | |
3148 | regbits->clkact_shift, | |
3149 | sysc_fields->clkact_shift); | |
3150 | omap_hwmod_check_one(dev, "enwkup_shift", | |
3151 | regbits->enwkup_shift, | |
3152 | sysc_fields->enwkup_shift); | |
3153 | omap_hwmod_check_one(dev, "srst_shift", | |
3154 | regbits->srst_shift, | |
3155 | sysc_fields->srst_shift); | |
3156 | omap_hwmod_check_one(dev, "autoidle_shift", | |
3157 | regbits->autoidle_shift, | |
3158 | sysc_fields->autoidle_shift); | |
3159 | ||
3160 | return 0; | |
3161 | } | |
3162 | ||
8c879705 TL |
3163 | /** |
3164 | * omap_hwmod_init_regbits - init sysconfig specific register bits | |
3165 | * @dev: struct device | |
3166 | * @data: module data | |
3167 | * @sysc_fields: new sysc configuration | |
3168 | */ | |
3169 | static int omap_hwmod_init_regbits(struct device *dev, | |
3170 | const struct ti_sysc_module_data *data, | |
3171 | struct sysc_regbits **sysc_fields) | |
3172 | { | |
3173 | *sysc_fields = NULL; | |
3174 | ||
3175 | switch (data->cap->type) { | |
3176 | case TI_SYSC_OMAP2: | |
3177 | case TI_SYSC_OMAP2_TIMER: | |
3178 | *sysc_fields = &omap_hwmod_sysc_type1; | |
3179 | break; | |
3180 | case TI_SYSC_OMAP3_SHAM: | |
3181 | *sysc_fields = &omap3_sham_sysc_fields; | |
3182 | break; | |
3183 | case TI_SYSC_OMAP3_AES: | |
3184 | *sysc_fields = &omap3xxx_aes_sysc_fields; | |
3185 | break; | |
3186 | case TI_SYSC_OMAP4: | |
3187 | case TI_SYSC_OMAP4_TIMER: | |
3188 | *sysc_fields = &omap_hwmod_sysc_type2; | |
3189 | break; | |
3190 | case TI_SYSC_OMAP4_SIMPLE: | |
3191 | *sysc_fields = &omap_hwmod_sysc_type3; | |
3192 | break; | |
3193 | case TI_SYSC_OMAP34XX_SR: | |
3194 | *sysc_fields = &omap34xx_sr_sysc_fields; | |
3195 | break; | |
3196 | case TI_SYSC_OMAP36XX_SR: | |
3197 | *sysc_fields = &omap36xx_sr_sysc_fields; | |
3198 | break; | |
3199 | case TI_SYSC_OMAP4_SR: | |
3200 | *sysc_fields = &omap36xx_sr_sysc_fields; | |
3201 | break; | |
3202 | case TI_SYSC_OMAP4_MCASP: | |
3203 | *sysc_fields = &omap_hwmod_sysc_type_mcasp; | |
3204 | break; | |
3205 | case TI_SYSC_OMAP4_USB_HOST_FS: | |
3206 | *sysc_fields = &omap_hwmod_sysc_type_usb_host_fs; | |
3207 | break; | |
3208 | default: | |
3209 | return -EINVAL; | |
3210 | } | |
3211 | ||
a8844306 | 3212 | return omap_hwmod_check_sysc(dev, data, *sysc_fields); |
8c879705 TL |
3213 | } |
3214 | ||
3215 | /** | |
3216 | * omap_hwmod_init_reg_offs - initialize sysconfig register offsets | |
3217 | * @dev: struct device | |
3218 | * @data: module data | |
3219 | * @rev_offs: revision register offset | |
3220 | * @sysc_offs: sysc register offset | |
3221 | * @syss_offs: syss register offset | |
3222 | */ | |
3223 | int omap_hwmod_init_reg_offs(struct device *dev, | |
3224 | const struct ti_sysc_module_data *data, | |
103fd8e7 | 3225 | s32 *rev_offs, s32 *sysc_offs, s32 *syss_offs) |
8c879705 | 3226 | { |
103fd8e7 | 3227 | *rev_offs = -ENODEV; |
8c879705 TL |
3228 | *sysc_offs = 0; |
3229 | *syss_offs = 0; | |
3230 | ||
103fd8e7 | 3231 | if (data->offsets[SYSC_REVISION] >= 0) |
8c879705 TL |
3232 | *rev_offs = data->offsets[SYSC_REVISION]; |
3233 | ||
103fd8e7 | 3234 | if (data->offsets[SYSC_SYSCONFIG] >= 0) |
8c879705 TL |
3235 | *sysc_offs = data->offsets[SYSC_SYSCONFIG]; |
3236 | ||
103fd8e7 | 3237 | if (data->offsets[SYSC_SYSSTATUS] >= 0) |
8c879705 TL |
3238 | *syss_offs = data->offsets[SYSC_SYSSTATUS]; |
3239 | ||
3240 | return 0; | |
3241 | } | |
3242 | ||
3243 | /** | |
3244 | * omap_hwmod_init_sysc_flags - initialize sysconfig features | |
3245 | * @dev: struct device | |
3246 | * @data: module data | |
3247 | * @sysc_flags: module configuration | |
3248 | */ | |
3249 | int omap_hwmod_init_sysc_flags(struct device *dev, | |
3250 | const struct ti_sysc_module_data *data, | |
3251 | u32 *sysc_flags) | |
3252 | { | |
3253 | *sysc_flags = 0; | |
3254 | ||
3255 | switch (data->cap->type) { | |
3256 | case TI_SYSC_OMAP2: | |
3257 | case TI_SYSC_OMAP2_TIMER: | |
3258 | /* See SYSC_OMAP2_* in include/dt-bindings/bus/ti-sysc.h */ | |
3259 | if (data->cfg->sysc_val & SYSC_OMAP2_CLOCKACTIVITY) | |
3260 | *sysc_flags |= SYSC_HAS_CLOCKACTIVITY; | |
3261 | if (data->cfg->sysc_val & SYSC_OMAP2_EMUFREE) | |
3262 | *sysc_flags |= SYSC_HAS_EMUFREE; | |
3263 | if (data->cfg->sysc_val & SYSC_OMAP2_ENAWAKEUP) | |
3264 | *sysc_flags |= SYSC_HAS_ENAWAKEUP; | |
3265 | if (data->cfg->sysc_val & SYSC_OMAP2_SOFTRESET) | |
3266 | *sysc_flags |= SYSC_HAS_SOFTRESET; | |
3267 | if (data->cfg->sysc_val & SYSC_OMAP2_AUTOIDLE) | |
3268 | *sysc_flags |= SYSC_HAS_AUTOIDLE; | |
3269 | break; | |
3270 | case TI_SYSC_OMAP4: | |
3271 | case TI_SYSC_OMAP4_TIMER: | |
3272 | /* See SYSC_OMAP4_* in include/dt-bindings/bus/ti-sysc.h */ | |
3273 | if (data->cfg->sysc_val & SYSC_OMAP4_DMADISABLE) | |
3274 | *sysc_flags |= SYSC_HAS_DMADISABLE; | |
3275 | if (data->cfg->sysc_val & SYSC_OMAP4_FREEEMU) | |
3276 | *sysc_flags |= SYSC_HAS_EMUFREE; | |
3277 | if (data->cfg->sysc_val & SYSC_OMAP4_SOFTRESET) | |
3278 | *sysc_flags |= SYSC_HAS_SOFTRESET; | |
3279 | break; | |
3280 | case TI_SYSC_OMAP34XX_SR: | |
3281 | case TI_SYSC_OMAP36XX_SR: | |
3282 | /* See SYSC_OMAP3_SR_* in include/dt-bindings/bus/ti-sysc.h */ | |
3283 | if (data->cfg->sysc_val & SYSC_OMAP3_SR_ENAWAKEUP) | |
3284 | *sysc_flags |= SYSC_HAS_ENAWAKEUP; | |
3285 | break; | |
3286 | default: | |
3287 | if (data->cap->regbits->emufree_shift >= 0) | |
3288 | *sysc_flags |= SYSC_HAS_EMUFREE; | |
3289 | if (data->cap->regbits->enwkup_shift >= 0) | |
3290 | *sysc_flags |= SYSC_HAS_ENAWAKEUP; | |
3291 | if (data->cap->regbits->srst_shift >= 0) | |
3292 | *sysc_flags |= SYSC_HAS_SOFTRESET; | |
3293 | if (data->cap->regbits->autoidle_shift >= 0) | |
3294 | *sysc_flags |= SYSC_HAS_AUTOIDLE; | |
3295 | break; | |
3296 | } | |
3297 | ||
3298 | if (data->cap->regbits->midle_shift >= 0 && | |
3299 | data->cfg->midlemodes) | |
3300 | *sysc_flags |= SYSC_HAS_MIDLEMODE; | |
3301 | ||
3302 | if (data->cap->regbits->sidle_shift >= 0 && | |
3303 | data->cfg->sidlemodes) | |
3304 | *sysc_flags |= SYSC_HAS_SIDLEMODE; | |
3305 | ||
3306 | if (data->cfg->quirks & SYSC_QUIRK_UNCACHED) | |
3307 | *sysc_flags |= SYSC_NO_CACHE; | |
3308 | if (data->cfg->quirks & SYSC_QUIRK_RESET_STATUS) | |
3309 | *sysc_flags |= SYSC_HAS_RESET_STATUS; | |
3310 | ||
3311 | if (data->cfg->syss_mask & 1) | |
3312 | *sysc_flags |= SYSS_HAS_RESET_STATUS; | |
3313 | ||
3314 | return 0; | |
3315 | } | |
3316 | ||
3317 | /** | |
3318 | * omap_hwmod_init_idlemodes - initialize module idle modes | |
3319 | * @dev: struct device | |
3320 | * @data: module data | |
3321 | * @idlemodes: module supported idle modes | |
3322 | */ | |
3323 | int omap_hwmod_init_idlemodes(struct device *dev, | |
3324 | const struct ti_sysc_module_data *data, | |
3325 | u32 *idlemodes) | |
3326 | { | |
3327 | *idlemodes = 0; | |
3328 | ||
3329 | if (data->cfg->midlemodes & BIT(SYSC_IDLE_FORCE)) | |
3330 | *idlemodes |= MSTANDBY_FORCE; | |
3331 | if (data->cfg->midlemodes & BIT(SYSC_IDLE_NO)) | |
3332 | *idlemodes |= MSTANDBY_NO; | |
3333 | if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART)) | |
3334 | *idlemodes |= MSTANDBY_SMART; | |
3335 | if (data->cfg->midlemodes & BIT(SYSC_IDLE_SMART_WKUP)) | |
3336 | *idlemodes |= MSTANDBY_SMART_WKUP; | |
3337 | ||
3338 | if (data->cfg->sidlemodes & BIT(SYSC_IDLE_FORCE)) | |
3339 | *idlemodes |= SIDLE_FORCE; | |
3340 | if (data->cfg->sidlemodes & BIT(SYSC_IDLE_NO)) | |
3341 | *idlemodes |= SIDLE_NO; | |
3342 | if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART)) | |
3343 | *idlemodes |= SIDLE_SMART; | |
3344 | if (data->cfg->sidlemodes & BIT(SYSC_IDLE_SMART_WKUP)) | |
3345 | *idlemodes |= SIDLE_SMART_WKUP; | |
3346 | ||
3347 | return 0; | |
3348 | } | |
3349 | ||
a8844306 TL |
3350 | /** |
3351 | * omap_hwmod_check_module - check new module against platform data | |
3352 | * @dev: struct device | |
3353 | * @oh: module | |
3354 | * @data: new module data | |
3355 | * @sysc_fields: sysc register bits | |
3356 | * @rev_offs: revision register offset | |
3357 | * @sysc_offs: sysconfig register offset | |
3358 | * @syss_offs: sysstatus register offset | |
3359 | * @sysc_flags: sysc specific flags | |
3360 | * @idlemodes: sysc supported idlemodes | |
3361 | */ | |
3362 | static int omap_hwmod_check_module(struct device *dev, | |
3363 | struct omap_hwmod *oh, | |
3364 | const struct ti_sysc_module_data *data, | |
3365 | struct sysc_regbits *sysc_fields, | |
103fd8e7 TL |
3366 | s32 rev_offs, s32 sysc_offs, |
3367 | s32 syss_offs, u32 sysc_flags, | |
a8844306 TL |
3368 | u32 idlemodes) |
3369 | { | |
3370 | if (!oh->class->sysc) | |
3371 | return -ENODEV; | |
3372 | ||
3373 | if (sysc_fields != oh->class->sysc->sysc_fields) | |
3374 | dev_warn(dev, "sysc_fields %p != %p\n", sysc_fields, | |
3375 | oh->class->sysc->sysc_fields); | |
3376 | ||
3377 | if (rev_offs != oh->class->sysc->rev_offs) | |
3378 | dev_warn(dev, "rev_offs %08x != %08x\n", rev_offs, | |
3379 | oh->class->sysc->rev_offs); | |
3380 | if (sysc_offs != oh->class->sysc->sysc_offs) | |
3381 | dev_warn(dev, "sysc_offs %08x != %08x\n", sysc_offs, | |
3382 | oh->class->sysc->sysc_offs); | |
3383 | if (syss_offs != oh->class->sysc->syss_offs) | |
3384 | dev_warn(dev, "syss_offs %08x != %08x\n", syss_offs, | |
3385 | oh->class->sysc->syss_offs); | |
3386 | ||
3387 | if (sysc_flags != oh->class->sysc->sysc_flags) | |
3388 | dev_warn(dev, "sysc_flags %08x != %08x\n", sysc_flags, | |
3389 | oh->class->sysc->sysc_flags); | |
3390 | ||
3391 | if (idlemodes != oh->class->sysc->idlemodes) | |
3392 | dev_warn(dev, "idlemodes %08x != %08x\n", idlemodes, | |
3393 | oh->class->sysc->idlemodes); | |
3394 | ||
3395 | if (data->cfg->srst_udelay != oh->class->sysc->srst_udelay) | |
3396 | dev_warn(dev, "srst_udelay %i != %i\n", | |
3397 | data->cfg->srst_udelay, | |
3398 | oh->class->sysc->srst_udelay); | |
3399 | ||
3400 | return 0; | |
3401 | } | |
3402 | ||
8c879705 TL |
3403 | /** |
3404 | * omap_hwmod_allocate_module - allocate new module | |
3405 | * @dev: struct device | |
3406 | * @oh: module | |
3407 | * @sysc_fields: sysc register bits | |
3408 | * @rev_offs: revision register offset | |
3409 | * @sysc_offs: sysconfig register offset | |
3410 | * @syss_offs: sysstatus register offset | |
3411 | * @sysc_flags: sysc specific flags | |
3412 | * @idlemodes: sysc supported idlemodes | |
3413 | * | |
3414 | * Note that the allocations here cannot use devm as ti-sysc can rebind. | |
3415 | */ | |
3416 | int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh, | |
3417 | const struct ti_sysc_module_data *data, | |
3418 | struct sysc_regbits *sysc_fields, | |
103fd8e7 | 3419 | s32 rev_offs, s32 sysc_offs, s32 syss_offs, |
8c879705 TL |
3420 | u32 sysc_flags, u32 idlemodes) |
3421 | { | |
3422 | struct omap_hwmod_class_sysconfig *sysc; | |
3423 | struct omap_hwmod_class *class; | |
3424 | void __iomem *regs = NULL; | |
3425 | unsigned long flags; | |
3426 | ||
3427 | sysc = kzalloc(sizeof(*sysc), GFP_KERNEL); | |
3428 | if (!sysc) | |
3429 | return -ENOMEM; | |
3430 | ||
3431 | sysc->sysc_fields = sysc_fields; | |
3432 | sysc->rev_offs = rev_offs; | |
3433 | sysc->sysc_offs = sysc_offs; | |
3434 | sysc->syss_offs = syss_offs; | |
3435 | sysc->sysc_flags = sysc_flags; | |
3436 | sysc->idlemodes = idlemodes; | |
3437 | sysc->srst_udelay = data->cfg->srst_udelay; | |
3438 | ||
3439 | if (!oh->_mpu_rt_va) { | |
3440 | regs = ioremap(data->module_pa, | |
3441 | data->module_size); | |
3442 | if (!regs) | |
3443 | return -ENOMEM; | |
3444 | } | |
3445 | ||
3446 | /* | |
3447 | * We need new oh->class as the other devices in the same class | |
3448 | * may not yet have ioremapped their registers. | |
3449 | */ | |
3450 | class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL); | |
3451 | if (!class) | |
3452 | return -ENOMEM; | |
3453 | ||
3454 | class->sysc = sysc; | |
3455 | ||
3456 | spin_lock_irqsave(&oh->_lock, flags); | |
3457 | if (regs) | |
3458 | oh->_mpu_rt_va = regs; | |
3459 | oh->class = class; | |
3460 | oh->_state = _HWMOD_STATE_INITIALIZED; | |
3461 | _setup(oh, NULL); | |
3462 | spin_unlock_irqrestore(&oh->_lock, flags); | |
3463 | ||
3464 | return 0; | |
3465 | } | |
3466 | ||
3467 | /** | |
3468 | * omap_hwmod_init_module - initialize new module | |
3469 | * @dev: struct device | |
3470 | * @data: module data | |
3471 | * @cookie: cookie for the caller to use for later calls | |
3472 | */ | |
3473 | int omap_hwmod_init_module(struct device *dev, | |
3474 | const struct ti_sysc_module_data *data, | |
3475 | struct ti_sysc_cookie *cookie) | |
3476 | { | |
3477 | struct omap_hwmod *oh; | |
3478 | struct sysc_regbits *sysc_fields; | |
103fd8e7 TL |
3479 | s32 rev_offs, sysc_offs, syss_offs; |
3480 | u32 sysc_flags, idlemodes; | |
8c879705 TL |
3481 | int error; |
3482 | ||
3483 | if (!dev || !data) | |
3484 | return -EINVAL; | |
3485 | ||
3486 | oh = _lookup(data->name); | |
3487 | if (!oh) | |
3488 | return -ENODEV; | |
3489 | ||
3490 | cookie->data = oh; | |
3491 | ||
3492 | error = omap_hwmod_init_regbits(dev, data, &sysc_fields); | |
3493 | if (error) | |
3494 | return error; | |
3495 | ||
3496 | error = omap_hwmod_init_reg_offs(dev, data, &rev_offs, | |
3497 | &sysc_offs, &syss_offs); | |
3498 | if (error) | |
3499 | return error; | |
3500 | ||
3501 | error = omap_hwmod_init_sysc_flags(dev, data, &sysc_flags); | |
3502 | if (error) | |
3503 | return error; | |
3504 | ||
3505 | error = omap_hwmod_init_idlemodes(dev, data, &idlemodes); | |
3506 | if (error) | |
3507 | return error; | |
3508 | ||
3509 | if (data->cfg->quirks & SYSC_QUIRK_NO_IDLE_ON_INIT) | |
3510 | oh->flags |= HWMOD_INIT_NO_IDLE; | |
3511 | if (data->cfg->quirks & SYSC_QUIRK_NO_RESET_ON_INIT) | |
3512 | oh->flags |= HWMOD_INIT_NO_RESET; | |
3513 | ||
a8844306 TL |
3514 | error = omap_hwmod_check_module(dev, oh, data, sysc_fields, |
3515 | rev_offs, sysc_offs, syss_offs, | |
3516 | sysc_flags, idlemodes); | |
3517 | if (!error) | |
3518 | return error; | |
8c879705 TL |
3519 | |
3520 | return omap_hwmod_allocate_module(dev, oh, data, sysc_fields, | |
3521 | rev_offs, sysc_offs, syss_offs, | |
3522 | sysc_flags, idlemodes); | |
3523 | } | |
3524 | ||
8dd6666f LV |
3525 | /** |
3526 | * omap_hwmod_setup_earlycon_flags - set up flags for early console | |
3527 | * | |
3528 | * Enable DEBUG_OMAPUART_FLAGS for uart hwmod that is being used as | |
3529 | * early concole so that hwmod core doesn't reset and keep it in idle | |
3530 | * that specific uart. | |
3531 | */ | |
3532 | #ifdef CONFIG_SERIAL_EARLYCON | |
3533 | static void __init omap_hwmod_setup_earlycon_flags(void) | |
3534 | { | |
3535 | struct device_node *np; | |
3536 | struct omap_hwmod *oh; | |
3537 | const char *uart; | |
3538 | ||
3539 | np = of_find_node_by_path("/chosen"); | |
3540 | if (np) { | |
3541 | uart = of_get_property(np, "stdout-path", NULL); | |
3542 | if (uart) { | |
3543 | np = of_find_node_by_path(uart); | |
3544 | if (np) { | |
3545 | uart = of_get_property(np, "ti,hwmods", NULL); | |
3546 | oh = omap_hwmod_lookup(uart); | |
15618256 TL |
3547 | if (!oh) { |
3548 | uart = of_get_property(np->parent, | |
3549 | "ti,hwmods", | |
3550 | NULL); | |
3551 | oh = omap_hwmod_lookup(uart); | |
3552 | } | |
8dd6666f LV |
3553 | if (oh) |
3554 | oh->flags |= DEBUG_OMAPUART_FLAGS; | |
3555 | } | |
3556 | } | |
3557 | } | |
3558 | } | |
3559 | #endif | |
3560 | ||
63c85238 | 3561 | /** |
381d033a | 3562 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 3563 | * |
381d033a PW |
3564 | * Initialize and set up all IP blocks registered with the hwmod code. |
3565 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
3566 | * names to struct clk pointers for each registered omap_hwmod. Also | |
3567 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 3568 | */ |
550c8092 | 3569 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 3570 | { |
381d033a | 3571 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 3572 | |
381d033a | 3573 | omap_hwmod_for_each(_init, NULL); |
8dd6666f LV |
3574 | #ifdef CONFIG_SERIAL_EARLYCON |
3575 | omap_hwmod_setup_earlycon_flags(); | |
3576 | #endif | |
2092e5cc | 3577 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
3578 | |
3579 | return 0; | |
3580 | } | |
8dd5ea72 | 3581 | omap_postcore_initcall(omap_hwmod_setup_all); |
63c85238 | 3582 | |
63c85238 PW |
3583 | /** |
3584 | * omap_hwmod_enable - enable an omap_hwmod | |
3585 | * @oh: struct omap_hwmod * | |
3586 | * | |
74ff3a68 | 3587 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
3588 | * Returns -EINVAL on error or passes along the return value from _enable(). |
3589 | */ | |
3590 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
3591 | { | |
3592 | int r; | |
dc6d1cda | 3593 | unsigned long flags; |
63c85238 PW |
3594 | |
3595 | if (!oh) | |
3596 | return -EINVAL; | |
3597 | ||
dc6d1cda PW |
3598 | spin_lock_irqsave(&oh->_lock, flags); |
3599 | r = _enable(oh); | |
3600 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3601 | |
3602 | return r; | |
3603 | } | |
3604 | ||
3605 | /** | |
3606 | * omap_hwmod_idle - idle an omap_hwmod | |
3607 | * @oh: struct omap_hwmod * | |
3608 | * | |
74ff3a68 | 3609 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
3610 | * Returns -EINVAL on error or passes along the return value from _idle(). |
3611 | */ | |
3612 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
3613 | { | |
6da23358 | 3614 | int r; |
dc6d1cda PW |
3615 | unsigned long flags; |
3616 | ||
63c85238 PW |
3617 | if (!oh) |
3618 | return -EINVAL; | |
3619 | ||
dc6d1cda | 3620 | spin_lock_irqsave(&oh->_lock, flags); |
6da23358 | 3621 | r = _idle(oh); |
dc6d1cda | 3622 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 | 3623 | |
6da23358 | 3624 | return r; |
63c85238 PW |
3625 | } |
3626 | ||
3627 | /** | |
3628 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
3629 | * @oh: struct omap_hwmod * | |
3630 | * | |
74ff3a68 | 3631 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
3632 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
3633 | * the return value from _shutdown(). | |
3634 | */ | |
3635 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
3636 | { | |
6da23358 | 3637 | int r; |
dc6d1cda PW |
3638 | unsigned long flags; |
3639 | ||
63c85238 PW |
3640 | if (!oh) |
3641 | return -EINVAL; | |
3642 | ||
dc6d1cda | 3643 | spin_lock_irqsave(&oh->_lock, flags); |
6da23358 | 3644 | r = _shutdown(oh); |
dc6d1cda | 3645 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 | 3646 | |
6da23358 | 3647 | return r; |
63c85238 PW |
3648 | } |
3649 | ||
5e8370f1 PW |
3650 | /* |
3651 | * IP block data retrieval functions | |
3652 | */ | |
3653 | ||
63c85238 PW |
3654 | /** |
3655 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
3656 | * @oh: struct omap_hwmod * | |
3657 | * | |
3658 | * Return the powerdomain pointer associated with the OMAP module | |
3659 | * @oh's main clock. If @oh does not have a main clk, return the | |
3660 | * powerdomain associated with the interface clock associated with the | |
3661 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
3662 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
3663 | * success. | |
3664 | */ | |
3665 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
3666 | { | |
3667 | struct clk *c; | |
2d6141ba | 3668 | struct omap_hwmod_ocp_if *oi; |
f5dd3bb5 | 3669 | struct clockdomain *clkdm; |
f5dd3bb5 | 3670 | struct clk_hw_omap *clk; |
63c85238 PW |
3671 | |
3672 | if (!oh) | |
3673 | return NULL; | |
3674 | ||
f5dd3bb5 RN |
3675 | if (oh->clkdm) |
3676 | return oh->clkdm->pwrdm.ptr; | |
3677 | ||
63c85238 PW |
3678 | if (oh->_clk) { |
3679 | c = oh->_clk; | |
3680 | } else { | |
2d6141ba PW |
3681 | oi = _find_mpu_rt_port(oh); |
3682 | if (!oi) | |
63c85238 | 3683 | return NULL; |
2d6141ba | 3684 | c = oi->_clk; |
63c85238 PW |
3685 | } |
3686 | ||
f5dd3bb5 RN |
3687 | clk = to_clk_hw_omap(__clk_get_hw(c)); |
3688 | clkdm = clk->clkdm; | |
f5dd3bb5 | 3689 | if (!clkdm) |
d5647c18 TG |
3690 | return NULL; |
3691 | ||
f5dd3bb5 | 3692 | return clkdm->pwrdm.ptr; |
63c85238 PW |
3693 | } |
3694 | ||
db2a60bf PW |
3695 | /** |
3696 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
3697 | * @oh: struct omap_hwmod * | |
3698 | * | |
3699 | * Returns the virtual address corresponding to the beginning of the | |
3700 | * module's register target, in the address range that is intended to | |
3701 | * be used by the MPU. Returns the virtual address upon success or NULL | |
3702 | * upon error. | |
3703 | */ | |
3704 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
3705 | { | |
3706 | if (!oh) | |
3707 | return NULL; | |
3708 | ||
3709 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
3710 | return NULL; | |
3711 | ||
3712 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
3713 | return NULL; | |
3714 | ||
3715 | return oh->_mpu_rt_va; | |
3716 | } | |
3717 | ||
63c85238 PW |
3718 | /* |
3719 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
3720 | * for context save/restore operations? | |
3721 | */ | |
3722 | ||
63c85238 PW |
3723 | /** |
3724 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
3725 | * @oh: struct omap_hwmod * | |
3726 | * | |
3727 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
3728 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
3729 | * this IP block if it has dynamic mux entries. Eventually this | |
3730 | * should set PRCM wakeup registers to cause the PRCM to receive | |
3731 | * wakeup events from the module. Does not set any wakeup routing | |
3732 | * registers beyond this point - if the module is to wake up any other | |
3733 | * module or subsystem, that must be set separately. Called by | |
3734 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3735 | */ |
3736 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
3737 | { | |
dc6d1cda | 3738 | unsigned long flags; |
5a7ddcbd | 3739 | u32 v; |
dc6d1cda | 3740 | |
dc6d1cda | 3741 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3742 | |
3743 | if (oh->class->sysc && | |
3744 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3745 | v = oh->_sysc_cache; | |
3746 | _enable_wakeup(oh, &v); | |
3747 | _write_sysconfig(v, oh); | |
3748 | } | |
3749 | ||
dc6d1cda | 3750 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3751 | |
3752 | return 0; | |
3753 | } | |
3754 | ||
3755 | /** | |
3756 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
3757 | * @oh: struct omap_hwmod * | |
3758 | * | |
3759 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
3760 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
3761 | * events for this IP block if it has dynamic mux entries. Eventually | |
3762 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
3763 | * wakeup events from the module. Does not set any wakeup routing | |
3764 | * registers beyond this point - if the module is to wake up any other | |
3765 | * module or subsystem, that must be set separately. Called by | |
3766 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3767 | */ |
3768 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
3769 | { | |
dc6d1cda | 3770 | unsigned long flags; |
5a7ddcbd | 3771 | u32 v; |
dc6d1cda | 3772 | |
dc6d1cda | 3773 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3774 | |
3775 | if (oh->class->sysc && | |
3776 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3777 | v = oh->_sysc_cache; | |
3778 | _disable_wakeup(oh, &v); | |
3779 | _write_sysconfig(v, oh); | |
3780 | } | |
3781 | ||
dc6d1cda | 3782 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3783 | |
3784 | return 0; | |
3785 | } | |
43b40992 | 3786 | |
aee48e3c PW |
3787 | /** |
3788 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
3789 | * contained in the hwmod module. | |
3790 | * @oh: struct omap_hwmod * | |
3791 | * @name: name of the reset line to lookup and assert | |
3792 | * | |
3793 | * Some IP like dsp, ipu or iva contain processor that require | |
3794 | * an HW reset line to be assert / deassert in order to enable fully | |
3795 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3796 | * yet supported on this OMAP; otherwise, passes along the return value | |
3797 | * from _assert_hardreset(). | |
3798 | */ | |
3799 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
3800 | { | |
3801 | int ret; | |
dc6d1cda | 3802 | unsigned long flags; |
aee48e3c PW |
3803 | |
3804 | if (!oh) | |
3805 | return -EINVAL; | |
3806 | ||
dc6d1cda | 3807 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3808 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 3809 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3810 | |
3811 | return ret; | |
3812 | } | |
3813 | ||
3814 | /** | |
3815 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
3816 | * contained in the hwmod module. | |
3817 | * @oh: struct omap_hwmod * | |
3818 | * @name: name of the reset line to look up and deassert | |
3819 | * | |
3820 | * Some IP like dsp, ipu or iva contain processor that require | |
3821 | * an HW reset line to be assert / deassert in order to enable fully | |
3822 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3823 | * yet supported on this OMAP; otherwise, passes along the return value | |
3824 | * from _deassert_hardreset(). | |
3825 | */ | |
3826 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
3827 | { | |
3828 | int ret; | |
dc6d1cda | 3829 | unsigned long flags; |
aee48e3c PW |
3830 | |
3831 | if (!oh) | |
3832 | return -EINVAL; | |
3833 | ||
dc6d1cda | 3834 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3835 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 3836 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3837 | |
3838 | return ret; | |
3839 | } | |
3840 | ||
43b40992 PW |
3841 | /** |
3842 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
3843 | * @classname: struct omap_hwmod_class name to search for | |
3844 | * @fn: callback function pointer to call for each hwmod in class @classname | |
3845 | * @user: arbitrary context data to pass to the callback function | |
3846 | * | |
ce35b244 BC |
3847 | * For each omap_hwmod of class @classname, call @fn. |
3848 | * If the callback function returns something other than | |
43b40992 PW |
3849 | * zero, the iterator is terminated, and the callback function's return |
3850 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
3851 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
3852 | */ | |
3853 | int omap_hwmod_for_each_by_class(const char *classname, | |
3854 | int (*fn)(struct omap_hwmod *oh, | |
3855 | void *user), | |
3856 | void *user) | |
3857 | { | |
3858 | struct omap_hwmod *temp_oh; | |
3859 | int ret = 0; | |
3860 | ||
3861 | if (!classname || !fn) | |
3862 | return -EINVAL; | |
3863 | ||
3864 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
3865 | __func__, classname); | |
3866 | ||
43b40992 PW |
3867 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
3868 | if (!strcmp(temp_oh->class->name, classname)) { | |
3869 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
3870 | __func__, temp_oh->name); | |
3871 | ret = (*fn)(temp_oh, user); | |
3872 | if (ret) | |
3873 | break; | |
3874 | } | |
3875 | } | |
3876 | ||
43b40992 PW |
3877 | if (ret) |
3878 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
3879 | __func__, ret); | |
3880 | ||
3881 | return ret; | |
3882 | } | |
3883 | ||
2092e5cc PW |
3884 | /** |
3885 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
3886 | * @oh: struct omap_hwmod * | |
3887 | * @state: state that _setup() should leave the hwmod in | |
3888 | * | |
550c8092 | 3889 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
3890 | * (called by omap_hwmod_setup_*()). See also the documentation |
3891 | * for _setup_postsetup(), above. Returns 0 upon success or | |
3892 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
3893 | * in the wrong state. | |
2092e5cc PW |
3894 | */ |
3895 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
3896 | { | |
3897 | int ret; | |
dc6d1cda | 3898 | unsigned long flags; |
2092e5cc PW |
3899 | |
3900 | if (!oh) | |
3901 | return -EINVAL; | |
3902 | ||
3903 | if (state != _HWMOD_STATE_DISABLED && | |
3904 | state != _HWMOD_STATE_ENABLED && | |
3905 | state != _HWMOD_STATE_IDLE) | |
3906 | return -EINVAL; | |
3907 | ||
dc6d1cda | 3908 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
3909 | |
3910 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3911 | ret = -EINVAL; | |
3912 | goto ohsps_unlock; | |
3913 | } | |
3914 | ||
3915 | oh->_postsetup_state = state; | |
3916 | ret = 0; | |
3917 | ||
3918 | ohsps_unlock: | |
dc6d1cda | 3919 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
3920 | |
3921 | return ret; | |
3922 | } | |
c80705aa KH |
3923 | |
3924 | /** | |
3925 | * omap_hwmod_get_context_loss_count - get lost context count | |
3926 | * @oh: struct omap_hwmod * | |
3927 | * | |
e6d3a8b0 RN |
3928 | * Returns the context loss count of associated @oh |
3929 | * upon success, or zero if no context loss data is available. | |
c80705aa | 3930 | * |
e6d3a8b0 RN |
3931 | * On OMAP4, this queries the per-hwmod context loss register, |
3932 | * assuming one exists. If not, or on OMAP2/3, this queries the | |
3933 | * enclosing powerdomain context loss count. | |
c80705aa | 3934 | */ |
fc013873 | 3935 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
3936 | { |
3937 | struct powerdomain *pwrdm; | |
3938 | int ret = 0; | |
3939 | ||
e6d3a8b0 RN |
3940 | if (soc_ops.get_context_lost) |
3941 | return soc_ops.get_context_lost(oh); | |
3942 | ||
c80705aa KH |
3943 | pwrdm = omap_hwmod_get_pwrdm(oh); |
3944 | if (pwrdm) | |
3945 | ret = pwrdm_get_context_loss_count(pwrdm); | |
3946 | ||
3947 | return ret; | |
3948 | } | |
43b01643 | 3949 | |
9ebfd285 KH |
3950 | /** |
3951 | * omap_hwmod_init - initialize the hwmod code | |
3952 | * | |
3953 | * Sets up some function pointers needed by the hwmod code to operate on the | |
3954 | * currently-booted SoC. Intended to be called once during kernel init | |
3955 | * before any hwmods are registered. No return value. | |
3956 | */ | |
3957 | void __init omap_hwmod_init(void) | |
3958 | { | |
ff4ae5d9 | 3959 | if (cpu_is_omap24xx()) { |
9002e921 | 3960 | soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready; |
ff4ae5d9 PW |
3961 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3962 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3963 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
3964 | } else if (cpu_is_omap34xx()) { | |
9002e921 | 3965 | soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready; |
b8249cf2 KH |
3966 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3967 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3968 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
0385c582 | 3969 | soc_ops.init_clkdm = _init_clkdm; |
debcd1f8 | 3970 | } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { |
9ebfd285 KH |
3971 | soc_ops.enable_module = _omap4_enable_module; |
3972 | soc_ops.disable_module = _omap4_disable_module; | |
8f6aa8ee | 3973 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
b8249cf2 KH |
3974 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
3975 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
3976 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
0a179eaa | 3977 | soc_ops.init_clkdm = _init_clkdm; |
e6d3a8b0 RN |
3978 | soc_ops.update_context_lost = _omap4_update_context_lost; |
3979 | soc_ops.get_context_lost = _omap4_get_context_lost; | |
9fabc1a2 | 3980 | soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm; |
70f05be3 | 3981 | soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl; |
0f3ccb24 TL |
3982 | } else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() || |
3983 | soc_is_am43xx()) { | |
c8b428a5 AM |
3984 | soc_ops.enable_module = _omap4_enable_module; |
3985 | soc_ops.disable_module = _omap4_disable_module; | |
3986 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | |
409d7063 | 3987 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
1688bf19 | 3988 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; |
a5bf00cd | 3989 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; |
1688bf19 | 3990 | soc_ops.init_clkdm = _init_clkdm; |
9fabc1a2 | 3991 | soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm; |
2b96be3d | 3992 | soc_ops.xlate_clkctrl = _omap4_xlate_clkctrl; |
8f6aa8ee KH |
3993 | } else { |
3994 | WARN(1, "omap_hwmod: unknown SoC type\n"); | |
9ebfd285 KH |
3995 | } |
3996 | ||
70f05be3 TK |
3997 | _init_clkctrl_providers(); |
3998 | ||
9ebfd285 KH |
3999 | inited = true; |
4000 | } | |
68c9a95e TL |
4001 | |
4002 | /** | |
4003 | * omap_hwmod_get_main_clk - get pointer to main clock name | |
4004 | * @oh: struct omap_hwmod * | |
4005 | * | |
4006 | * Returns the main clock name assocated with @oh upon success, | |
4007 | * or NULL if @oh is NULL. | |
4008 | */ | |
4009 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) | |
4010 | { | |
4011 | if (!oh) | |
4012 | return NULL; | |
4013 | ||
4014 | return oh->main_clk; | |
4015 | } |